1364036 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種延遲電路，尤指一種不受溫度影響且具 有固定延遲時間之延遲電路。 【先前技術】 在如DRAM(動態隨機存取記憶體)的記憶體裝置中，rc(電 阻電容)時間追蹤是非常重要的一件事^ RC時間關係到整個延 遲電路的延遲時間，且具有較小的RC時間變化量對延遲電路來 說亦較好。一般記憶體的工作溫度大約在+100。(:〜_40。(:之間， 在此溫度下工作，RC時間的變化量將會非常的大。 第一圖係為習知延遲電路之電路圖，此延遲電路係可作為 輸出電路來使用。此延遲電路包含有複數組延遲級1〇1(圖中舉 例為五組）’各延遲級101包含一反相接收器（由PMOS電晶體BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a delay circuit, and more particularly to a delay circuit that is temperature-independent and has a fixed delay time. [Prior Art] In a memory device such as DRAM (Dynamic Random Access Memory), rc (resistance and capacitance) time tracking is a very important thing ^ RC time is related to the delay time of the entire delay circuit, and has A small amount of RC time variation is also good for the delay circuit. Typical memory operating temperatures are approximately +100. (:~_40. (: Between, working at this temperature, the amount of change in RC time will be very large. The first figure is a circuit diagram of a conventional delay circuit, which can be used as an output circuit. The delay circuit includes a complex array delay stage 1〇1 (exemplified by five groups in the figure) 'each delay stage 101 includes an inverting receiver (by PMOS transistor)
Pll、NMOS電晶體Nil以及電阻器IU所構成）、一電容器〇以 及二輸出反相器（由PMOS電晶體P12以及NMOS電晶體N12所 才冓成)所組成。於此延遲電路中，電阻器則與電容器〇 ^輸入訊_對於溫度改變賴化量以產 ^ 化無關之輸出訊號OUT。 興/皿度變 溫=工作特性會隨著溫細續，其於高 =:1會隨著溫度變化而改變，此並非為-良好的ίί 圖，id中訊卿、0卜02在不同溫度下之ί序 路之ί電流會降低，將增加第—圖中延S ^遲時間。第二圖中之溫度變化範圍係界定於 電 5 1364036 係發散，此即意味 盖，延1電路之缺撼，本發明人有感其未至臻完 i積，出克服’憑從事該項產業多年之經驗 遲電路，可改善上述各影響且具有蚊延遲時間之延 【發明内容】 由是，本發明之主要目的，即在於提供一種延遲電路，可 達到延遲時間不受溫度影響之功效者。 為達上述目的，本發明之技術實現如下： 種不受溫度影響且具有固定延遲時間之延遲電路，係包 含：一具有一電阻元件之反相接收器，該反相接收器含有一接 收一輸入訊號之輸入端、一與該電阻元件耦接之輸出端以及一 内部端點，一電容器，係與該反相接收器之輸出端耗接；一第 一電晶體’係含有與該反相接收器輸出端耦接之第一端子、一 控制端子以及一第二端子；一第二電晶體，係含有一第一端子、 一與該輸入訊號耦接之控制端子以及一與該第一電晶體第二端 子搞接之第二端子；以及一輸出反相器，係含有一與該第一電 晶體第二端子耦接之輸入端點以及一輸出端點，用以輸出一輸 出訊號；其中，該第一電晶體提供溫度變化對該反相接收器的 延遲時間的補償，且該第二電晶體係於該第一電晶體之第二端 子產生一軌對軌訊號。該延遲電路更包含有一第三電晶體，係 含有一第一端子、一與該反相接收器輸出端點耦接之控制端子 1364036 以及一該輸出反相器輸出節點耦接之第二端子。該第三電晶體 係用於增強對該輸出訊號下拉的能力。 本發明之另一實施例，即在提供一種延遲電路，係包含： 一具有一電阻元件之反相接收器，該反相接收器含有一接收一 輸入訊號之輸入端、一與該電阻元件耦接之輸出端以及一内部 端點；一電容器，係與該反相接收器之輸出端耦接；一第一電 晶體，係與該反相接收器輸出端以及該電容器耦接，該第一電 晶體之導通臨界電壓係隨溫度變化而改變；一第二電晶體，係 與該輸入訊號以及該第一電晶體耦接，用以於該第一電晶體上 提供一軌對軌訊號；以及一輸出反相器，係包含有一與該第一 電晶體與第二電晶體搞接之輸入端點以及一用以輸出該延遲電 路輸出訊號之輸出端點。該延遲電路更包含有了與該反相接收 器輸出端以及該輸出反相器輸出端點耦接之第三電晶體，用以 增強對該輸出訊號下拉的能力。 為讓本發明之上述和其它目的、特徵和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 於本發明延遲電路之實施例中，係使用一提供負溫度效應 之電晶體、該電晶體提供一軌對軌訊號之另一電晶體以及一增 強對延遲電路輸出訊號下拉能力之下拉電晶體。 第三圖係為本發明之電路圖，該延遲電路300包含有一組或 組以上之延遲級3〇1。每一延遲級3〇1具有一反相接收器（由 PMOS電晶體P3卜NMOS電晶體N31以及電阻元件R3所構成）、 7 1364036 一電容器C3、一PMOS電晶體P33以及NMOS電晶體N33-N34。 本發明之反相接收器係由一 ？]^〇8電晶體、—NM〇s，晶體以 及一電阻元件所構成，與習知由一PM〇s電晶體以及一nm〇S 電晶體組成之CMOS反相器不同。 PMOS電.晶體P31之源極與電源供應端v]^輕接，其閘極與 輸入訊號IN耦接且其汲極係與電阻元件幻之一端耦接。 電晶體N31之源極係接地，其閘極與輸入訊號m耦接且其汲極 鲁 係與電阻疋件113之另一端(即節點Q3)輕接。電阻元件R3係耦接 於PMOS電晶體P31之汲極以及NM〇s電晶體N3丨之汲極之間， 且電容器C3係耦接於節點q3以及接地端之間。pM〇s電晶體 P33之源極係與節點q3耦接，其閘極係接地且其汲極係與節點 Q3耦接。NMOSf：B曰曰體N33之源極係接地，其閘極與輸入訊號 IN耦接且其汲極係與節點Q3’耦接。pM〇s電晶體p32之源極係 與電源供應端VDD#接，其閘極係與節點q3,輕接且其沒極係 與輸^訊號01耦接。NM0S電晶體N32之源極係接地，其閘極 φ 係與節點Q3轉接且其汲極係與輸出訊號01輕接。NM0S電晶 體N34之源極係接地，其雜係與節點q说接且其没極係與輸 出訊號01耦接。 於環i兄/m度較低時，電晶體之飽和電流會較高，因此節點 Q3的電壓位準會被拉升的較快，但pM〇s電晶體之臨界電 壓=變高丄故PM0S電晶體P33稱後才會被導通。相反的，於環 兄’皿度較〶時，電晶體之飽和電流會較低，因此節點印的電應 位準會被拉升的較慢，但PM〇s電晶體p33之臨界電壓會變低， 故PM0S電晶體|>33很快就會被導通。換句話說，當環境溫度升 8 1364036 高時，PMOS電晶體P33較低的導通電壓會補償反相接收器與輸 出反相器之低飽和電流，並使溫度變化不影響其輸出。PMOS 電晶體P33之負溫度效應會降低於低溫時PMOS電晶體P33之延 遲時間（第四圖中節點Q 3與Q3，孓間）大於高溫時PMO S電晶體 P33之延遲時間的程度，即環境溫度愈高，PMOS電晶體P33之 延遲時間愈小。 NMOS電晶體N33係藉由PMOS電晶體P33來補償降低之臨 界電壓，並於節點Q3’產生一軌對軌(rail-to-mil)波形的低邏輯訊 號。當輸入訊號IN為高邏輯位準時，節點Q3為低邏輯位準 (0V)，且NM0S電晶體N33係為導通，用以將節點Q3’之位準下 拉至低邏輯位準。 NMOS電晶體N34係用以增強對輸出訊號01的下拉能力， 當輸入訊號IN為向邏輯位準時’輸出訊號〇1會被電晶體 P32拉升至為高邏輯位準。當輸入訊號取為低邏輯位準時，輸 出訊號01會被NMOS電晶體N32、N34下拉至為低邏輯位準。 第四圖顯示第三圖中訊號Q3、Q3,、01、〇2在不同溫度下 之時序圖，環境溫度於+1〇〇。(：〜_4〇。(：之間時，輸出訊號〇卜〇2 會比第二®巾之輸出訊號⑴、〇2為㈣。此即意味輸出訊號 ΟΙ、02、OUT之結果與溫度變化無關。此外，於環境溫度變化 時’ PMOS電晶體p33會對節點Q3,提供溫度補償。舉例來說， 於T=5ns時，當溫度上升時，節點q3,之電壓位準會报快上 但節點Q3之電壓位準會上升的較慢。 、’ 第五圖係為本發明延遲電路之另一實施電路圖，該 路500包含有-組或—組以上之延遲級跡每—延遲級^具有 9 1364036 一反相接收器(由PMOS電晶體P51、NMOS電晶體N51以及電阻 元件R5所構成）、一電容器C5、一NMOS電晶體N53、一輸出反 相器（由PMOS電晶體P52以及NMOS電晶體N52所構成）以及 PMOS電晶體Ρ53·Ρ54。節點Q5與Q5’為内部節點，pm〇S電晶 體Ρ5卜NMOS電晶體Ν5卜電容器C5、NMOS電晶體Ν53、PMOS 電晶體P52、NMOS電晶體N52以及PMOS電晶體P53-P54與第三 圖中類似的元件具有相似之功能，故於此不再贅述。電阻元件 R5係麵接於節點Q5以及NMOS電晶體N51之汲極之間。 第六圖係為係為本發明延遲電路之又一實施電路圖，該延 遲電路600包含有一組或一組以上之延遲級6〇1。每一延遲級6〇1 具有一反相接收器（由PMOS電晶體P61、NMOS電晶體N61以及 電阻元件R6所構成）、一電容器C6、一PMOS電晶體P63、一輸 出反相器（由PMOS電晶體P62以及NMOS電晶體N62所構成)以 及NMOS電晶體N63-N64。節點Q6與Q6’為内部節點，PMOS電 晶體P61、NMOS電晶體N61、電容器C6、PMOS電晶體P63、 PMOS電晶體P62、NMOS電晶體N62以及NMOS電晶體 N63-N64與第三圖中類似的元件具有相似之功能，故於此不再 贅述。電阻元件R6係耦接於節點Q6以及反相接收器之輸出端之 間。 第七圖係為係為本發明延遲電路之再一實施電路圖，該延 遲電路700包含有一組或一組以上之延遲級701。每一延遲級701 具有一反相接收器（由PMOS電晶體P7卜NMOS電晶體N71以及 電阻元件R7所構成）、一電容器C7、一NMOS電晶體N73、一輸 出反相器（由PMOS電晶體P72以及NMOS電晶體N72所構成)以 10 1364036 及PMOS電晶體P73-P74。節點Q7與Q7,為内部節點，PM0S電 晶體P71、NMOS電晶體N71、電容器C7、NMOS電晶體N73、 PMOS電晶體P72、NMOS電晶體N72以及PMOS電晶體P73-P74 與第三圖中類似的元件具有相似之功能，故於此不再贅述。電 阻元件R7係耦接於節點Q7以及反相接收器之輸出端之間。 在上述實施例中’電容器(C3、C5、C6以及C7)係耦接於内 部節點以及一參考位準(接地端或VDD)之間，如電容器C5(第五 圖中)係耦接於節電Q5以及電源供應端VDD之間。 在上述實施例中，其RC時間係與溫度變化無關，因此，本 發明之延遲電路具有不受溫度影響之固定的延遲時間。 雖然本發明已以較佳實施例揭露如上’然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内， 當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之 申請專利範圍所界定者為準。 【圖式簡單說明】 第一圖係為習知延遲電路之電路圖。 第二圖顯示第一圖中訊號Q1、〇卜02在不同溫度下之時序圖。 第三圖係為本發明之電路圖。 第四圖顯示第三圖中訊號q3 、Q3’、0卜〇2在不同溫度下之時 序圖。 第五圖係為本發明之另一實施電路圖。 第八圖係為係為本發明之又一實施電路圖。 第七圖係為係為本發明之再一實施電路圖。 1364036 【主要元件符號說明】Pll, NMOS transistor Nil and resistor IU are formed, a capacitor 〇 and a two-output inverter (formed by PMOS transistor P12 and NMOS transistor N12). In this delay circuit, the resistor and the capacitor 输入 ^ input signal output voltage OUT irrespective of the temperature change. Xing / dish temperature change = working characteristics will continue with the temperature, its height =: 1 will change with temperature, this is not - good ίί map, id Zhongxun, 0 Bu 02 at different temperatures The current of the ί sequence will decrease, which will increase the delay time in the first graph. The temperature variation range in the second figure is defined as the divergence of electricity 5 1364036, which means that the cover is missing, and the inventor feels that it has not finished the accumulation of the product. Years of experience late circuit can improve the above effects and have the delay of mosquito delay time. SUMMARY OF THE INVENTION The main object of the present invention is to provide a delay circuit capable of achieving the effect of delay time without being affected by temperature. In order to achieve the above object, the technology of the present invention is implemented as follows: a delay circuit that is not affected by temperature and has a fixed delay time, and includes: an inverting receiver having a resistive element, the inverting receiver including a receiving input An input end of the signal, an output coupled to the resistive element, and an internal terminal, a capacitor is coupled to the output of the inverting receiver; a first transistor 'includes the inverted receive The first terminal of the device is coupled to the first terminal, the control terminal and the second terminal; the second transistor comprises a first terminal, a control terminal coupled to the input signal, and a first transistor The second terminal is connected to the second terminal; and an output inverter includes an input terminal coupled to the second terminal of the first transistor and an output terminal for outputting an output signal; The first transistor provides a temperature variation to compensate for the delay time of the inverting receiver, and the second transistor system generates a rail-to-rail signal at the second terminal of the first transistor. The delay circuit further includes a third transistor including a first terminal, a control terminal 1364036 coupled to the output terminal of the inverting receiver, and a second terminal coupled to the output node of the output inverter. The third transistor is used to enhance the ability to pull down the output signal. Another embodiment of the present invention provides a delay circuit including: an inverting receiver having a resistive element, the inverting receiver including an input receiving an input signal, and a coupling with the resistive element An output terminal and an internal terminal; a capacitor coupled to the output of the inverting receiver; a first transistor coupled to the inverting receiver output and the capacitor, the first The turn-on threshold voltage of the transistor changes with temperature; a second transistor is coupled to the input signal and the first transistor for providing a track-to-rail signal on the first transistor; An output inverter includes an input terminal connected to the first transistor and the second transistor, and an output terminal for outputting the output signal of the delay circuit. The delay circuit further includes a third transistor coupled to the output of the inverting receiver and the output terminal of the output inverter for enhancing the ability to pull down the output signal. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] In the embodiment of the delay circuit of the present invention, a transistor for providing a negative temperature effect, another transistor for providing a track-to-rail signal, and an enhanced pull-down capability for the output signal of the delay circuit are used. Pull down the transistor. The third diagram is a circuit diagram of the present invention, and the delay circuit 300 includes one or more sets of delay stages 〇1. Each delay stage 3〇1 has an inverting receiver (consisting of PMOS transistor P3, NMOS transistor N31 and resistor element R3), 7 1364036, a capacitor C3, a PMOS transistor P33, and an NMOS transistor N33-N34. . The inverting receiver of the present invention is composed of one? It is composed of a transistor, a NM〇s, a crystal, and a resistive element, which is different from a conventional CMOS inverter composed of a PM〇s transistor and a nm〇S transistor. PMOS. The source of the crystal P31 is connected to the power supply terminal v]^, the gate is coupled to the input signal IN, and the drain is coupled to one end of the resistor element. The source of the transistor N31 is grounded, its gate is coupled to the input signal m, and its drain is lightly connected to the other end of the resistor element 113 (i.e., node Q3). The resistor element R3 is coupled between the drain of the PMOS transistor P31 and the drain of the NM〇s transistor N3, and the capacitor C3 is coupled between the node q3 and the ground. The source of the pM〇s transistor P33 is coupled to the node q3, the gate of which is grounded and whose drain is coupled to the node Q3. The source of the NMOSf:B body N33 is grounded, the gate is coupled to the input signal IN and the drain is coupled to the node Q3'. The source of the pM〇s transistor p32 is connected to the power supply terminal VDD#, and the gate is connected to the node q3, and its non-polar system is coupled to the input signal 01. The source of the NM0S transistor N32 is grounded, and its gate φ is switched to the node Q3 and its drain is connected to the output signal 01. The source of the NM0S transistor N34 is grounded, and the hybrid is connected to the node q and its pedestal is coupled to the output signal 01. When the ring i brother / m degree is low, the saturation current of the transistor will be higher, so the voltage level of the node Q3 will be pulled up faster, but the threshold voltage of the pM〇s transistor = become higher, so PM0S The transistor P33 is called after it is turned on. On the contrary, when the ring brother's degree is relatively low, the saturation current of the transistor will be lower, so the node printed electricity should be pulled up slowly, but the threshold voltage of the PM〇s transistor p33 will change. Low, so PM0S transistor|>33 will be turned on very soon. In other words, when the ambient temperature rises by 8 1364036, the lower turn-on voltage of the PMOS transistor P33 compensates for the low saturation current of the inverting receiver and the output inverter, and the temperature change does not affect its output. The negative temperature effect of PMOS transistor P33 is reduced to the delay time of PMOS transistor P33 at low temperature (nodes Q 3 and Q3 in the fourth figure, inter-turn) is greater than the delay time of PMO S transistor P33 at high temperature, ie environment The higher the temperature, the smaller the delay time of the PMOS transistor P33. The NMOS transistor N33 compensates for the reduced threshold voltage by the PMOS transistor P33 and generates a low-logic signal of a rail-to-mil waveform at the node Q3'. When the input signal IN is at a high logic level, the node Q3 is at a low logic level (0V), and the NM0S transistor N33 is turned on to pull the level of the node Q3' down to a low logic level. The NMOS transistor N34 is used to enhance the pull-down capability of the output signal 01. When the input signal IN is at the logic level, the output signal 〇1 is pulled up to a high logic level by the transistor P32. When the input signal is taken to a low logic level, the output signal 01 is pulled down to the low logic level by the NMOS transistors N32, N34. The fourth figure shows the timing diagram of signals Q3, Q3, 01, and 〇2 at different temperatures in the third figure. The ambient temperature is +1 〇〇. (:~_4〇. (: When the signal is output, the output signal is 2 (1) and 〇2 is (4). This means that the output signals ΟΙ, 02, OUT are independent of temperature changes. In addition, when the ambient temperature changes, the PMOS transistor p33 provides temperature compensation for node Q3. For example, at T=5 ns, when the temperature rises, the voltage level of node q3 will be reported faster but the node The voltage level of Q3 will rise slowly. 'The fifth figure is another implementation circuit diagram of the delay circuit of the present invention. The path 500 includes a delay group of -group or above-group delay-levels having 9 1364036 An inverting receiver (consisting of PMOS transistor P51, NMOS transistor N51 and resistor element R5), a capacitor C5, an NMOS transistor N53, an output inverter (by PMOS transistor P52 and NMOS transistor) N52 is formed) and PMOS transistor Ρ53·Ρ54. Nodes Q5 and Q5' are internal nodes, pm〇S transistor Ρ5 NMOS transistor Ν5 capacitor C5, NMOS transistor Ν53, PMOS transistor P52, NMOS transistor N52 And the PMOS transistor P53-P54 is similar to the element in the third figure. There is a similar function, so it will not be described here. The resistive element R5 is connected between the node Q5 and the drain of the NMOS transistor N51. The sixth figure is another implementation circuit diagram of the delay circuit of the present invention. The delay circuit 600 includes one or more sets of delay stages 6〇1. Each delay stage 6〇1 has an inverting receiver (consisting of a PMOS transistor P61, an NMOS transistor N61, and a resistive element R6), Capacitor C6, a PMOS transistor P63, an output inverter (consisting of PMOS transistor P62 and NMOS transistor N62) and NMOS transistors N63-N64. Nodes Q6 and Q6' are internal nodes, PMOS transistor P61, The NMOS transistor N61, the capacitor C6, the PMOS transistor P63, the PMOS transistor P62, the NMOS transistor N62, and the NMOS transistor N63-N64 have similar functions to those of the third figure, and thus will not be described again. The component R6 is coupled between the node Q6 and the output of the inverting receiver. The seventh figure is a further implementation circuit diagram of the delay circuit of the present invention, the delay circuit 700 includes one or more sets of delay stages. 701. Each extension Stage 701 has an inverting receiver (consisting of PMOS transistor P7, NMOS transistor N71 and resistor element R7), a capacitor C7, an NMOS transistor N73, and an output inverter (by PMOS transistor P72 and NMOS). The transistor N72 is composed of 10 1364036 and PMOS transistors P73-P74. Nodes Q7 and Q7 are internal nodes, and PM0S transistor P71, NMOS transistor N71, capacitor C7, NMOS transistor N73, PMOS transistor P72, NMOS transistor N72, and PMOS transistor P73-P74 are similar to those in the third figure. The components have similar functions and will not be described here. The resistor element R7 is coupled between the node Q7 and the output of the inverting receiver. In the above embodiment, the capacitors (C3, C5, C6, and C7) are coupled between the internal node and a reference level (ground or VDD), such as capacitor C5 (figure 5) coupled to power saving. Q5 and the power supply terminal VDD. In the above embodiment, the RC time is independent of the temperature change, and therefore, the delay circuit of the present invention has a fixed delay time which is not affected by temperature. Although the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. [Simple Description of the Drawings] The first figure is a circuit diagram of a conventional delay circuit. The second figure shows the timing diagram of the signals Q1 and 102 in the first graph at different temperatures. The third figure is a circuit diagram of the present invention. The fourth figure shows the timing diagram of the signals q3, Q3', and 0 in the third diagram at different temperatures. The fifth drawing is another circuit diagram of the present invention. The eighth drawing is a further embodiment circuit diagram of the present invention. The seventh drawing is a circuit diagram of still another embodiment of the present invention. 1364036 [Main component symbol description]
101 :延遲級 C1 :電容器 R1 :電阻元件 N11-N12、P11-P12 : 電晶體 300 :延遲電路 301 :延遲級 C3 :電容器 R3 :電阻元件 P31-P33 ' N31-N34 ： 電晶體 500 :延遲電路 501 :延遲級 C5 :電容器 R5 :電阻元件 N51-N53、P51-P54 :電晶體 600 :延遲電路 601 :延遲級 C6 :電容器 R6 :電阻元件 N61-N64、P61-P63 :電晶體 700 :延遲電路 701 :延遲級 C7 :電容器 R7 :電阻元件 N71-N73、P71-P74 :電晶體101: delay stage C1: capacitor R1: resistance element N11-N12, P11-P12: transistor 300: delay circuit 301: delay stage C3: capacitor R3: resistance element P31-P33 'N31-N34: transistor 500: delay circuit 501: delay stage C5: capacitor R5: resistance element N51-N53, P51-P54: transistor 600: delay circuit 601: delay stage C6: capacitor R6: resistance element N61-N64, P61-P63: transistor 700: delay circuit 701: Delay stage C7: Capacitor R7: Resistive elements N71-N73, P71-P74: Transistor