TWI890460B - Voltage level shifter - Google Patents

Abstract

A voltage level shifter includes a first voltage adjustment unit, a second voltage adjustment unit, a first latch unit and an output unit. The first voltage adjustment unit and the second voltage adjustment unit respectively receive first and second input signals and generate first and second adjustment signals respectively. The first latch unit receives the first and second adjustment signals and generates a first latch signal accordingly. The output unit generates an output signal according to the first latch signal, an input voltage and a control signal. A high logic level voltage of the output signal is greater than the respective high logic level voltages of the first input signal and the second input signal. Wherein, the first voltage adjustment unit and the second voltage adjustment unit are each a capacitively coupled voltage adjustment unit and each includes an input capacitor. The input capacitor has no capacitance to ground at one end.

Description

Voltage level shifter

The present invention relates to a shifter, and in particular to a voltage level shifter.

Conventional voltage level shifters are widely used in circuits across various fields. They are primarily used to convert signal voltage levels (for example, converting I/O signals from a low supply voltage domain to a high supply voltage domain, and vice versa) to provide output signals with appropriate voltage levels for proper operation of subsequent circuits.

However, during the voltage level conversion process, the voltage level shifter's internal electronic components, such as transistors, need to withstand high voltage differences. Therefore, these components are almost always high-voltage-difference-tolerant components, meaning they must be large to perform the voltage level conversion. However, due to the large size of these components and the need for a large circuit area to separate high-voltage and low-voltage related circuits during layout, existing voltage level shifters have a large circuit area. Furthermore, high-voltage-difference-tolerant transistors vary in transition speed due to variations in process, voltage, and temperature, resulting in a large propagation delay in existing voltage level shifters. Furthermore, high-voltage-difference electronic components are easily affected by the conduction of parasitic elements, and high-voltage-difference electronic components can only be manufactured using high-voltage-resistant processes, resulting in high manufacturing costs for existing voltage level shifters.

Therefore, the object of the present invention is to provide a voltage level shifter with a smaller circuit area, lower manufacturing cost, and smaller propagation delay, so as to overcome the shortcomings of the prior art.

Therefore, the voltage level shifter of the present invention includes a first voltage adjustment unit, a second voltage adjustment unit, a first latch unit, and an output unit.

The first voltage adjustment unit receives a first input signal and generates an amplified first adjustment signal accordingly. The second voltage adjustment unit receives a second input signal and generates an amplified second adjustment signal accordingly. The first latching unit is coupled to the first voltage adjustment unit and the second voltage adjustment unit to receive the first adjustment signal and the second adjustment signal, respectively, and generates a first latching signal based on the first adjustment signal and the second adjustment signal. The output unit is coupled to the first latch unit to receive the first latch signal and generates an output signal based on the first latch signal, an input voltage, and a control signal. The high logic level of the output signal is greater than the high logic level of each of the first input signal and the second input signal. The first voltage adjustment unit and the second voltage adjustment unit are each a capacitively coupled voltage adjustment unit and each include an input capacitor, one end of which has no capacitance to ground.

In some embodiments, in the voltage level shifter of the present invention, the second input signal and the first input signal are mutually inverse signals, the input capacitor is a high-voltage parasitic capacitor and has a first terminal and a second terminal without a capacitance to ground, the first voltage adjustment unit and the second voltage adjustment unit are symmetrical and each further includes: a first buffer gate having a first terminal receiving a corresponding one of the first input signal and the second input signal, and a second terminal coupled to the first terminal of the corresponding input capacitor and outputting a buffer signal; a first transistor having a first terminal, a second terminal coupled to a first voltage terminal, and a second terminal coupled to the second terminal of the input capacitor to output a buffer signal; A control terminal for receiving the buffer signal; a second transistor having a first terminal coupled to the first latch unit and outputting a corresponding one of the first adjustment signal and the second adjustment signal, a second terminal coupled to the first terminal of the first transistor, and a control terminal for receiving a corresponding one of a first switching signal and a second switching signal; a first resistor coupled between a second voltage terminal and the first terminal of the second transistor; a second resistor coupled between the second voltage terminal and the second terminal of the second transistor; and a clamping circuit coupled between the control terminal and the first voltage terminal of the first transistor for clamping the erroneous buffer signal.

In some embodiments, in the voltage level shifter of the present invention, the voltage at the second voltage terminal is greater than or less than the voltage at the first voltage terminal.

In some embodiments, the voltage level shifter of the present invention further includes a signal adjustment unit that receives an input signal and is coupled to the first voltage terminal. The signal adjustment unit detects whether a rising edge of the input signal is within a slope range of a rising voltage at the first voltage terminal. If the detection result is yes, the signal adjustment unit adjusts the rising edge position of the input signal to generate the first input signal and the second input signal, which are output to the first voltage adjustment unit and the second voltage adjustment unit, respectively. The rising edge position of the first input signal is not within the slope range of a rising voltage at the first voltage terminal.

In some embodiments, the signal adjustment unit of the voltage level shifter of the present invention includes: a detection circuit coupled to the first voltage terminal and detecting the voltage of the first voltage terminal to generate a detection signal; and a signal adjustment circuit receiving the input signal and coupled to the detection circuit to receive the detection signal, and generating the first input signal and the second input signal based on the input signal, the detection signal, and the control signal.

In some embodiments, the detection circuit of the voltage level shifter of the present invention includes: a capacitor having a first terminal coupled to the first voltage terminal and a second terminal; a first current mirror coupled to the second terminal of the capacitor; a second current mirror coupled to the first current mirror; and a current source coupled between the second current mirror and a low voltage terminal. A common node between the current source and the second current mirror outputs the detection signal.

In some embodiments, the signal adjustment circuit of the voltage level shifter of the present invention includes: a logic gate, which receives the input signal and is coupled to the detection circuit to receive the detection signal, and generates a logic signal based on the input signal and the detection signal; and an RS flip-flop, which receives the control signal and is coupled to the logic gate to receive the logic signal, and generates the first input signal and the second input signal based on the logic signal and the control signal.

In some embodiments, the first latch unit of the voltage level shifter of the present invention includes: a third transistor having a first terminal coupled to a second voltage terminal, a second terminal, and a control terminal coupled to the first voltage adjustment unit to receive the first adjustment signal; a fourth transistor having a first terminal coupled to the second voltage terminal, a second terminal, and a control terminal coupled to the second voltage adjustment unit to receive the second adjustment signal; and a latch circuit coupled to the second terminals of the third transistor and the fourth transistor for latching the potential of one of the second terminals of the third transistor and the fourth transistor to generate the first latch signal.

In some embodiments, the output unit of the voltage level shifter of the present invention includes: a second buffer gate having a first end coupled to the first latch unit to receive the first latch signal, a second end coupled to a first voltage end, a third end coupled to a second voltage end, and an output end for outputting a buffer control signal; a fifth transistor having a first end for receiving the input voltage, a second end coupled to the first voltage end and outputting the output signal, and a control end coupled to the output end of the second buffer gate to receive the buffer control signal; and a sixth transistor having a first end coupled to the second end of the fifth transistor, a second end connected to ground, and a control end for receiving the control signal.

In some embodiments, the second input signal of the voltage level shifter of the present invention is a synchronous signal with the first input signal, the input capacitor has a first terminal and a second terminal without a ground capacitance, the second terminal of the input capacitor outputs a corresponding one of the first adjustment signal and the second adjustment signal, and the first voltage adjustment unit and the second voltage adjustment unit each further include: a buffer gate having a receiving A first terminal corresponding to one of the first input signal and the second input signal, and a second terminal coupled to the first terminal of the corresponding input capacitor and outputting a buffer signal; and a clamping circuit coupled between a corresponding one of a first voltage terminal and a second voltage terminal and the second terminal of the corresponding input capacitor, for clamping the corresponding one of the erroneous first adjustment signal and the second adjustment signal.

In some embodiments, in the voltage level shifter of the present invention, the potentials of the first adjustment signal and the second adjustment signal respectively track the potential of the first voltage terminal.

In some embodiments, the clamping circuit of the voltage level shifter of the present invention includes: a first transistor and a second transistor connected in series between a corresponding one of the first voltage terminal and the second voltage terminal and the corresponding second end of the input capacitor; and a resistor coupled between a corresponding one of the first voltage terminal and the second voltage terminal and the corresponding second end of the input capacitor.

In some embodiments, the first voltage adjustment unit and the second voltage adjustment unit of the voltage level shifter of the present invention each further include: a third transistor having a first end coupled to the second end of the corresponding input capacitor, a second end coupled to the corresponding resistor, and a control end; wherein the control end of the third transistor of the first voltage adjustment unit is coupled to the second end of the third transistor of the second voltage adjustment unit, and the control end of the third transistor of the second voltage adjustment unit is coupled to the second end of the third transistor of the first voltage adjustment unit.

In some embodiments, the first latch unit of the voltage level shifter of the present invention includes: a fourth transistor having a first terminal coupled to the second voltage terminal, a second terminal, and a control terminal coupled to the first voltage adjustment unit to receive the first adjustment signal, the fourth transistor being a P-type metal oxide semiconductor field effect transistor; a fifth transistor having a first terminal coupled to the second terminal of the fourth transistor, a second terminal coupled to the first voltage adjustment unit, and a control terminal coupled to the first voltage adjustment unit to receive the first adjustment signal; The fifth transistor comprises an N-type metal oxide semiconductor field effect transistor (MOSFET), a second terminal connected to the first voltage terminal, and a control terminal coupled to the second voltage adjustment unit to receive the second adjustment signal; an output capacitor coupled between the first voltage terminal and the second voltage terminal; and a latch circuit coupled to the first terminal of the fifth transistor for latching the potential of the first terminal of the fifth transistor to generate the first latch signal.

In some embodiments, the output unit of the voltage level shifter of the present invention includes: an inverter having a first terminal coupled to the first latch unit to receive the first latch signal, and a second terminal outputting an inverted signal; a sixth transistor having a first terminal receiving the input voltage, a second terminal coupled to the first voltage terminal and outputting the output signal, and a control terminal coupled to the second terminal of the inverter to receive the inverted signal; and a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, a second terminal connected to ground, and a control terminal receiving the control signal.

In some embodiments, the voltage level shifter of the present invention further includes: a third voltage adjustment unit coupled to the second terminal of the inverter to receive the inverted signal and generate an amplified third adjustment signal accordingly; a fourth voltage adjustment unit coupled to the second terminal of the inverter to receive the inverted signal and generate an amplified fourth adjustment signal accordingly; and a second latching unit coupled to the third and fourth voltage adjustment units to receive the third and fourth adjustment signals, respectively, and generate a second latching signal based on the third and fourth adjustment signals.

1.1’: Voltage level shifter

2: Signal conditioning unit

3.11: First voltage adjustment unit

4.12: Second voltage adjustment unit

5.13: First Locking Unit

6, 14: Output unit

15: Third voltage adjustment unit

16: Fourth voltage adjustment unit

17: Second locking unit

21: Detection Circuit

22: Signal conditioning circuit

31, 41: First buffer gate

32, 42: Input capacitor

33, 43: First transistor

34, 44: Second transistor

35, 45: First resistor

36, 46: Second resistor

37, 47: Clamping circuit

51: Third transistor

52: Fourth transistor

53: Lock circuit

61: Second buffer gate

62: Fifth transistor

63: Sixth transistor

111, 121: Buffer Gate

112, 122: Input capacitor

113, 123: Clamping circuit

114, 124: First transistor

115, 125: Second transistor

116, 126: Resistors

117, 127: Third transistor

131: Fourth transistor

132: Fifth transistor

133: Output capacitor

134: Lock circuit

141: Inverter

142: Sixth transistor

143: Seventh transistor

171: Inverter

211: Capacitor

212: First Current Mirror

213: Second Current Mirror

214: Current Source

221:Logic Gate

222: RS flip-flop

N: Common nodes

As1, As1’: First adjustment signal

As2, As2’: Second adjustment signal

As3: Third adjustment signal

As4: Fourth adjustment signal

Bc: Buffer control signal

Boost: Second voltage terminal

Ds: Detection signal

in, in1: first input signal

inb, in2: second input signal

IN: Input signal

Is: Anti-belief sign

Lat1: First lock signal

Lat2: Second lock signal

LG: Control signal

Ls: Logic signal

LX: First voltage terminal

M1, M2: Metal wire

Q, /Q: output terminal

R: Second receiving end

S: First receiving end

S1: First switching signal

S2: Second switching signal

t1, t2, t3: time points

Vin: Input voltage

Vdd: supply voltage

Vout: output signal

Other features and benefits of the present invention will be clearly demonstrated in the embodiments with reference to the accompanying drawings, in which: Figure 1 is a block diagram illustrating an embodiment of the voltage level shifter of the present invention; Figure 2 is a circuit diagram illustrating a signal adjustment unit of the embodiment; Figure 3 is a circuit diagram illustrating a first voltage adjustment unit, a second voltage adjustment unit, a first latch unit, and an output unit of the embodiment; Figures 4A, 4B, and 4C are schematic diagrams illustrating the layout of an input capacitor of the embodiment; Figure 5 is a waveform diagram illustrating a first input signal, a second input signal, a signal at a first voltage terminal, and a second input signal of the embodiment. Waveforms of a first adjustment signal, a second adjustment signal, a first switching signal, a second switching signal, a first latching signal, and a control signal; FIG6 is a block diagram illustrating another embodiment of the voltage level shifter of the present invention; FIG7 is a circuit diagram illustrating a first voltage adjustment unit, a second voltage adjustment unit, a first latching unit, and an output unit of the another embodiment; FIG8 is a circuit diagram illustrating another implementation of the first voltage adjustment unit and the second voltage adjustment unit of the another embodiment; and FIG9 is a circuit block diagram illustrating yet another embodiment of the voltage level shifter of the present invention.

The present invention will be described in detail through the following embodiments and accompanying drawings to help those skilled in the art understand the purpose, features, and effectiveness of the present invention. It should be noted that in the following description and claims, the terms "including" and "comprising" are used in an open-ended manner and should not be construed as closed-ended terms such as "consisting of." Furthermore, the term "coupled" is intended to indicate either an indirect or direct coupling. Thus, if one device is coupled to another, the connection may be through a direct coupling or an indirect coupling via other devices and connections. Furthermore, in the following description and claims, terms such as "first," "second," and "third" are used to distinguish between elements and are not intended to limit the elements themselves or indicate a specific ordering of the elements. Before the present invention is described in detail, it should be noted that in the following description, similar components in different embodiments are represented by the same reference numerals.

1 to 3 illustrate an embodiment of a voltage level shifter 1 of the present invention. The voltage level shifter 1 includes a signal adjustment unit 2, a first voltage adjustment unit 3, a second voltage adjustment unit 4, a first latch unit 5, and an output unit 6.

The signal conditioning unit 2 receives an input signal IN and is coupled to a first voltage terminal LX. It detects whether a rising edge of the input signal IN is within a rising slope of the voltage at the first voltage terminal LX. If the detection result is yes, the rising edge of the input signal IN is adjusted to generate a first input signal in and a second input signal inb. The second input signal inb is an inverse signal to the first input signal in. The rising edge of the first input signal IN is not located within the slope of the rising voltage at the first voltage terminal LX. This prevents the first latch unit 5 from failing to switch normally due to the rising edge of the input signal IN being located within the slope of the rising voltage at the first voltage terminal LX (in which case the first transistors 33 and 43 in FIG. 3 cannot conduct, and the first voltage adjustment unit 3 and the second voltage adjustment unit 4 cannot operate normally). The voltage at the first voltage terminal LX, for example, ranges from 0V to 25V. In this embodiment, the signal adjustment unit 2 includes a detection circuit 21 and a signal adjustment circuit 22.

The detection circuit 21 is coupled to the first voltage terminal LX and detects the voltage of the first voltage terminal LX to generate a detection signal Ds. In this embodiment, the detection circuit 21 includes a capacitor 211, a first current mirror 212, a second current mirror 213, and a current source 214.

The capacitor 211 has a first terminal coupled to the first voltage terminal LX and a second terminal. The first current mirror 212 is coupled to the second terminal of the capacitor 211. The second current mirror 213 is coupled to the first current mirror 212. The current source 214 is coupled between the second current mirror 213 and a low voltage terminal. The current source 214 and the second current mirror 213 output the detection signal Ds at a common node N. In this embodiment, the first current mirror 212 includes, but is not limited to, two N-type metal oxide semiconductor field effect transistors. The second current mirror 213 includes, but is not limited to, two P-type metal oxide semiconductor field effect transistors.

The signal conditioning circuit 22 receives the input signal IN and is coupled to the detection circuit 21 to receive the detection signal Ds. Based on the input signal IN, the detection signal Ds, and a control signal LG, the signal conditioning circuit 22 generates the first input signal in and the second input signal inb. In this embodiment, the signal conditioning circuit 22 includes a logic gate 221 and an RS flip-flop 222.

The logic gate 221 receives the input signal IN and is coupled to the common node N of the detection circuit 21 to receive the detection signal Ds. Based on the input signal IN and the detection signal Ds, the logic gate 221 generates a logic signal Ls. The RS flip-flop 222 has a first receiving terminal S coupled to the logic gate 221 to receive the logic signal Ls, a second receiving terminal R receiving the control signal LG, and two output terminals Q and /Q. Based on the logic signal Ls and the control signal LG, the RS flip-flop 222 generates the first input signal in and the second input signal inb at the output terminals Q and /Q, respectively. In this embodiment, the logic gate 221 is an NOR gate and its end for receiving the input signal IN inverts the input signal IN.

The first voltage adjustment unit 3 is coupled to the output terminal Q of the RS flip-flop 222 to receive the first input signal in and generate an amplified first adjustment signal As1. The second voltage adjustment unit 4 is coupled to the output terminal /Q of the RS flip-flop 222 to receive the second input signal inb and generate an amplified second adjustment signal As2. In this embodiment, the first voltage adjustment unit 3 includes a first buffer gate 31, an input capacitor 32, a first transistor 33, a second transistor 34, a first resistor 35, a second resistor 36, and a clamp circuit 37. The second voltage regulating unit 4 includes a first buffer gate 41, an input capacitor 42, a first transistor 43, a second transistor 44, a first resistor 45, a second resistor 46, and a clamping circuit 47. The first transistors 33, 43 and the second transistors 34, 44 are each N-type metal oxide semiconductor field effect transistors. The first voltage regulating unit 3 and the second voltage regulating unit 4 are each capacitively coupled voltage regulating units. Because the first voltage regulating unit 3 and the second voltage regulating unit 4 have symmetrical structures, for simplicity, the following description uses the first voltage regulating unit 3 as an example to illustrate its internal component connections.

The first buffer gate 31 has a first terminal for receiving the first input signal "in" and a second terminal for outputting a buffer signal. The input capacitor 32 is used for capacitive coupling and has a first terminal coupled to the second terminal of the first buffer gate 31 for receiving the buffer signal, and a second terminal without ground capacitance. The first transistor 33 has a first terminal, a second terminal coupled to the first voltage terminal LX, and a control terminal coupled to the second terminal of the input capacitor 32 for receiving the buffer signal. The second transistor 34 has a first terminal coupled to the first latch unit 5 and outputting the first adjustment signal As1, a second terminal coupled to the first terminal of the first transistor 33, and a control terminal receiving a first switching signal S1 (i.e., a corresponding one of the first switching signal S1 and the second switching signal S2). The first resistor 35 is coupled between a second voltage terminal Boost and the first terminal of the second transistor 34. The second resistor 36 is coupled between the second voltage terminal Boost and the second terminal of the second transistor 34. The clamping circuit 37 is coupled between the control terminal of the first transistor 33 and the first voltage terminal LX and is used to clamp the erroneous buffer signal. The clamp circuit 37 includes, but is not limited to, two N-type metal oxide semiconductor field effect transistors and a resistor. The voltage of the second voltage terminal Boost is, for example, in the range of 25V to 30V. The voltage at the first terminal of the first transistor 43 (denoted by the symbol aa in FIG3 ) serves as the first switching signal S1. The voltage at the first terminal of the first transistor 33 (denoted by the symbol bb in FIG3 ) serves as the second switching signal S2.

It should be noted that, referring further to FIG. 4A to FIG. 4C , in the layout, the input capacitor 32 (42) (50 fF) is a metal-metal type high-voltage parasitic capacitor generated by the metal wire between the metal wire M1 at the first end of the first buffer gate 31 (41) and the metal wire M2 at the control end of the first transistor 33 (43). The present invention utilizes these input capacitors 32, 42 to replace the high-voltage difference transistor of the existing voltage level shifter to form a single-chip compact capacitor-type voltage level shifter. With this architecture, the voltage level shifter 1 does not require high-voltage-dropout transistors (HVDDs), resulting in a smaller circuit area. Furthermore, the voltage level shifter 1 is not subject to the varying transition speeds associated with HVDDs due to process, voltage, and temperature variations. Consequently, the voltage level shifter 1 exhibits a smaller propagation delay. Furthermore, since the voltage level shifter 1 does not require HVDDs, it does not require a HVDD manufacturing process, resulting in lower manufacturing costs. In addition, the present invention utilizes the metal wire M1 at the first end of the first buffer gate 31 (41) to surround the metal wire M2 at the control end of the first transistor 33 (43) (i.e., the control end of the first transistor 33 serving as a receiver node can be shielded by the first buffer gate 31 serving as a transmitter), so that the second end of the input capacitor 32 has no capacitance to ground, thereby preventing the control end of the first transistor 33 (43) from having capacitance to ground, which causes the received signal to be reduced.

The first latch unit 5 is coupled to the first terminals of the second transistor 34 and the second transistor 44 to receive the first adjustment signal As1 and the second adjustment signal As2, respectively, and generates a first latch signal Lat1 according to the first adjustment signal As1 and the second adjustment signal As2.

In this embodiment, the first latch unit 5 includes a third transistor 51, a fourth transistor 52, and a latch circuit 53. The third transistor 51 has a first terminal coupled to the second voltage terminal Boost, a second terminal, and a control terminal coupled to the first terminal of the second transistor 34 for receiving the first adjustment signal As1. The fourth transistor 52 has a first terminal coupled to the second voltage terminal Boost, a second terminal, and a control terminal coupled to the second transistor 44 for receiving the second adjustment signal As2. The latch circuit 53 is coupled to the second terminals of the third transistor 51 and the fourth transistor 52 and is configured to latch the potential of one of the second terminals of the third transistor 51 and the fourth transistor 52 to generate the first latch signal Lat1. In this embodiment, the latch circuit 53 includes two inverters and a resistor. The third transistor 51 and the fourth transistor 52 are each a P-type metal oxide semiconductor field effect transistor.

The output unit 6 is coupled to the latch circuit 53 to receive the first latch signal Lat1 and generate an output signal Vout based on the first latch signal Lat1, an input voltage Vin, and the control signal LG. The high logic level voltage of the output signal Vout is greater than the high logic level voltage of each of the first input signal in and the second input signal inb.

In this embodiment, the output unit 6 includes a second buffer gate 61, a fifth transistor 62, and a sixth transistor 63. The second buffer gate 61 has a first terminal coupled to the latch circuit 53 to receive the first latch signal Lat1, a second terminal coupled to the first voltage terminal LX, a third terminal coupled to the second voltage terminal Boost, and an output terminal. The second buffer gate 61 generates and outputs a buffer control signal Bc at its output terminal based on the first latch signal Lat1 and the voltage levels of the first voltage terminal LX and the second voltage terminal Boost. The fifth transistor 62 has a first terminal for receiving the input voltage Vin, a second terminal coupled to the first voltage terminal LX and outputting the output signal Vout, and a control terminal coupled to the output terminal of the second buffer gate 61 for receiving the buffer control signal Bc. The sixth transistor 63 has a first terminal coupled to the second terminal of the fifth transistor 62, a second terminal connected to ground, and a control terminal for receiving the control signal LG. The fifth transistor 62 and the sixth transistor 63 are each an N-type metal oxide semiconductor field effect transistor.

It should be noted that in this embodiment, the voltage of the second voltage terminal Boost is greater than the voltage of the first voltage terminal LX, but this is not limited to this. In other embodiments, the voltage of the second voltage terminal Boost may be less than the voltage of the first voltage terminal LX, and each N-type MOSFET in the first voltage adjustment unit 3, the second voltage adjustment unit 4, and the first latch unit 5 may be replaced by a P-type MOSFET, and each P-type MOSFET may be replaced by an N-type MOSFET.

With further reference to Figures 3 and 5, the operation of the voltage level shifter 1 of this embodiment will be described below.

At time t1, in the first voltage regulating unit 3, the first transistor 33 and the second transistor 34 are conductive, and the voltage bb at the first terminal of the first transistor 33 is temporarily pulled down due to the conductive first transistor 33. This causes the first adjustment signal As1 output by the first voltage regulating unit 3 to temporarily have a low logic level. This causes the third transistor 51 to be conductive, and the first latch signal Lat1 transitions from a low logic level to a high logic level until time t2. Simultaneously, in the second voltage regulating unit 4, the first transistor 43, the second transistor 44, and the fourth transistor 52 are non-conductive, and the second voltage regulating unit 4 does not generate the second adjustment signal As2. Because the first latch signal Lat1 transitions from a low logic level to a high logic level, the buffer control signal Bc reaches a high logic level. Therefore, the fifth transistor 62 turns on, and the sixth transistor 63 turns off under the control of the control signal LG. The output signal Vout output by the output unit 6 reaches a high voltage level.

At time t2, in the first voltage regulating unit 3, the first transistor 33, the second transistor 34, and the third transistor 51 are not conducting, and the first voltage regulating unit 3 does not generate the first regulating signal As1. Simultaneously, in the second voltage regulating unit 4, the first transistor 43 and the second transistor 44 are conducting, and the voltage aa at the first terminal of the first transistor 43 is temporarily pulled down due to the conduction of the first transistor 43. This causes the second regulating signal As2 output by the second voltage regulating unit 4 to have a low logic level, thereby turning on the fourth transistor 52 and causing the first latch signal Lat1 to transition from a high logic level to a low logic level. Because the first latch signal Lat1 transitions from a high logic level to a low logic level, the buffer control signal Bc reaches a low logic level. Therefore, the fifth transistor 62 is turned off, and the sixth transistor 63 is turned on by the control signal LG. The output signal Vout output by the output unit 6 reaches a low voltage level.

It should be noted that, under normal operation, when the first voltage adjustment unit 3 operates to generate the first adjustment signal As1, the second voltage adjustment unit 4 does not generate the second adjustment signal As2. When the second voltage adjustment unit 4 operates to generate the second adjustment signal As2, the first voltage adjustment unit 3 does not generate the first adjustment signal As1. When the first voltage regulating unit 3 and the second voltage regulating unit 4 operate simultaneously (i.e., at time t3, when the potential of the first voltage terminal LX reaches a low logic level), to prevent the voltage level shifter 1 from being affected by the common-mode voltage of the first input signal in and the second input signal inb, the voltages of the first switching signal S1 and the second switching signal S2 are temporarily pulled down at time t3 to render the second transistors 34 and 44 non-conductive. This prevents the voltage level shifter 1 from being affected by the common-mode voltage of the first input signal in and the second input signal inb.

Referring to Figures 6 and 7 , another embodiment of the voltage level shifter 1′ of the present invention is described. This voltage level shifter 1′ is similar to the voltage level shifter 1 of Figure 1 . The difference between the two is that in this embodiment, a first voltage adjustment unit 11, a second voltage adjustment unit 12, a first latch unit 13, and an output unit 14 replace the first voltage adjustment unit 3, the second voltage adjustment unit 4, the first latch unit 5, and the output unit 6 of Figure 1 , respectively. The signal adjustment unit 2 of Figure 1 is omitted.

The first voltage regulation unit 11 includes a buffer gate 111, an input capacitor 112, and a clamping circuit 113. The buffer gate 111 has a first terminal for receiving a first input signal in1, a second terminal for outputting a buffer signal, a third terminal for receiving a supply voltage Vdd, and a fourth terminal connected to ground. The input capacitor 112 has a first terminal coupled to the second terminal of the buffer gate 111 for receiving the buffer signal, and a second terminal without ground capacitance that outputs a first adjustment signal As1′. The clamping circuit 113 is coupled between the second voltage terminal Boost and the second terminal of the input capacitor 112 to clamp the erroneous first adjustment signal As1′. The clamping circuit 113 includes a first transistor 114, a second transistor 115, and a resistor 116. The first transistor 114 and the second transistor 115 are connected in series between the second voltage terminal Boost and the second end of the input capacitor 112. The resistor 116 is coupled between the second voltage terminal Boost and the second end of the input capacitor 112. The first transistor 114 and the second transistor 115 are each P-type metal oxide semiconductor field effect transistors.

The second voltage regulation unit 12 includes a buffer gate 121, an input capacitor 122, and a clamp circuit 123. The buffer gate 121 has a first terminal for receiving a second input signal in2, a second terminal for outputting a buffer signal, a third terminal for receiving the supply voltage Vdd, and a fourth terminal connected to ground. The input capacitor 122 has a first terminal coupled to the second terminal of the buffer gate 121 for receiving the buffer signal, and a second terminal with no capacitance to ground and outputting a second adjustment signal As2′. The second input signal in2 is in phase with the first input signal in1. The clamping circuit 123 is coupled between the first voltage terminal LX and the second terminal of the input capacitor 122 to clamp the erroneous second adjustment signal As2'. The clamping circuit 123 includes a first transistor 124, a second transistor 125, and a resistor 126. The first transistor 124 and the second transistor 125 are connected in series between the first voltage terminal LX and the second terminal of the input capacitor 122. The resistor 126 is coupled between the first voltage terminal LX and the second terminal of the input capacitor 122. The first transistor 124 and the second transistor 125 are each an N-type metal oxide semiconductor field effect transistor. It should be noted that each of the buffer gates 111 and 121 operates within an operating voltage range that is between the supply voltage Vdd and the ground voltage. The input capacitors 112 and 122 each have the same layout as the input capacitor 32 of FIG3 and have the same function (i.e., the voltage level shifter 1' does not need to be provided with a high voltage difference transistor). They are also metal-metal type high voltage parasitic capacitors, and the metal line at the first end of the buffer gate 111 (121) surrounds the metal line at the control end of the fourth transistor 131 (fifth transistor 132), so that the second end of each of the input capacitors 112 and 122 has no capacitance to ground. The potentials of the first adjustment signal As1’ and the second adjustment signal As2’ respectively track the potential of the first voltage terminal LX.

The first latch unit 13 includes a fourth transistor 131, a fifth transistor 132, an output capacitor 133, and a latch circuit 134. The fourth transistor 131 has a first terminal coupled to the second voltage terminal Boost, a second terminal, and a control terminal coupled to the first voltage adjustment unit 11 to receive the first adjustment signal As1′. The fifth transistor 132 has a first terminal coupled to the second terminal of the fourth transistor 131, a second terminal coupled to the first voltage terminal LX, and a control terminal coupled to the second voltage adjustment unit 12 to receive the second adjustment signal As2′. The output capacitor 133 is coupled between the first voltage terminal LX and the second voltage terminal Boost. The latch circuit 134 is coupled to the first terminal of the fifth transistor 132 to latch the potential of the first terminal of the fifth transistor 132 to generate the first latch signal Lat1. The latch circuit 134 includes two inverters, with the output of one inverter coupled to the input of the other inverter. The fourth transistor 131 is a P-type metal oxide semiconductor field-effect transistor. The fifth transistor 132 is an N-type metal oxide semiconductor field-effect transistor. It should be noted that in this embodiment, since the second input signal in2 and the first input signal in1 are synchronous signals, and the potentials of the first adjustment signal As1’ and the second adjustment signal As2’ respectively track the potential of the first voltage terminal LX, when the potential of the first voltage terminal LX rises, the fourth transistor 131 is turned on and the fifth transistor 132 is turned off; when the potential of the first voltage terminal LX drops, the fourth transistor 131 is turned off and the fifth transistor 132 is turned on. In this way, the voltage level shifter 1' will not experience the situation where the fourth transistor 131 and the fifth transistor 132 are turned on at the same time (which would cause the voltage level shifter 1' to be affected by the common-mode voltage), thereby preventing the voltage level shifter 1' from being affected by the common-mode voltage of the first input signal in1 and the second input signal in2.

The output unit 14 includes an inverter 141, a sixth transistor 142, and a seventh transistor 143. The inverter 141 has a first terminal coupled to the latch circuit 134 to receive the first latch signal Lat1, and a second terminal. The inverter 141 outputs an inverted signal Is at its second terminal based on the first latch signal Lat1. The sixth transistor 142 has a first terminal that receives the input voltage Vin, a second terminal coupled to the first voltage terminal LX and outputs the output signal Vout, and a control terminal coupled to the second terminal of the inverter 141 to receive the inverted signal Is. The seventh transistor 143 has a first terminal coupled to the second terminal of the sixth transistor 142, a second terminal connected to ground, and a control terminal that receives the control signal LG. The sixth transistor 142 and the seventh transistor 143 are each an N-type metal oxide semiconductor field effect transistor.

During operation, when the fourth transistor 131 is conducting and the fifth transistor 132 is not conducting, the first latch signal Lat1 generated by the latch circuit 134 has a low logic level "0", causing the inverting signal Is to have a high logic level. This causes the sixth transistor 142 to conduct, and the seventh transistor 143 to be non-conducting due to the control signal LG. As a result, the output signal Vout output by the output unit 14 has a high voltage level.

When the fourth transistor 131 is off and the fifth transistor 132 is on, the first latch signal Lat1 generated by the latch circuit 134 has a high logic level "1", causing the inverter signal Is to have a low logic level. This causes the sixth transistor 142 to be off and the seventh transistor 143 to be turned on by the control signal LG. Consequently, the output signal Vout output by the output unit 14 has a low voltage level.

Referring to FIG. 8 , another embodiment of the first voltage regulating unit 11 and the second voltage regulating unit 12 is illustrated. The first voltage regulating unit 11 further includes a third transistor 117 having a first end coupled to the second end of the input capacitor 112, a second end coupled to the resistor 116, and a control end. The second voltage regulating unit 12 further includes a third transistor 127 having a first end coupled to the second end of the input capacitor 122, a second end coupled to the resistor 126, and a control end. The control end of the third transistor 117 is coupled to the second end of the third transistor 127, and the control end of the third transistor 127 is coupled to the second end of the third transistor 117. The third transistor 117 is a P-type metal oxide semiconductor field effect transistor. The third transistor 127 is an N-type metal oxide semiconductor field effect transistor. In this embodiment, when the first adjustment signal As1' or the second adjustment signal As2' has a spike (not the desired sampled signal), one of the third transistors 117 and 127 is turned on and the other is turned off, creating a blanking time to mask the corresponding spike and prevent noise injection.

Referring to FIG9 , another embodiment of the voltage level shifter 1′ is illustrated. The voltage level shifter 1′ further includes a third voltage adjustment unit 15, a fourth voltage adjustment unit 16, and a second latch unit 17.

The third voltage adjustment unit 15 is coupled to the second terminal of the inverter 141 to receive the inverted signal Is and generate an amplified third adjustment signal As3 accordingly. The fourth voltage adjustment unit 16 is coupled to the second terminal of the inverter 141 to receive the inverted signal Is and generate an amplified fourth adjustment signal As4 accordingly. The second latch unit 17 is coupled to the third voltage adjustment unit 15 and the fourth voltage adjustment unit 16 to receive the third adjustment signal As3 and the fourth adjustment signal As4, respectively, and generate a second latch signal Lat2 based on the third adjustment signal As3 and the fourth adjustment signal As4. The internal structure and configuration of the third voltage adjustment unit 15, the fourth voltage adjustment unit 16, and the second latch unit 17, as well as their operating principles, are similar to those of the first voltage adjustment unit 11, the second voltage adjustment unit 12, and the first latch unit 13, respectively, and are therefore not further described here. It should be noted that the output signal of the inverter 171 and the second latch signal Lat2 are transmitted from the upper bridge detection signal back to the lower bridge for use, for example, as dead time non-overlap control to ensure that the upper and lower bridges are not simultaneously activated.

In this embodiment, the input capacitors 32, 42 (112, 122) are used to replace the high-voltage-difference transistors of the existing voltage level shifter to form a single-chip compact capacitor-type voltage level shifter. Under this architecture, since the voltage level shifter 1 (1') does not need to be provided with a high-voltage-difference transistor and is composed of a low-voltage-difference transistor, it has a smaller circuit area and will not have different transition speeds due to changes in the high-voltage-difference transistor caused by different processes, voltages, and temperatures. In this way, the voltage level shifter 1 (1') has a smaller propagation delay. In other words, the voltage level shifter 1 (1') can provide higher speed performance. Furthermore, since the voltage level shifter 1 (1') does not require a high-voltage-difference transistor, it does not need to be manufactured using a high-voltage-difference process, resulting in lower manufacturing costs. Furthermore, the problem of using high-voltage-difference electronic components that are easily affected by the conduction of parasitic components, as mentioned in the prior art, does not exist.

However, the above descriptions are merely examples of the present invention and should not be construed to limit the scope of the present invention. Any simple equivalent variations and modifications made within the scope of the patent application and the contents of the patent specification are still covered by the present patent.

1’: Voltage level shifter

11: First voltage adjustment unit

12: Second voltage adjustment unit

13: First locking unit

14: Output unit

As1’: First adjustment signal

As2’: Second adjustment signal

in1: first input signal

in2: Second input signal

Lat1: First lock signal

LG: Control signal

Vin: Input voltage

Vout: output signal

Claims (16)

A voltage level shifter comprises: a first voltage adjustment unit that receives a first input signal and generates an amplified first adjustment signal accordingly; a second voltage adjustment unit that receives a second input signal and generates an amplified second adjustment signal accordingly; a first latching unit that couples the first voltage adjustment unit and the second voltage adjustment unit to receive the first adjustment signal and the second adjustment signal, respectively, and generates a first latching signal based on the first adjustment signal and the second adjustment signal; and An output unit is coupled to the first latch unit to receive the first latch signal and generates an output signal based on the first latch signal, an input voltage, and a control signal. The high logic level of the output signal is greater than the high logic level of each of the first input signal and the second input signal. The first voltage regulating unit and the second voltage regulating unit are each a capacitively coupled voltage regulating unit and each include an input capacitor, one end of which has no capacitance to ground. The voltage level shifter of claim 1, wherein the second input signal and the first input signal are inversely proportional to each other, the input capacitor is a high-voltage parasitic capacitor having a first terminal and a second terminal without ground capacitance, and the first voltage adjustment unit and the second voltage adjustment unit are symmetrical and each further comprises: a first buffer gate having a first terminal for receiving a corresponding one of the first input signal and the second input signal, and a second terminal coupled to the first terminal of the corresponding input capacitor and outputting a buffer signal; a first transistor having a first terminal, a second terminal coupled to a first voltage terminal, and a control terminal coupled to the second terminal of the input capacitor for receiving the buffer signal; A second transistor having a first terminal coupled to the first latch unit and outputting a corresponding one of the first adjustment signal and the second adjustment signal, a second terminal coupled to the first terminal of the first transistor, and a control terminal receiving a corresponding one of a first switching signal and a second switching signal; A first resistor coupled between a second voltage terminal and the first terminal of the second transistor; A second resistor coupled between the second voltage terminal and the second terminal of the second transistor; and A clamping circuit coupled between the control terminal and the first voltage terminal of the first transistor for clamping the erroneous buffer signal. The voltage level shifter as described in claim 2, wherein the voltage of the second voltage terminal is greater than or less than the voltage of the first voltage terminal. The voltage level shifter of claim 2 further comprises: A signal adjustment unit receiving an input signal and coupled to the first voltage terminal for detecting whether a rising edge of the input signal is within a slope range of a rising voltage at the first voltage terminal. If the detection result is yes, the rising edge position of the input signal is adjusted to generate the first input signal and the second input signal, which are output to the first voltage adjustment unit and the second voltage adjustment unit, respectively. The voltage level shifter of claim 4, wherein the signal conditioning unit comprises: a detection circuit coupled to the first voltage terminal and detecting the voltage of the first voltage terminal to generate a detection signal; and a signal conditioning circuit receiving the input signal and coupled to the detection circuit to receive the detection signal, and generating the first input signal and the second input signal based on the input signal, the detection signal, and the control signal. The voltage level shifter of claim 5, wherein the detection circuit comprises: a capacitor having a first terminal coupled to the first voltage terminal and a second terminal; a first current mirror coupled to the second terminal of the capacitor; a second current mirror coupled to the first current mirror; and a current source coupled between the second current mirror and a low voltage terminal, the detection signal being outputted at a common node between the current source and the second current mirror. The voltage level shifter of claim 5, wherein the signal conditioning circuit comprises: a logic gate receiving the input signal, coupled to the detection circuit to receive the detection signal, and generating a logic signal based on the input signal and the detection signal; and an RS flip-flop receiving the control signal, coupled to the logic gate to receive the logic signal, and generating the first input signal and the second input signal based on the logic signal and the control signal. The voltage level shifter of claim 1, wherein the first latch unit comprises: a third transistor having a first terminal coupled to a second voltage terminal, a second terminal, and a control terminal coupled to the first voltage adjustment unit to receive the first adjustment signal; a fourth transistor having a first terminal coupled to the second voltage terminal, a second terminal, and a control terminal coupled to the second voltage adjustment unit to receive the second adjustment signal; and a latch circuit coupled to the second terminals of the third transistor and the fourth transistor for latching the potential of one of the second terminals of the third transistor and the fourth transistor to generate the first latch signal. The voltage level shifter of claim 1, wherein the output unit comprises: a second buffer gate having a first terminal coupled to the first latch unit to receive the first latch signal, a second terminal coupled to a first voltage terminal, a third terminal coupled to a second voltage terminal, and an output terminal for outputting a buffer control signal; a fifth transistor having a first terminal for receiving the input voltage, a second terminal coupled to the first voltage terminal and outputting the output signal, and a control terminal coupled to the output terminal of the second buffer gate to receive the buffer control signal; and a sixth transistor having a first terminal coupled to the second terminal of the fifth transistor, a second terminal connected to ground, and a control terminal for receiving the control signal. The voltage level shifter of claim 1, wherein the second input signal and the first input signal are synchronous signals, the input capacitor has a first terminal and a second terminal without a ground capacitance, the second terminal of the input capacitor outputs a corresponding one of the first adjustment signal and the second adjustment signal, and the first voltage adjustment unit and the second voltage adjustment unit each further include: a buffer gate having a first terminal for receiving a corresponding one of the first input signal and the second input signal, and a second terminal coupled to the first terminal of the corresponding input capacitor and outputting a buffer signal; and A clamping circuit is coupled between a corresponding one of a first voltage terminal and a second voltage terminal and the second end of the corresponding input capacitor, for clamping a corresponding one of the erroneous first adjustment signal and the second adjustment signal. The voltage level shifter of claim 10, wherein the potentials of the first adjustment signal and the second adjustment signal respectively track the potential of the first voltage terminal. The voltage level shifter of claim 10, wherein the clamping circuit comprises: a first transistor and a second transistor connected in series between a corresponding one of the first voltage terminal and the second voltage terminal and the corresponding second end of the input capacitor; and a resistor coupled between a corresponding one of the first voltage terminal and the second voltage terminal and the corresponding second end of the input capacitor. The voltage level shifter of claim 12, wherein the first voltage regulating unit and the second voltage regulating unit each further include: a third transistor having a first end coupled to the second end of the corresponding input capacitor, a second end coupled to the corresponding resistor, and a control end; wherein, the control end of the third transistor of the first voltage regulating unit is coupled to the second end of the third transistor of the second voltage regulating unit, and the control end of the third transistor of the second voltage regulating unit is coupled to the second end of the third transistor of the first voltage regulating unit. The voltage level shifter of claim 10, wherein the first latch unit comprises: a fourth transistor having a first end coupled to the second voltage terminal, a second end, and a control end coupled to the first voltage adjustment unit to receive the first adjustment signal, the fourth transistor being a P-type metal oxide semiconductor field effect transistor; a fifth transistor having a first end coupled to the second end of the fourth transistor, a second end coupled to the first voltage terminal, and a control end coupled to the second voltage adjustment unit to receive the second adjustment signal, the fifth transistor being an N-type metal oxide semiconductor field effect transistor; an output capacitor coupled between the first voltage terminal and the second voltage terminal; and A latch circuit is coupled to the first terminal of the fifth transistor and is configured to latch the potential of the first terminal of the fifth transistor to generate the first latch signal. The voltage level shifter of claim 14, wherein the output unit comprises: an inverter having a first terminal coupled to the first latch unit to receive the first latch signal, and a second terminal outputting an inverted signal; a sixth transistor having a first terminal receiving the input voltage, a second terminal coupled to the first voltage terminal and outputting the output signal, and a control terminal coupled to the second terminal of the inverter to receive the inverted signal; and a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, a second terminal connected to ground, and a control terminal receiving the control signal. The voltage level shifter of claim 15 further comprises: a third voltage adjustment unit coupled to the second terminal of the inverter to receive the inverted signal and generate an amplified third adjustment signal accordingly; a fourth voltage adjustment unit coupled to the second terminal of the inverter to receive the inverted signal and generate an amplified fourth adjustment signal accordingly; and a second latching unit coupled to the third voltage adjustment unit and the fourth voltage adjustment unit to receive the third adjustment signal and the fourth adjustment signal, respectively, and generate a second latching signal based on the third adjustment signal and the fourth adjustment signal.