1363968 101年02月15日按正替换頁 六、 [0001] [0002] [0003] 發明說明： 【發明所屬之技術領域】 本發明係關於一種高速差分訊號傳輸系統。 [先前技術] 習知之個人電腦主機板上’除了有中央處理器，控制晶 片組外’還有複數用於安裝各種傳輸規格裝置之連接器 。隨著電子產業之發展，出現了多種傳輸規格之硬碟， 如SAS (Serial Attached SCSI)傳輸規格硬碟及 SATA (Serial ΑΤΑ)傳輸規格硬碟，這兩種傳輸規格硬 碟可共用同一連接器。但不同之主機板產品僅能支援其 中一種傳輸規格硬碟，如有的廠商要求主機板支援SAS傳 輸規格硬碟，有的廠商則要求主機板支援SATA傳輸規格 硬碟’因此’縱使該兩傳輸規格硬碟可共用同一連接器 ，但設計主機板時通常也只能選擇其中一種傳輸規格硬 碟來進行對應之高速差分訊號傳輸系統設計，即支援SAS 傳輸規格硬碟之主機板，或支援SATA傳輸規格硬碟之主 機板，兩者無法共用。故按照不同廠商要求，需要對支 援該兩傳輸規格硬碟之主機板佈線進行分別設計，進而 增加了主機板設计之成本。因此，如何提供一種主機板 佈線架構，利用相同之主機板佈線，可彈性地支援能共 用同一連接器之兩種傳輸規格硬碟，並使線路工作時都 能維持訊號完整性，即為業界急需解決之課題。 【發明内容】 鑒於以上内容，有必要提供一種高速差分訊號傳輸系統 ，可彈性地連接能共用連接器之兩種傳輸規格裝置。 0961391# 料號 Α0101 第4頁/共11頁 1013054972-0 1363968 [0004] 1101年.02月15曰 一種高速差分訊號傳輸系統，其包括一訊號控制晶片、1363968 February 15th, 2011, according to the replacement page. [0001] [0002] [0003] [Technical Field] The present invention relates to a high-speed differential signal transmission system. [Prior Art] On the personal computer motherboard of the prior art, in addition to the central processing unit, the control chip group has a plurality of connectors for mounting various transmission specification devices. With the development of the electronics industry, there are a variety of hard drives for transmission specifications, such as SAS (Serial Attached SCSI) transmission specification hard disk and SATA (Serial ΑΤΑ) transmission specification hard disk. These two transmission specifications can share the same connector. . However, different motherboard products can only support one of the transmission specifications hard disks. If some manufacturers require the motherboard to support SAS transmission specification hard disk, some manufacturers require the motherboard to support SATA transmission specification hard disk 'so' even if the two transmissions The standard hard disk can share the same connector, but when designing the motherboard, usually only one of the transmission standard hard disks can be selected for the corresponding high-speed differential signal transmission system design, that is, the motherboard supporting SAS transmission specification hard disk, or supporting SATA The motherboard of the standard hard disk is not shared. Therefore, according to the requirements of different manufacturers, it is necessary to separately design the motherboard wiring supporting the two transmission specifications hard disks, thereby increasing the cost of the motherboard design. Therefore, how to provide a motherboard wiring structure, using the same motherboard wiring, can flexibly support two transmission specifications hard disks that can share the same connector, and maintain signal integrity during line operation, which is urgently needed by the industry. Solve the problem. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a high-speed differential signal transmission system that can elastically connect two transmission specification devices that can share a connector. 0961391# Item No. Α0101 Page 4 of 11 1013054972-0 1363968 [0004] 1101.02月15曰 A high-speed differential signal transmission system comprising a signal control chip,
複數第一傳輸線、複數第二傳輸線、複數第三傳輸線、 一訊號轉換晶片及一可連接兩種不同傳輸規格裝置之共 用連接器，該訊號控制晶片依次透過該等第一及第二傳 輸線與該共用連接器連接，該訊號控制晶片還透過該等 第一傳輸線與該訊號轉換晶片連接，該訊號轉換晶片透 過該等第三傳輸線與該共用連接器連接，當該共用連接 器連接第一傳輸規格裝置時，使每一第二傳輸線上串聯 一第一電阻’而每一第三傳輸線斷開使該訊號轉換晶片 空接’當該共用連接器連接第二傳輸規格裝置時，使每 一第二傳輸線串聯一第二電阻，而每一第二傳輸線斷開 [0005]相較習知技術，該高速差分訊號傳輸系統在一主機板上 佈置了可供安裝兩種傳輸規格裝置之共用連接器，生產 時只需控制該訊號控制晶片及該第一、第二電阻之連接 狀態，並在該共用連接器上選擇性地安裝不同之傳輸規 格裝置，即可滿足不同客戶之需求，從而節省了主機板 之設計費用。 【實施方式】 ]參考圖1，本發明高遠差分訊號傳輸系統包括一訊號控制 曰a片10複數第一傳輸線2〇、複數第二傳輸線、複數 第三傳輸線40 ’ 一訊號轉換晶片50及一共用連接器6〇。 本實施方式以支援SAS傳輪規格硬碟及SATA傳輸規格硬碟 之高速差分訊號傳輸系統來舉例說明，該共用連接器6〇 可安裝SAS傳輸規格硬碟或SATA傳輸規格硬碟，即為 第5頁/共11頁 09613916#單編號 A0101 1013054972-0 1363968 101年02月15日核正替換頁 SAS/SATA共用連接器。該訊號控制晶月1〇為高速差分訊 號控制晶片（如北橋晶片），該訊號轉換晶片5〇aSAS轉 換SATA訊號轉換晶片，為方便說明，圖中每種傳輸線僅 以兩根線表示。 [0007] [0008] 該訊號控制晶片10透過第—傳輸線2〇及第二傳輸線3〇與 該共用連接器6°連接，且每-第-傳輸線2。上還串聯」 第-電容Π ’每-第二傳輪細上還串聯—第—電⑽ 。該訊號㈣晶片10還透過該等第—傳輸線2Q與該訊號 轉換晶片50連接，該訊號轉換晶㈣透過料第三傳輸 線4〇與該共用連接器⑼連接，且每-第三傳輸線40上還 串聯由一第二電阻以及_第二電容㈡組成之串聯電路。 當在該共用連接器6G上安裝-第-傳輸規格裝置（如SAS 傳輸規格硬碟）時，該訊號轉換晶片5()空接，移除該第 :細及第二電容C2，使該第三傳輪線4〇斷開。該訊 说控制晶片U)直接與該第—傳輸規格裝置通訊4丘用 連接器60與該第二電瞻之間之傳輸線成為—殘段此 殘效齡產生職反射，為了避免訊號在該第 二傳輸線4〇上產生之反射影響訊號之完整性，需控制該 第二電鐵與該共用連接器6G間之傳輸線之長卜❹ 滿足以下公式： 又 、 [0009] Lstub<(Tj*v)/2 ; [0010] v = c//* £ e [0011] 其中Lstub代表該共用連接器6〇與 、—電阻尺2間之傳輸 <長度，Tj為向速差为訊號可容 卞&幷動，v為訊號在傳 09613916#單編號AOm 第6頁/共π頁 1013054972-0 1363968 .101年02月15日俊正替換頁 輸線中傳輸之速度，c為光速，£e為傳輸線之等效介電 常數。 _]當在該共用連接器6〇上安裝一第二傳輸規格裝置（如 SATA傳輸規格硬碟）時，移除該第_電阻R1，使該第二 傳輸線30斷開’該訊號控制晶片η透過該訊號轉換晶片 50與該第二傳輸規格裝置通訊。同理該共用連接器6〇 與該第一電阻R1之間之傳輸線成為—殘段，為了避免訊 · 號在該第二傳輸線30上產生之反射影響訊號之完整性， # 需控制該第一電阻R1與該共用連接器60間之傳輸線之長 度，使其滿足以下公式： [0013] Lstub<(Tj*v)/2 ; [0014] v = c/y~ ε e [0015]其中Lstub代表該共用連接器6〇與第一電阻^間之傳輸 線長度’ Tj為高速差分訊號可容許之抖動，v為訊號在傳 輸線中傳輸之速度，c為光速，ee為傳輸線之等效介電 • 常數》 [0016]為了減小訊號傳輸損耗’該第一電阻R1及第二電阻R2之 電阻值優選為零歐姆。此外，該第一電容C1及第二電容 C2用於濾除差分訊號之共模直流部分，以便得到更好之 傳輸訊號品質，如果差分訊號之共模直流部分很小或沒 有，則可移除該第一電容C1及第二電容C2，以進一步降 低成本’節約佈線空間。該共用連接器60也可以是支援 其他裝置之共用連接器，不拘泥於僅僅支援硬碟。 [0017] 09613916#單編號初如 藉此，只需提供該主機板佈線架構，利用相同之主機板 第7頁/共11頁 1013054972-0 1363968 _^ 101年02月15日按正替换頁 佈線及共用連接器，即可彈性地支援不同之傳輸規格裝 置，並使線路工作時都能維持訊號完整性，節省了主機 板設計之成本。 [0018] 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施方式，舉 凡熟悉本案技藝之人士，在爰依本發明精神所作之等效 修飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0019] 圖1係本發明高速差分訊號傳輸系統較佳實施方式之示意 · 圖。 【主要元件符號說明】 [0020] 訊號控制晶片：10 [0021] 第一傳輸線：20 [0022] 第二傳輸線：30 [0023] 第三傳輸線：40 [0024] 訊號轉換晶片：50 [0025] 共用連接器：60 [0026] 第一電阻：R1 ' [0027] 第二電阻：R2 [0028] 第一電容：C1。 [0029] 第二電容：C2 09_1^單職删1 第8頁/共11頁 1013054972-0a plurality of first transmission lines, a plurality of second transmission lines, a plurality of third transmission lines, a signal conversion chip, and a common connector connectable to two different transmission specification devices, wherein the signal control chip sequentially passes through the first and second transmission lines a common connector connection, the signal control chip is further connected to the signal conversion chip through the first transmission lines, and the signal conversion chip is connected to the common connector through the third transmission lines, when the common connector is connected to the first transmission specification In the device, each first transmission line is connected in series with a first resistor 'and each third transmission line is disconnected to make the signal conversion wafer empty" when the common connector is connected to the second transmission specification device, so that each second The transmission line is connected in series with a second resistor, and each of the second transmission lines is disconnected [0005]. Compared with the prior art, the high-speed differential signal transmission system is provided with a common connector for mounting two transmission specification devices on a motherboard. During production, it is only necessary to control the connection state of the signal control chip and the first and second resistors, and selectively select the common connector. The installation of different transmission specification devices can meet the needs of different customers, thus saving the design cost of the motherboard. [Embodiment] Referring to FIG. 1, the high-distance differential signal transmission system of the present invention includes a signal control unit 10, a plurality of first transmission lines 2, a plurality of second transmission lines, a plurality of third transmission lines 40', a signal conversion chip 50, and a common Connector 6〇. This embodiment is exemplified by a high-speed differential signal transmission system supporting a SAS transmission specification hard disk and a SATA transmission specification hard disk. The shared connector 6 can be installed with a SAS transmission specification hard disk or a SATA transmission specification hard disk. 5 pages / total 11 pages 09936916# single number A0101 1013054972-0 1363968 On February 15, 101, the nuclear replacement page SAS / SATA shared connector. The signal controls the crystal moon 1〇 as a high-speed differential signal control chip (such as a north bridge chip). The signal conversion chip 5〇aSAS converts the SATA signal conversion chip. For convenience of explanation, each transmission line in the figure is represented by only two lines. [0008] The signal control chip 10 is connected to the common connector 6° through the first transmission line 2〇 and the second transmission line 3〇, and each to the first transmission line 2. The upper part is also connected in series. The -capacitor Π ' is also connected in series to the second pass-----(10). The signal (4) chip 10 is further connected to the signal conversion chip 50 through the first transmission line 2Q, and the signal conversion crystal (4) is connected to the common connector (9) through the third transmission line 4, and is further connected to the third transmission line 40. A series circuit consisting of a second resistor and a second capacitor (2) in series. When a -first transmission specification device (such as a SAS transmission specification hard disk) is mounted on the common connector 6G, the signal conversion chip 5 () is vacant, and the first and second capacitances C2 are removed, so that the first The three-pass line is disconnected. The communication chip U) directly communicates with the first transmission specification device, and the transmission line between the connector 4 and the second telescope becomes a residual segment, and the residual effect is generated by the resident reflection, in order to avoid the signal in the second The reflection generated on the transmission line 4〇 affects the integrity of the signal, and the length of the transmission line between the second electric iron and the common connector 6G is controlled to satisfy the following formula: [0009] Lstub<(Tj*v)/ 2; [0010] v = c / / * £ e [0011] where Lstub represents the transmission between the common connector 6 〇, - the resistance rule 2 < length, Tj is the speed difference signal can be accommodated & Inciting, v is the signal in the transmission 09613916# single number AOm page 6 / total π page 1013054972-0 1363968 . February 15th, 2011, the replacement speed of the page transmission line, c is the speed of light, £e is the transmission line Equivalent dielectric constant. _] When a second transmission specification device (such as a SATA transmission specification hard disk) is mounted on the common connector 6A, the _th resistor R1 is removed, and the second transmission line 30 is disconnected 'the signal control chip η The signal conversion chip 50 is in communication with the second transmission specification device. Similarly, the transmission line between the shared connector 6〇 and the first resistor R1 becomes a stub, and in order to prevent the reflection of the signal on the second transmission line 30 from affecting the integrity of the signal, #1 needs to be controlled. The length of the transmission line between the resistor R1 and the common connector 60 is such that it satisfies the following formula: [0013] Lstub<(Tj*v)/2; [0014] v = c/y~ ε e [0015] where Lstub represents The length of the transmission line between the common connector 6〇 and the first resistor is Tj, which is the allowable jitter of the high-speed differential signal, v is the speed at which the signal is transmitted in the transmission line, c is the speed of light, and ee is the equivalent dielectric constant of the transmission line. [0016] In order to reduce the signal transmission loss, the resistance values of the first resistor R1 and the second resistor R2 are preferably zero ohms. In addition, the first capacitor C1 and the second capacitor C2 are used to filter the common mode DC portion of the differential signal for better transmission signal quality, and may be removed if the common mode DC portion of the differential signal is small or not. The first capacitor C1 and the second capacitor C2 further reduce the cost of 'saving wiring space. The shared connector 60 may be a shared connector that supports other devices, and is not limited to supporting only a hard disk. [0017] 09613916 # single number as such, only need to provide the motherboard wiring structure, using the same motherboard page 7 / 11 pages 1013054972-0 1363968 _ ^ February 15, 2011 by the replacement page wiring And the shared connector can flexibly support different transmission specification devices, and maintain signal integrity while the line is working, saving the cost of the motherboard design. [0018] In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0019] FIG. 1 is a schematic diagram of a preferred embodiment of a high speed differential signal transmission system of the present invention. [Main component symbol description] [0020] Signal control chip: 10 [0021] First transmission line: 20 [0022] Second transmission line: 30 [0023] Third transmission line: 40 [0024] Signal conversion chip: 50 [0025] Sharing Connector: 60 [0026] First resistor: R1 ' [0027] Second resistor: R2 [0028] First capacitor: C1. [0029] The second capacitor: C2 09_1^ single job deletion 1 page 8 / a total of 11 pages 1013054972-0