200919192 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種高速差分訊號傳輪架構。 【先前技術】 習知之個人電腦主機板上，除了有中央處理器，控制 晶片組外，還有複數用於安裝各種傳輪規格裴置之^接 器。隨著電子產業之發展，出現了多種傳輪規格之硬碟， 如 SAS (Sedal Attached SCSI)傳輸規格硬碟及 (Serial ΑΤΑ)傳輸規格硬碟，這兩種傳輸規格硬碟可共用 同-連接器。料同之主機板產品僅能支援其I種傳 =格：碟，如有的廠商要求主機板支援SAS傳輪規“ 碟，有的薇商則要求主機板支援SATA傳輸規格硬碟，因 此，縱使該兩傳輸規格硬碟可共用同一連接器，但設 機板B守通吊也只能選擇其中一種傳輸規格硬碟來進行對應 =差分訊號傳輸架構設計，即支援SAS傳輸規格硬； =機板，或支援SATA傳輸規格硬碟之主機板，兩者益 主：Γ照不同廢商要求，需要對支援該兩傳輸規： 之成太。 線進行分別設計，進而增加了主機板設計 之主機;’如何提供—種主機板佈線架構，利用相同 輪規格硬碟，並 =^、用同—連接器之兩種傳 業界急需解決之^題作"都能維持訊號完整性，即為 【發明内容】 構，a ’有必要提供—種高速差分訊號傳輸架 連接以用連㈣之兩㈣減袼裝置。 200919192 -種高速差分訊號傳輸架構，其包括—訊號控制晶 複數第-傳輸線、複數第二傳輸線、複數第三傳輸線 厂訊:虎轉換晶片及—可連接兩種不同傳輸規格裝置之共用 連接器，該訊號控制晶片依次透過該等第一及第ς 與該共用連接器連接，該訊號控制晶片還透過該等第一傳 輸=該訊號轉換晶片連接，該訊號轉換晶片透過該等第 -傳輪線與該共料接器連接，t該共用連接 傳輸規格裝置時，使每一第二傳輸線上串聯-第-而母一第三傳輸線斷開使該訊號轉換晶片空接，者該 連接器連接第二傳輸規格裝置時，使每一第三傳二線击、 -第二電阻，而每一第二傳輸線斷開。 i線串如 相較習知技術，該高速差分訊號傳輪架構在— 士=了可供安裝兩種傳輸規格裝置之共用連接器， 日守只需控制該訊號控制晶片及該第一、 帝 產 態’並在該共用連接器上選擇性地安裝不 費用。 ^ ^印名了主機板之設計 【實施方式】 參考目本發明高速差分訊號傳輪架構包括 控制晶片10、複數第一傳輪線2〇、 σ號 複數第三傳輸線40,-訊號轉換晶片5 ~^輸線30、 6〇。本實施方式以支援SAS傳輪 二^器 高速差分訊號傳輸架構來舉例= Ω 〇可安裝SAS傳輸規格硬碟或s概傳輪規格=接 200919192 即為SAS/SATA共用連接器。該訊號控制晶片1〇為 分訊號控制晶片（如北橋晶片），該訊號轉換晶片刈為 轉換SATA訊號轉換晶片，為方便說日月， 僅以兩根録#。 ®得輸線 該訊號控制晶片10透過第一傳輸線2〇及第二 30與該共用連接器6G連接，且每H輸線20上^ φ 聯一第一電容Cl，每一第二傳輸線3〇上還串聯一第」 阻R1。該訊號控制晶片1〇還透過該等第一傳輸線2〇與該 訊號轉換晶片50連接，該訊號轉換晶片50透過該等第: ㈣線40與該共用連接器6〇連接，且每一第三傳輸線ς 上還串聯由-第二電阻R2及一第二電容。2組成之串聯恭 路0 當在該共料接H 6G上安裝—第—傳輸規格褒置 SAS傳輸規格硬碟）時’該訊號轉換晶片5〇空接，移陝 該第二電阻R2及第二電容C2’使該第三傳輪線4〇斷開： 该訊號控制晶片10直接與該第—傳輸規格裝置通訊。該妓 用連接器60與該第二電阻R2之間之傳輸線成為_殘°段^ 此殘段之開路效應會產生訊號反射，^ 了避免訊號在該第 三傳輸線40上產生之反射影響訊號之完整性，需控制該 二電阻R2與該共用連㈣6G間之傳輸線之長度 ^ 足以下公式： 吏/、滿200919192 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a high-speed differential signal transmission architecture. [Prior Art] On the conventional personal computer motherboard, in addition to the central processing unit and the control chip set, there are a plurality of connectors for mounting various types of transmission specifications. With the development of the electronics industry, there are a variety of hard disk formats, such as SAS (Sedal Attached SCSI) transmission specification hard disk and (Serial ΑΤΑ) transmission specification hard disk. These two transmission specifications can share the same-connection. Device. It is expected that the same motherboard product can only support its I type: grid. If some manufacturers require the motherboard to support the SAS transmission wheel gauge, some Weishang requires the motherboard to support the SATA transmission specification hard disk. Therefore, Even if the two transmission specifications hard disks can share the same connector, but the machine board B hang hang can only select one of the transmission specification hard disks for the corresponding = differential signal transmission architecture design, that is, support SAS transmission specifications hard; Board, or motherboard that supports SATA transmission specification hard disk, both of them: According to different waste business requirements, it is necessary to support the two transmission rules: the line is designed separately, and then the host of the motherboard design is added. ; 'How to provide a kind of motherboard wiring structure, using the same wheel specification hard disk, and = ^, with the same - connector two transmission industry urgently need to solve the problem "can maintain signal integrity, that is [ SUMMARY OF THE INVENTION A, it is necessary to provide a high-speed differential signal transmission frame connection to connect four (four) two (four) reduction device. 200919192 - High-speed differential signal transmission architecture, including - signal control crystal complex number - a transmission line, a plurality of second transmission lines, and a plurality of third transmission lines: a tiger conversion chip and a shared connector for connecting two different transmission specification devices, the signal control chip sequentially connecting the first and third terminals to the common connection Connected to the signal control chip, through the first transmission=the signal conversion wafer connection, the signal conversion chip is connected to the common connector through the first-passing transmission line, when the common connection transmission specification device Connecting each of the second transmission lines in series - the first and the third - the third transmission line is disconnected to make the signal conversion chip empty, and when the connector is connected to the second transmission specification device, each third pass and second line is struck, The second resistor, and each of the second transmission lines is disconnected. The i-line string is compared with the prior art, and the high-speed differential signal transmission architecture is in the common connector for installing two transmission specification devices. It is only necessary to control the signal control chip and the first, the state, and selectively install on the shared connector without cost. ^ ^Printed the design of the motherboard [embodiment] The sub-signal transmission structure includes a control chip 10, a plurality of first transfer lines 2〇, a σ number complex third transmission line 40, a signal conversion chip 5~^ transmission lines 30, 6〇. This embodiment supports SAS transmission two ^ High-speed differential signal transmission architecture to example = Ω 〇 can be installed SAS transmission specification hard disk or s-transmission wheel specification = connected to 200919192 is SAS / SATA shared connector. The signal control chip 1 is a sub-signal control chip (such as The north bridge chip), the signal conversion chip is converted into a SATA signal conversion chip, for convenience, only two records are recorded. The signal control chip 10 is transmitted through the first transmission line 2 and the second 30. The common connector 6G is connected, and each of the H transmission lines 20 is connected to a first capacitor C1, and each of the second transmission lines 3 is further connected in series with a first resistor R1. The signal control chip 1 is further connected to the signal conversion chip 50 through the first transmission line 2, and the signal conversion chip 50 is connected to the common connector 6 through the (4) line 40, and each third A second resistor R2 and a second capacitor are also connected in series on the transmission line ς. 2, the series of Christine Road 0 when installing on the common material H 6G - the first transmission specification set SAS transmission specification hard disk) 'The signal conversion chip 5 is vacant, and the second resistance R2 and the second The second capacitor C2' disconnects the third transfer line 4: the signal control chip 10 directly communicates with the first transmission specification device. The transmission line between the connector 60 and the second resistor R2 becomes a residual phase. The open circuit effect of the stub generates signal reflection, and the reflection signal on the third transmission line 40 is prevented from affecting the signal. Integrity, it is necessary to control the length of the transmission line between the two resistors R2 and the common connection (4) 6G ^ is enough for the formula: 吏 /, full
Lstub<(Tj*v)/2 ； v=c//~ se 其中Lstub代表該共用連接器6〇與第二電阻R2間之 200919192 谷許之抖動，V為訊號 se為傳輪線之等效介 傳輸線長度’ Tj為高速差分訊號可 在傳輪線中傳輸之速度，C為光速， 電常數。 共用連接^ 6G上安裝—第二傳輪規格裝置（如 傳輸規格硬碟）時，移除該[電阻r f該訊號控制晶透過該訊號二 傳輪規格裝置通訊。同理，該共料接器6〇 : 之間之傳輸線成為-殘段…避免訊 線30上產生之反射影響訊號之完整性，需 工制^-電㉛R1與該共用連接器60間之傳輪線之長 度’使其滿足以下公式：Lstub<(Tj*v)/2 ; v=c//~ se where Lstub represents the jitter of 200919192 between the common connector 6〇 and the second resistor R2, and V is the signal se is the equivalent of the transmission line The length of the transmission line 'Tj is the speed at which the high-speed differential signal can be transmitted in the transmission line, and C is the speed of light and the electrical constant. When the common connection ^ 6G is mounted - the second transmission specification device (such as the transmission specification hard disk), the [resistance r f signal control crystal is transmitted through the signal transmission device specification device. Similarly, the transmission line between the common connector 6〇: becomes a residual segment...the reflection generated on the signal line 30 is prevented from affecting the integrity of the signal, and the transmission between the power supply 31R1 and the shared connector 60 is required. The length of the wheel' makes it satisfy the following formula:
Lstub<(Tj*v)/2 ； v==c//~ £e -、中Lstub代表該共用連接器6〇與第一電阻ri間之 傳輪線長度’ Tj為高速差分訊號可容許 在傳輪線中傳輸之速度，c為光速_為傳輸線之等效； 電常數。 為了減小訊號傳輸損耗，該第一電阻R1及第二電阻 112之電阻值優選為零歐姆。此外，該第一電容C1及第二 電容C2用於濾除差分訊號之共模直流部分，以便得到更 好之傳輸訊號品質，如果差分訊號之共模直流部分很小或 沒有’則可移除該第一電容C1及第二電容C2，以進一步 降低成本，節約佈線空間。該共用連接器6〇也可以是支援 其他裝置之共用連接器，不拘泥於僅僅支援硬碟。 200919192 藉此’只需提供該主機板佈線架構，利 板佈線及共用連接D之主機 置，並使線路工作時都一傳輸規格裝 設計之成本。 D持。“整性，節省了主機板 細上所述，本發明符合發明專利要件，爰依法提出專 利申請。惟，以上所述者僅為本發明之較佳實施方式，舉 凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 少 【圖式簡單說明】 圖1係本發明高速差分訊號傳輸架構較佳實施方式之 示意圖。 【主要元件符號說明】 訊號控制晶片 10 第 一傳輸線 20 第二傳輸線 30 第 二傳輸線 40 訊號轉換晶片 50 共用連接器 60 第一電阻 R1 第 二電阻 R2 第一電容 C1 第 二電容 C2 11Lstub<(Tj*v)/2 ; v==c//~ £e -, the middle Lstub represents the length of the transmission line between the common connector 6〇 and the first resistor ri' Tj is a high-speed differential signal that can be tolerated The speed of transmission in the transmission line, c is the speed of light _ is the equivalent of the transmission line; electrical constant. In order to reduce the signal transmission loss, the resistance values of the first resistor R1 and the second resistor 112 are preferably zero ohms. In addition, the first capacitor C1 and the second capacitor C2 are used to filter the common mode DC portion of the differential signal for better transmission signal quality, and may be removed if the common mode DC portion of the differential signal is small or not. The first capacitor C1 and the second capacitor C2 further reduce the cost and save wiring space. The shared connector 6〇 may also be a shared connector that supports other devices, and is not limited to supporting only a hard disk. 200919192 By this, it is only necessary to provide the motherboard wiring structure, the board layout and the main unit of the connection D, and make the line work to transmit the cost of the specification design. D holds. The invention is in accordance with the invention patent requirements, and the patent application is filed according to law. However, the above description is only a preferred embodiment of the present invention, and those who are familiar with the skill of the present invention Equivalent modifications or variations made in accordance with the spirit of the present invention are intended to be included in the scope of the following claims. Brief Description of the Drawings Figure 1 is a schematic diagram of a preferred embodiment of the high speed differential signal transmission architecture of the present invention. DESCRIPTION OF SYMBOLS] Signal control chip 10 First transmission line 20 Second transmission line 30 Second transmission line 40 Signal conversion chip 50 Common connector 60 First resistor R1 Second resistor R2 First capacitor C1 Second capacitor C2 11