九、發明說明： 【發明所屬之技術領域】 本發明係關於-種積體電路S件之重工方法 去除積體電路元件中金屬内連線膜層缺陷之重工方法曰。 【先前技術】 積體電路7C件之製造極其複雜，通常f要經過數百道 同的製程步财能完成H在這些餘步驟中發生無 法達到製程要求的情況時，即需要進行龍電路元件之重 工 〇 一^^閱第1圖’第丨圖係為___習知金屬内連線結構之剖 面不意圖。近年來為符合積體電路元件高積集度及高整人 度要求，積體電路it件之結構係趨向形成多層的金屬内: Λ〜構以增加内連線與元件或内連線之間的電路連接。 在金屬内連線製程中，通常係於一基底100上依序形成一 底層101與一介電層102，並於其内利用微影、蝕刻等製 ㈣成溝渠’以定義所需之金屬内連線圖案。隨後於溝渠 内依序形成阻障層（barrier layer) 104與金屬層1〇6等，以 也成所站之金屬内連線圖案。隨後如第1圖所示，再辞由 沉積一底層110、一介電層112與一覆蓋層（cap丨ayer)i9i4、 硬遮罩層（hardmasklayer)(圖未示）等，以及微影、蝕刻等 製程定義所需之下一層金屬内連線圖案116，以預備下— 1363399 層金屬内連線層之製作。 月繼’·貝參閱第1圖。然而在前述步驟，例如在沉積製程 '或在㈣製程中，若發生微粒污染，或因微粒之遮罩 (maSking)效應導致金屬内連線圖案116蝕刻不完全，或因 外界因素導致晶圓表面的到傷等缺陷，而使得晶圓無法進 仃下一個製程步驟時，就必須進行重工。否則將會導致完 籲成的積體電路元件良率降低；而嚴重的缺陷甚至可能導致 晶圓報廢等狀況。 【發明内容】 因此，本發明之一目的係在於提供一種去除積體電路元 件如金屬内連線膜層缺陷之重工製程，已減少積體電路元 件報廢所產生的成本損失。 • 根據本發明所提供之申請專利範圍，係提供一種積體電 路元件之重工方法。該重工方法包含有提供一依序包含有 一第一底層與一第一介電層之基底，隨後進行一第一乾蝕 刻（dry etching)製程以移除該第一介電層；進行一化學機械 研磨（CMP)製程。最後於該基底上依序重新形成一第+二底" 層與一第二介電層。 ' 根據本發明之申請專利範圍，另提供一種積體電路元件 7 1363399 底層 第 之重工方法。該重工方法包含有提供一依序包含有一第一 底層、—第-介電層、與-第-覆蓋層之基底，且 二盖:：該第一介電層内係形成有至少一金屬内連線圖 案。W依序進行-第-乾_製程與—第二乾餘刻製 程^分別移除該第-覆蓋層與該第—介電層。待該第一 覆盍層與該第-介電層移除後·，係進行- CMP製程，已移 除該第一底層。最後，依序重新形成—第 介電層與一第二覆蓋層。 根據本發明所提供之重工方法，係可在金屬内連線之膜 層檢測出缺陷時，或者金屬内連線圖案之形成未達桿準 時，快速而有效地去除必須重新製作臈層。故可減少積體 電路元件報廢的情形，較晶片因報廢所造叙損失，同 時降低生產成本。 ' 【實施方式】 請參考第2圖至第6圖，第2圖至第6圖係本發明所提 供之積體電路重工方法之一第一較佳實施例之示意圖。如 第2圖所示’首先提供一積體電路元件2〇〇，其包含有一 基底202，基底202上可包含有至少一金屬内連線(metal interconnection)層204。基底202上包含有一第一底層2〇6 與一第一介電層208。第一底層206可包含有氮化矽（silic〇n nitride，以下簡稱為SiN);而第一介電層208則可包含有 8 silicon glass， 以下簡稱為FSG)。 5青參閱第2圖與第3圖。積體電路元件200經過沉積後 檢'則而未通過該檢測時，即進行一乾姓刻（dry etching)製程 以移除該第一介電層208。值得注意的是，乾蝕刻製程 250對於第一介電層208與第一底層206係具有一高蝕刻 選擇比。舉例來說，乾蝕刻製程250係可利用氧氣與氟碳 化 5 物’如八氟環戊烯（octafluorocyclopentene，C5Fs) ’ 作 為反應氣體’其較佳之比例可為2:3，然不限於此。而利用 上述反應氣體之乾蝕刻製程250對構成第一介電層208之 FSG之蝕刻速率約為每秒鐘65埃（A/sec);對構成第一底 層206之SiN之融刻速率則約為4 A/sec。 請參閱第4圖。待第一介電層208移除後，係可如第4 圖所示於第一底層206上重新形成一第二介電層220。而 第二介電層220與第一介電層208相同，係可包含有FSG， 且第一介電層208與第二介電層220皆係用以作為金屬層 間介電層（inter metal dielectric，IMD layer)。 接下來請參閱第3圖與第5圖。在乾蝕刻製程250用以 移除第一介電層208後，亦可藉由一化學機械研磨 (chemical mechanic polish ’以下簡稱為CMP)製程移除第— 底層206。由於乾蝕刻製程250對第一介電層208與第— 1363399 底層206具有一高蝕刻比，因此即使第一底層2〇6在乾蝕 刻製程250中有所耗損，也不會過於影響其表面均勻度 (uniformity)，故可利用CMp製程將其移除。請參閱第6 圖。當所有未通過沉積後檢測之膜層皆移除後，即可於基 底202上重新形成一第二底層222，第二底層222係可與 第一底層206相同，包含有si]s^隨後於第二底層222上 形成第二介電層220。 請參閱第7圖至第1〇圖，第7圖至第10圖係為本哿明 所提供之積體電路重工方法之第二較佳實施例之示意圖。 如第7圖所示，首先提供一積體電路元件200，其包含有 一基底202，基底202上可包含有至少一金屬内連線層 204。基底202上依序包含有一第一底層206、一第一介電 層208、與一第一覆蓋層（cap layer) 210。第一底層206可 包含有SiN，第一介電層208可包含有FSG，而第一覆蓋 層210則可包含有氮氧化石夕（silicon oxynitride，以下簡稱為 SiON)。 請參閱第7圖至第8圖。積體電路元件200經過沉積後 檢測而未通過該檢測時，即進行一乾蝕刻製程260以移除 該第一覆蓋層210。待移除第一覆蓋層210後，係利用另 一乾蝕刻製程250移除第一介電層208。值得注意的是， 乾蝕刻製程250對第一介電層208與第一底層206係具有 1363399 一高#刻選擇比，如對構成第一介電層208之FSG之蝕刻 速率為65A/sec ;而對構成第一底層206之SiN之蝕刻速 率為4A/sec。舉例來說，乾蝕刻製程25〇係可利用氧氣與 氟碳化合物’如八氟環戊烯(C5F8)，作為反應氣體，其較佳 之比例可為2:3 ’然不限於此。而利用上述反應氣體之乾蝕 3 刻製程250對構成第一介電層208之FSG之蝕刻速率約為 每秒鐘65埃（A/sec);對構成第一底層206之SiN之蝕刻 速率則約為4 A/sec。 0 ^ 請參閱第9圖。待第一覆蓋層210與第一介電層208移 除後，係可如第9圖所示於第一底層206上依序重新形成 一第二介電層220與一第二覆蓋層224。第二介電層22〇 與第一介電層208相同，係可包含有FSG，且第一介電層 208與第二介電層220皆係用以作為金屬層間介電層。而 第二覆蓋層224則可與第一覆蓋層21〇相同包含有Si〇N。 另外’在用以移除第一介電層208的乾I虫刻製程250 後，亦可藉由一 CMP製程移除第一底層206，而CMP製 程之結果則如剐述第5圖所示。由於乾触刻製程25〇對第 一介電層208與第一底層2〇6具有一高蝕刻比，因此即使 第一底層206在乾蝕刻製程25〇中有所耗損，也不會過於 影響其表面均勻度，故可利用CMP製程將其移除。請參閱 第10圖，待所有未通過沉積後檢測之膜層皆移除後，即可 丄: 於基底202上依序重新形成一第二底層奶、一第二介電 S 220與第一覆蓋層224。而第二底層222係可與第一 底層206相同，包含有SiN。 根據本發崎提供之第—與第二較佳實關，當積體電 路疋件200上所形成之膜層如第一底層206、第-介電層 08 ”第覆蓋層210未通過沉積後檢測時，或因其他因 修素造成上述膜層之刮損時，即可利用本發明所提供之重工 方法即時騎频電路元件謂層之重王，減低積體 電路το件2GG報廢的情形，㈣亦可降低因晶片報廢所產 生的損失。 接下來凊參閱第11圖至第16圖，第11圖至第16圖係 本發明所提供之積體電職工方法之第三難實施例之示 意^如第U圖所示，首先提供—積體電路元件3〇〇，其 ^ 3有基底302，基底302上可包含有至少一金屬内連 在層304基底302上依序包含有-第-底層306、-用以 作為金屬層間介電層之第—介電層遍、與第一覆蓋層 31〇。如前所述，第一底層306可包含有SiN，第一介電層 308可包含有FSG，而第一覆蓋層則則可包含有$謂。 另外，第—覆蓋層310與第一介電層3〇8内尚有一與 影或餘刻製程所形成之金屬内連線圖案320，而第一底層 3〇6係如第11圖所示，暴露於金屬内連線圖案320之底部。 12 1363399 請參閱第12圖。若積體電路元件300未通過一蝕刻後 檢測（after-etching-inspection，AEI)，即可進行本發明所提 供之重工方法。首先於第一覆蓋層310上形成一保護層 322，保護層322之材料可為一光阻，並利用一旋轉塗佈 (spin on coating)製程形成於第一覆蓋層310上。隨後係進 行一回蝕刻製程，以回蝕刻保護層322至低於金屬内連線 圖案320之開口。 請參閱第13圖。接下來進行一乾蝕刻製程350以移除 第一覆蓋層310。乾蝕刻製程350對第一覆蓋層310與保 護層322係具有一高蝕刻選擇比，舉例來說，乾蝕刻製程 350係可利用氧氣、三氟曱烧(fluoroform，CH3F)、與氮氣 作為反應氣體，其較佳之比例可為1:12:24，然不限於此。 而包含有上述反應氣體之乾蝕刻製程350對構成第一覆蓋 層310之SiON之蝕刻速率為45 A/sec ;對構成保護層322 之光阻之蝕刻速率則為0 A/sec。 值得注意的是，通常用以蝕刻SiON之反應氣體對於siN 也具有一定的蝕刻能力，例如以氧氣、三氟曱烷、與氮氣 作為反應氣體之乾蝕刻製程對SiN之蝕刻速率即為35 A/sec。因此可能造成第一底層306在乾敍刻製程350中亦 被消耗，甚至露出第一底層306下方之銅導線。然而，由 於保護層322係填充於金屬内連線圖案320之内，而乾|虫 13 1363399 刻製程350之反應氣體對於保護層如光阻之蝕刻速率極 低，因此保護層322之設置係可阻絕第一底層306接觸乾 蝕刻製程350之反應氣體，故可保護第一底層306免於被 蝕刻，同時保護其下方的銅導線。另外值得注意的是，由 於保護層322係被回蝕刻至低於金屬内連線圖案320之開 口，也就是說，第一覆蓋層310上不會殘留任何保護層 322,因此乾蝕刻製程350係可完全地移除第一覆蓋層310。 請參閱第13圖與第14圖。待第一覆蓋層310移除後， 隨即係進行另一乾蝕刻製程360，以移除第一介電層306。 而在保護層322移除後，係可如第14圖所示，於第一底層 306上依序重新形成一第二介電層330與一第二覆蓋層 334，以預備重新形成金屬内連線圖案。第二介電層330與 第一介電層308相同，係可包含有FSG，且第一介電層308 與第二介電層330皆係用以作為金屬層間介電層。而第二 覆蓋層334則可與第一覆蓋層310相同包含有SiON。 乾蝕刻製程360對第一介電層308與第一底層306係具 有一高蝕刻選擇比，如對構成第一介電層308之FSG之蝕 刻速率為65 A/sec ;而對構成第一底層306之SiN之I虫刻 速率為4 A/sec。舉例來說，乾蝕刻製程360係可利用氧氣 與氟碳化合物，如八氟環戊烯(octafluorocyclopentene ’ C5F8)，作為反應氣體，其較佳之比例可為2:3，然不限於此。 14 1363399 另外，如第15圖所示，在用以移除第一介電層3〇8的 乾#刻製程360後，亦可藉由一 CMP製程移除第一底芦 306。由於乾蝕刻製程360對第一介電層3〇8與第—底層 306具有一高蝕刻比，因此即使第一底層3〇6在乾蝕刻製 程360中有所耗損，也不會過於影響其表面均勻度，故可 利用CMP製程將其移除。請參閱第丨6圖，待所有未通過 AEI之膜層皆移除後，即可於基底3〇2上依序重新形成一 • 第二底層332、一第二介電層330、與一第二覆蓋層334。 而第二底層332係可與第一底層306相同，包含有SiN。 而此完成重工之積體電路元件300即可重新預備進行金屬 内連線圖案之製作。 根據本發明所提供之第三較佳實施例，當金屬内連線圖 案320未通過飯刻後檢測(αεί)，例如微粒之遮罩（咖咖叫) 鲁 效應導致金屬内連線圖案320蝕刻不完全時，即可利用本 發明所提供之重工方法即時進行積體電路元件3〇〇上膜層 之重工，減低積體電路元件3〇〇報廢的情形。 縱上所述，本發明所提供之重工方法，係可在積體電路 疋件上之膜層，如底層、介電層、或覆蓋層未通過測試時， 或因其他因素造成膜層的刮損時，即時進行重工，快速而 有效的移除該等必須重新製作的膜層。而當積體電路元件 上的金屬内連線圖案未通過蝕刻後測試，或遭受因其他因 15 1363399 素造成金屬内連線圖案的塌損時，亦可根據本發明所提供 之方法立時進行重工，快速而有效的移除該等必須重新製 作的膜層，故可減少積體電路元件報廢的情形，避免晶片 因報廢所造成之損失，同時降低生產成本。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係為一習知金屬内連線結構之剖面示意圖。 第2圖至第6圖係本發明所提供之積體電路重工方法之第 一較佳實施例之示意圖。 第7圖至第1〇圖係為本發明所提供之積體電路重工方法之 第二較佳實施例之示意圖。 第11圖至第16圖係本發明所提供之積體電路重工方法之 第二較佳實施例之示意圖。 【主要元件符號說明】 100 基底 102 介電層 104 阻障層 106 金屬層 101、110 底層 112 介電層 114 覆蓋層 116 金屬内連線圖案 200 積體電路元件 202 基底 16 金屬内連線層 206 第一底層 第一介電層 210 第一覆蓋層 第二介電層 222 第二底層 第二覆蓋層 250、 260乾蝕刻製程 積體電路元件 302 基底 金屬内連線層 306 第一底層 第一介電層 310 第一覆蓋層 金屬内連線圖案 322 保護層 第二介電層 332 第二底層 第二覆蓋層 350、360乾蝕刻製程 17IX. Description of the Invention: [Technical Field] The present invention relates to a method for reworking a S-type integrated circuit S-piece to remove a defect of a metal interconnect film layer in an integrated circuit component. [Prior Art] The manufacturing of the integrated circuit 7C is extremely complicated. Usually, it takes hundreds of identical process steps to complete the H. In the case where the process requirements cannot be met in these remaining steps, the device components need to be performed. Heavy work 〇 ^ ^ ^ Read the first picture 'the second picture is ___ the structure of the metal interconnect structure is not intended. In recent years, in order to meet the high integration and high humanity requirements of integrated circuit components, the structure of integrated circuit components tends to form a multi-layered metal: Λ~ structure to increase the interconnection between components and interconnects Circuit connection. In the metal interconnect process, a bottom layer 101 and a dielectric layer 102 are sequentially formed on a substrate 100, and a dipole is formed therein by using lithography, etching, etc. to define a desired metal. Connection pattern. Then, a barrier layer 104 and a metal layer 1〇6 and the like are sequentially formed in the trench to form a metal interconnection pattern of the station. Then, as shown in FIG. 1, a bottom layer 110, a dielectric layer 112 and a cap layer (i) i9i4, a hard mask layer (not shown), and the like, and lithography, A process such as etching defines a desired metal interconnect pattern 116 to prepare the underlying layer of the 1363399 metal interconnect layer. See the first picture of the month. However, in the foregoing steps, for example, in the deposition process or in the (four) process, if the particle contamination occurs, or the metal interconnection pattern 116 is incompletely etched due to the particle mason effect, or the wafer surface is caused by external factors. Rework is necessary when the wafer is unable to enter the next process step due to defects such as injury. Failure to do so will result in a reduction in the yield of the completed integrated circuit components; serious defects may even result in wafer scrapping and the like. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a rework process for removing defects of an integrated circuit component such as a metal interconnect film layer, which has reduced the cost loss caused by the scrapping of the integrated circuit component. • The scope of the patent application provided by the present invention provides a method of reworking an integrated circuit component. The method of reworking includes providing a substrate including a first underlayer and a first dielectric layer in sequence, followed by a first dry etching process to remove the first dielectric layer; performing a chemical mechanical process Grinding (CMP) process. Finally, a +2nd layer & a second dielectric layer are sequentially formed on the substrate. According to the patent application scope of the present invention, there is further provided a method of reworking the integrated circuit component 7 1363399. The method of reworking includes providing a substrate including a first underlayer, a first dielectric layer, and a first cladding layer, and a cover: the first dielectric layer is formed with at least one metal Connection pattern. W sequentially performs a first-dry process and a second dry process to remove the first cap layer and the first dielectric layer, respectively. After the first capping layer and the first dielectric layer are removed, the CMP process is performed, and the first underlayer is removed. Finally, the first dielectric layer and the second cladding layer are sequentially formed. According to the rework method provided by the present invention, it is possible to quickly and efficiently remove the ruthenium layer when the defect is detected in the film layer of the metal interconnection or when the formation of the metal interconnection pattern is not reached. Therefore, the situation in which the integrated circuit components are scrapped can be reduced, and the production cost can be reduced at the same time as the wafers are lost due to scrapping. [Embodiment] Please refer to Figs. 2 to 6 and Fig. 2 to Fig. 6 are schematic views showing a first preferred embodiment of the integrated circuit rework method provided by the present invention. As shown in Fig. 2, an integrated circuit component 2 is first provided which includes a substrate 202 which may include at least one metal interconnection layer 204. The substrate 202 includes a first bottom layer 2〇6 and a first dielectric layer 208. The first underlayer 206 may include silicium nitride (hereinafter referred to as SiN); and the first dielectric layer 208 may include 8 silicon glass (hereinafter abbreviated as FSG). 5 Green refers to Figure 2 and Figure 3. After the integrated circuit component 200 is deposited and then not passed, a dry etching process is performed to remove the first dielectric layer 208. It is noted that the dry etch process 250 has a high etch selectivity ratio for the first dielectric layer 208 and the first bottom layer 206. For example, the dry etching process 250 can utilize oxygen and fluorocarbon 5 such as octafluorocyclopentene (C5Fs) as a reactive gas. The preferred ratio can be 2:3, but is not limited thereto. The etch rate of the FSG constituting the first dielectric layer 208 by the dry etching process 250 using the above reactive gas is about 65 angstroms per second (A/sec); and the etch rate of the SiN constituting the first underlayer 206 is about It is 4 A/sec. Please refer to Figure 4. After the first dielectric layer 208 is removed, a second dielectric layer 220 can be formed on the first underlayer 206 as shown in FIG. The second dielectric layer 220 is the same as the first dielectric layer 208, and may include an FSG, and the first dielectric layer 208 and the second dielectric layer 220 are used as an inter-metal dielectric layer (inter metal dielectric). , IMD layer). Next, please refer to Figure 3 and Figure 5. After the dry etching process 250 is used to remove the first dielectric layer 208, the first underlayer 206 may also be removed by a chemical mechanical polish (hereinafter referred to as CMP) process. Since the dry etch process 250 has a high etch ratio between the first dielectric layer 208 and the first 363399 bottom layer 206, even if the first underlayer 2 〇 6 is worn out in the dry etch process 250, it does not affect the surface uniformity too much. Uniformity, so it can be removed using the CMp process. Please refer to Figure 6. When all the layers that have not been detected by the deposition are removed, a second bottom layer 222 can be formed on the substrate 202. The second bottom layer 222 can be the same as the first bottom layer 206, including the si]s^ A second dielectric layer 220 is formed on the second underlayer 222. Please refer to FIG. 7 to FIG. 1 , and FIG. 7 to FIG. 10 are schematic diagrams showing a second preferred embodiment of the integrated circuit rework method provided by the present invention. As shown in FIG. 7, an integrated circuit component 200 is first provided that includes a substrate 202 that can include at least one metal interconnect layer 204. The substrate 202 includes a first bottom layer 206, a first dielectric layer 208, and a first cap layer 210. The first bottom layer 206 may include SiN, the first dielectric layer 208 may include FSG, and the first cover layer 210 may include silicon oxynitride (hereinafter referred to as SiON). Please refer to Figures 7 to 8. When the integrated circuit component 200 is detected after deposition and does not pass the detection, a dry etching process 260 is performed to remove the first cap layer 210. After the first cap layer 210 is removed, the first dielectric layer 208 is removed using another dry etch process 250. It should be noted that the dry etching process 250 has a 1363399-high selection ratio for the first dielectric layer 208 and the first bottom layer 206, such as an etch rate of 65 A/sec for the FSG constituting the first dielectric layer 208; The etching rate for the SiN constituting the first underlayer 206 is 4 A/sec. For example, the dry etching process can utilize oxygen and a fluorocarbon such as octafluorocyclopentene (C5F8) as a reactive gas, and a preferred ratio thereof can be 2:3'. The etching rate of the FSG constituting the first dielectric layer 208 by the dry etching process 250 of the above reactive gas is about 65 angstroms per second (A/sec); and the etching rate of the SiN constituting the first underlayer 206 is It is about 4 A/sec. 0 ^ Please refer to Figure 9. After the first cap layer 210 and the first dielectric layer 208 are removed, a second dielectric layer 220 and a second cap layer 224 are sequentially formed on the first underlayer 206 as shown in FIG. The second dielectric layer 22 is the same as the first dielectric layer 208, and may include an FSG, and the first dielectric layer 208 and the second dielectric layer 220 are used as a metal interlayer dielectric layer. The second cover layer 224 may include Si〇N as the first cover layer 21〇. In addition, after the dry I process 250 for removing the first dielectric layer 208, the first underlayer 206 can also be removed by a CMP process, and the result of the CMP process is as shown in FIG. . Since the dry etch process 25 〇 has a high etching ratio to the first dielectric layer 208 and the first underlayer 2 〇 6 , even if the first underlayer 206 is worn out in the dry etching process 25 ,, it does not affect the Surface uniformity, so it can be removed by CMP process. Referring to FIG. 10, after all the layers that have not been detected by the deposition are removed, the second layer of milk, a second dielectric S 220 and the first cover are sequentially formed on the substrate 202. Layer 224. The second bottom layer 222 can be the same as the first bottom layer 206 and contains SiN. According to the first and second preferred embodiments provided by the present invention, when the film layer formed on the integrated circuit component 200, such as the first underlayer 206, the first dielectric layer 08, the cap layer 210 is not deposited, At the time of detection, or due to other scratches caused by the repair of the film layer, the heavy-duty method provided by the present invention can be used to immediately ride the frequency circuit component to be the king of the layer, and reduce the situation that the integrated circuit τ ο 2GG is scrapped. (4) It is also possible to reduce the loss caused by the scrapping of the wafer. Next, referring to Fig. 11 to Fig. 16, Fig. 11 to Fig. 16 are schematic diagrams showing the third difficult embodiment of the integrated electric worker method provided by the present invention. As shown in FIG. U, first, an integrated circuit component 3 is provided, which has a substrate 302, and the substrate 302 may include at least one metal interconnected on the substrate 304 of the layer 304. The bottom layer 306 is used as the first dielectric layer of the inter-metal dielectric layer, and the first cladding layer 31. As described above, the first bottom layer 306 may include SiN, and the first dielectric layer 308 may include There is FSG, and the first overlay layer can contain $. In addition, the first overlay layer 310 and the first The dielectric layer 3〇8 has a metal interconnection pattern 320 formed by a shadow or a process, and the first bottom layer 3〇6 is exposed to the bottom of the metal interconnection pattern 320 as shown in FIG. 12 1363399 Please refer to Fig. 12. If the integrated circuit component 300 does not pass an after-etching-inspection (AEI), the rework method provided by the present invention can be performed. First, on the first cover layer 310. A protective layer 322 is formed. The material of the protective layer 322 can be a photoresist and formed on the first cap layer 310 by a spin on coating process. Then an etching process is performed to etch back. The layer 322 is lower than the opening of the metal interconnect pattern 320. Please refer to Fig. 13. Next, a dry etching process 350 is performed to remove the first cap layer 310. The dry etching process 350 pairs the first cap layer 310 and the cap layer 322 The system has a high etching selectivity. For example, the dry etching process 350 can utilize oxygen, fluoroform (CH3F), and nitrogen as the reactive gas, and the preferred ratio can be 1:12:24. Not limited to this. The gas dry etching process 350 has an etching rate of 45 A/sec for the SiON constituting the first cladding layer 310, and an etching rate of 0 A/sec for the photoresist constituting the protective layer 322. It is worth noting that The reaction gas for etching SiON also has a certain etching ability for siN, for example, the etching rate of SiN by dry etching process using oxygen, trifluorodecane, and nitrogen as a reactive gas is 35 A/sec, thus possibly causing the first underlayer. 306 is also consumed in the dry etch process 350, even exposing the copper wires under the first bottom layer 306. However, since the protective layer 322 is filled in the metal interconnect pattern 320, and the etching rate of the reactive gas of the dry film 13 1363399 process 350 to the protective layer such as photoresist is extremely low, the protective layer 322 can be disposed. The first underlayer 306 is prevented from contacting the reactive gas of the dry etching process 350, so that the first underlayer 306 can be protected from being etched while protecting the copper wires underneath. It is also worth noting that since the protective layer 322 is etched back to the opening lower than the metal interconnect pattern 320, that is, no protective layer 322 remains on the first cap layer 310, the dry etching process is 350 The first cover layer 310 can be completely removed. Please refer to Figure 13 and Figure 14. After the first cap layer 310 is removed, another dry etch process 360 is performed to remove the first dielectric layer 306. After the protective layer 322 is removed, a second dielectric layer 330 and a second cladding layer 334 are sequentially formed on the first bottom layer 306 as shown in FIG. 14 to prepare for re-forming the metal interconnect. Line pattern. The second dielectric layer 330 is the same as the first dielectric layer 308, and may include an FSG, and the first dielectric layer 308 and the second dielectric layer 330 are both used as a metal interlayer dielectric layer. The second cover layer 334 may include SiON as the first cover layer 310. The dry etch process 360 has a high etch selectivity ratio for the first dielectric layer 308 and the first bottom layer 306, such as an etch rate of 65 A/sec for the FSG constituting the first dielectric layer 308; The SiN of 306 has a I insect engraving rate of 4 A/sec. For example, the dry etching process 360 may utilize oxygen and a fluorocarbon such as octafluorocyclopentene 'C5F8 as the reactive gas, and the preferred ratio may be 2:3, but is not limited thereto. 14 1363399 In addition, as shown in FIG. 15, after the dry etching process 360 for removing the first dielectric layer 3〇8, the first bottom reed 306 can also be removed by a CMP process. Since the dry etching process 360 has a high etching ratio to the first dielectric layer 3〇8 and the first bottom layer 306, even if the first underlying layer 3〇6 is worn out in the dry etching process 360, the surface thereof is not excessively affected. Uniformity, so it can be removed using a CMP process. Referring to Figure 6, after all the layers that have not passed through the AEI are removed, a second bottom layer 332, a second dielectric layer 330, and a first layer can be sequentially formed on the substrate 3〇2. Two cover layers 334. The second bottom layer 332 can be the same as the first bottom layer 306 and includes SiN. On the other hand, the integrated circuit component 300 of the rework can be re-prepared for the production of the metal interconnection pattern. According to the third preferred embodiment of the present invention, when the metal interconnect pattern 320 is not detected after the meal (αεί), for example, the mask of the particles (the café) causes the metal interconnect pattern 320 to be etched. When it is incomplete, the rework method of the integrated circuit component 3 can be performed in real time by using the rework method provided by the present invention, and the situation in which the integrated circuit component 3 is scrapped can be reduced. In the longitudinal direction, the rework method provided by the present invention is that the film layer on the integrated circuit component, such as the bottom layer, the dielectric layer, or the cover layer fails to pass the test, or the film layer is scratched due to other factors. At the time of damage, rework is performed immediately, and the layers that must be reworked are quickly and efficiently removed. When the metal interconnection pattern on the integrated circuit component is not tested by etching, or suffers from the collapse of the metal interconnection pattern due to other factors, the method can also be reworked according to the method provided by the present invention. The film layer which must be re-made is quickly and effectively removed, so that the scrapping of the integrated circuit component can be reduced, the loss of the wafer due to scrapping can be avoided, and the production cost can be reduced. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional metal interconnect structure. 2 to 6 are views showing a first preferred embodiment of the integrated circuit rework method provided by the present invention. 7 to 1 are schematic views showing a second preferred embodiment of the integrated circuit rework method provided by the present invention. 11 to 16 are views showing a second preferred embodiment of the integrated circuit rework method provided by the present invention. [Main component symbol description] 100 substrate 102 dielectric layer 104 barrier layer 106 metal layer 101, 110 underlayer 112 dielectric layer 114 cladding layer 116 metal interconnect pattern 200 integrated circuit component 202 substrate 16 metal interconnect layer 206 First underlayer first dielectric layer 210 first overlayer second dielectric layer 222 second underlayer second cap layer 250, 260 dry etch process integrated circuit component 302 base metal interconnect layer 306 first bottom layer first Electrical layer 310 first cover metal interconnect pattern 322 protective layer second dielectric layer 332 second bottom layer second cover layer 350, 360 dry etching process 17