200921844 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種積體電路元件之重工方法，尤指一種 去除積體電路元件巾金屬内―層缺陷之重工方法。 【先前技術】 積體電路元件之製造極其複雜，通常需要經過數百道不 同的製程步财能完成n在這㈣財财發生無 法達到製程要求的情料’即需要進行積體電路元件之重 工。 請立參閱第^圖’第i圖係為一習知金屬内連線結構之剖 面不忍圖。近年來為符合積體電路元件高積集度及高整人 度要求’龍電路元狀結觸趨向形成多層的金屬㈣ 線結構，以增加㈣線與元件或岐線之_電路連接。 在金屬内連線製程中，通常係於—基底⑽上依序形成一 底層101與-介電層102，並於其内利用微影、韻刻等梦 程形成溝渠’以定義所需之金屬内連線圖案。隨後於溝渠 内依序形成阻障層（barrier layer) 104與金屬層1〇6等，以 形成所需之金屬内連線圖案。隨後如第！圖所示，再藉由 :冗積-底層U0、一介電層112與—覆蓋層二、 硬遮f層（hard mask layer)(圖未示）等，以及微影、蝕刻等 製柽火義所需之下一層金屬内連線圖案116，以預備下一 200921844 層金屬内連線層之製作。 請繼續參閱第1圖。然而在前述步驟，例如在沉積製程， 或在I虫刻製程中，若發生微粒污染，或因微粒之遮罩 (masking)效應導致金屬内連線圖案116蝕刻不完全，或因 外界因素導致晶圓表面的刮傷等缺陷，而使得晶圓無法進 行下一個製程步驟時，就必須進行重工。否則將會導致完 成的積體電路元件良率降低；而嚴重的缺陷甚至可能導致 晶圓報廢等狀況。 【發明内容】 口此本么明之一目的係在於提供一種去除積體電路元 件如金屬内連線膜層缺陷之重工製程，已減少積體電路元 件報廢所產生的成本損失。 根據本發明所提供之申請專利範圍，係提供一種積體電 路几件之重工方法。該重卫方法包含有提供—依序包含有 一第一底層與—第—介電層之基底，隨後進行-第-乾韻 刻㈣etching)製程以移除該第一介電層；進行一化學 研磨（CMP)製程。最後於該基底上依序重新形成-第二底 層與一第二介電層。 " 根據本發明之申請糊範圍，另提供—種積體電路元件 200921844 之重工方法。該重工方法包含有提供一依序包含有—第— 底層、一第一介電層、與一第一覆蓋層之基底，且該第一 覆蓋層與該第一介電層内係形成有至少一金屬内連線圖 案。1¼後依序進行一第一乾餘刻製程與一第二乾姓刻製 程’以分別移除該第一覆蓋層與該第一介電層。待該第— 覆蓋層與該第一介電層移除後’係進行一 CMP製程，已移 除s玄第一底層。最後，依序重新形成一第二底層、„第_ 介電層與一第二覆蓋層。 根據本發明所提供之重工方法，係可在金屬内連線之膜 層檢測出缺陷時，或者金屬内連線圖案之形成未達標準 時，快速而有效地去除必須重新製作膜層。故可減少積體 電路元件報廢的情形，避免晶片因報廢所造成之損失，同 時降低生產成本。 【實施方式】 請參考第2圖至第6圖’第2圖至第6圖係本發明所提 供之積體電路重工方法之一第一較佳實施例之示意圖。如 第2圖所示，首先提供一積體電路元件2〇〇，其包含有一 基底202 ’基底202上可包含有至少一金屬内連線(metal interconnection)層204。基底202上包含有一第一底層206 與一第一介電層208。第一底層206可包含有氮化矽（silic〇n nitride ’以下簡稱為SiN);而第一介電層208則可包含有 200921844 氟石夕玻璃（fluoride silicon glass ’以下簡稱為FSG)。 請參閱第2圖與第3圖。積體電路元件200經過沉積後 檢測而未通過該檢測時，即進行一乾敍刻（dry etching)製矛w 250以移除該第一介電層208。值得注意的是，乾餘刻製^ 250對於第一介電層208與第一底層206係具有一高餘刻 選擇比。舉例來說，乾蝕刻製程250係可利用氧氣與氣石户 化合物，如八II環戊稀（octafluorocyclopentene， C5Fs) 作 為反應氣體，其較佳之比例可為2:3，然不限於此。 上述反應氣體之乾蝕刻製程250對構成第一介電層2〇8 < FSG之敍刻速率約為每秒鐘65埃（A/sec);對構成第—底 層206之SiN之|虫刻速率則約為4 A/sec。 請參閱第4圖。待第一介電層208移除後，係可如第4 圖所示於第一底層206上重新形成一第二介電層220。而 第二介電層220與第一介電層208相同，係可包含有FSg， 且第一介電層208與第二介電層220皆係用以作為金屬層 間介電層（inter metal dielectric，IMD layer)。 接下來請參閱第3圖與第5圖。在乾蝕刻製程250用以 移除第一介電層208後，亦可藉由一化學機械研磨 (chemical mechanic polish，以下簡稱為CMP)製程移除第一 底層206。由於乾蝕刻製程250對第一介電層208與第一 200921844 底層206具有一高蚀刻比，因此即使第〜 刻製程250中有所耗損，也不會過於影響 (uniformity) ’故可利用CMP製程將其移匕 圖。當所有未通過沉積後檢測之膜層 底層206在乾蝕 其表面均勻度 請參閱第6 底202上重新形成一第二底層222，第 白移除後，即可於基 第一底層206相同，包含有SiN 形成第二介電層220。 ‘底層222係可與 ^後於第二底層222上 請參閱第7圖至第10圖，第7圖至筮门/ Μ芝弟丨〇圖係為本發明 所提供之積體電路重王方法之第二較佳實_之示意圖。 如第7圖所示，首先提供一積體電路元件2〇〇，其包含有 一基底202，基底202上可包含有至少一金屬内連線層 204。基底202上依序包含有一第一底層2〇6、一第一介電 層208、與一第一覆蓋層（cap iayer) 21〇。第一底層2〇6可 包含有SiN ’第一介電層208可包含有fsG，而第一覆蓋 層210則可包含有氮氧化矽（sincon 〇XynitHde，以下簡稱為 SiON)。 請參閱第7圖至第8圖。積體電路元件2〇〇經過沉積後 檢測而未通過該檢測時，即進行一乾钮刻製程260以移除 該第一覆蓋層210。待移除第一覆蓋層21〇後，係利用另 一乾蝕刻製程250移除第一介電層2〇8。值得注意的是， 乾蝕刻製程250對第一介電層208與第一底層206係具有 200921844 一高蝕刻選擇比，如對構成第一介電層208之FSG之蝕刻 速率為65A/sec ;而對構成第一底層206之SiN之蝕刻速 率為4 A/sec。舉例來說，乾蝕刻製程250係可利用氧氣與 氟碳化合物，如八氟環戊烯(C5F8)，作為反應氣體，其較佳 之比例可為2:3，然不限於此。而利用上述反應氣體之乾|虫 刻製程250對構成第一介電層208之FSG之蝕刻速率約為 每秒鐘65埃（A/sec);對構成第一底層206之SiN之蝕刻 速率則約為4 A/sec。 請參閱第9圖。待第一覆蓋層210與第一介電層208移 除後，係可如第9圖所示於第一底層206上依序重新形成 一第二介電層220與一第二覆蓋層224。第二介電層220 與第一介電層208相同，係可包含有FSG，且第一介電層 208與第二介電層220皆係用以作為金屬層間介電層。而 第二覆蓋層224則可與第一覆蓋層210相同包含有SiON。 另外，在用以移除第一介電層208的乾蝕刻製程250 後，亦可藉由一 CMP製程移除第一底層206，而CMP製 程之結果則如前述第5圖所示。由於乾蝕刻製程250對第 一介電層208與第一底層206具有一高姓刻比，因此即使 第一底層206在乾蝕刻製程250中有所耗損，也不會過於 影響其表面均勻度，故可利用CMP製程將其移除。請參閱 第10圖，待所有未通過沉積後檢測之膜層皆移除後，即可 11 200921844 於基底202上依序重新形成一第二底層222、一第二介電 層220、與一第二覆蓋層224。而第二底層222係可與第一 底層206相同’包含有。 根據本發明所提供之第一與第二較佳實施例，當積體電 路元件200上所形成之膜層如第一底層a%、第一介電層 208、與第一覆蓋層21〇未通過沉積後檢測時，或因其他因 素造成上述膜層之刮損時，即可利用本發明所提供之重工 方法即時進行積體電路元件2〇〇上膜層之重工’減低積體 電路tl件2GG報廢的情形，同時亦可降低因晶片報廢所產 生的損失。 接下來凊參閱第11圖至第16圖，第u圖至第16圖係 本發明所提供之積體電路重丄方法之第三較佳實施例之示 意圖。如第11圖所示，首先提供一積體電路元件3〇〇，其 包含有一基底302，基底302上可包含有至少一金屬内連 線層304。基底302上依序包含有一第一底層3〇6、一用以 作為金屬層間介電層之第一介電層3〇8、與第一覆蓋層 31〇。如前所述，第一底層3〇6可包含有SiN，第一介電層 308可包含有FSG，而第—覆蓋層31G則可包含有si〇N。 另外’第-覆蓋層310與第一介電層駕内尚有一藉由微 影或蝕刻製程所形成之金屬内連線圖案32〇，而第一底層 3〇6係如第11圖所示，暴露於金屬内連線圖案32〇之底部。 12 200921844 請參閱第12圖。若積體電路元件300未通過一蝕刻後 檢測（after-etching-inspection，AEI) ’即可進行本發明所提 供之重工方法。首先於第一覆蓋層310上形成一保護層 322，保護層322之材料可為一光阻，並利用一旋轉塗佈 (spin on coating)製程形成於第一覆蓋層310上。隨後係進 行一回蝕刻製程，以回蝕刻保護層322至低於金屬内連線 圖案320之開口。 請參閱第13圖。接下來進行一乾蝕刻製程35〇以移除 第一覆蓋層310。乾蝕刻製程350對第一覆蓋層31〇與保 護層322係具有一高蝕刻選擇比，舉例來說，乾餘刻製程 350係可利用氧氣、三氟曱炫(fluoroform，CH3F)、與氣氣 作為反應氣體，其較佳之比例可為1:12:24，然不限於此。 而包含有上述反應氣體之乾蝕刻製程350對構成第—覆蓋 層310之SiON之敍刻速率為45 A/sec ;對構成保護芦322 之光阻之蝕刻速率則為0 A/sec。 值得注意的是，通常用以触刻SiON之反應氣體對於siN 也具有一定的I虫刻能力，例如以氧氣、三氟曱燒、與氣氣 作為反應氣體之乾蝕刻製程對SiN之蝕刻速率即為35 A/sec。因此可能造成第一底層306在乾蝕刻製裎35〇中亦 被消耗，甚至露出第一底層306下方之銅導線。然而，由 於保護層322係填充於金屬内連線圖案320之内，而乾名虫 13 200921844 • 刻製程350之反應氣體對於保護層如光阻之蝕刻速率極 _ 低，因此保護層322之設置係可阻絕第一底層306接觸乾 蝕刻製程350之反應氣體，故可保護第一底層306免於被 蝕刻，同時保護其下方的銅導線。另外值得注意的是，由 於保護層322係被回蝕刻至低於金屬内連線圖案320之開 口，也就是說，第一覆蓋層310上不會殘留任何保護層 322,因此乾蝕刻製程350係可完全地移除第一覆蓋層310。 請參閱第13圖與第14圖。待第一覆蓋層310移除後， 隨即係進行另一乾蝕刻製程360，以移除第一介電層306。 而在保護層322移除後，係可如第14圖所示，於第一底層 306上依序重新形成一第二介電層330與一第二覆蓋層 334，以預備重新形成金屬内連線圖案。第二介電層330與 第一介電層308相同，係可包含有FSG，且第一介電層308 與第二介電層330皆係用以作為金屬層間介電層。而第二 覆蓋層334則可與第一覆蓋層310相同包含有SiON。 乾蝕刻製程360對第一介電層308與第一底層306係具 有一高蝕刻選擇比，如對構成第一介電層308之FSG之蝕 刻速率為65 A/sec ;而對構成第一底層306之SiN之蝕刻 速率為4 A/sec。舉例來說，乾蝕刻製程360係可利用氧氣 與氟碳化合物，如八氟環戊稀（octafluorocyclopentene， ' C5F8)，作為反應氣體，其較佳之比例可為2:3，然不限於此。 14 200921844 另外，如第15圖所示，在用以移除第一介電層308的 乾蝕刻製程360後，亦可藉由一 CMP製程移除第一底層 306。由於乾蝕刻製程360對第一介電層308與第一底層 306具有一高蝕刻比，因此即使第一底層306在乾蝕刻製 程360中有所耗損，也不會過於影響其表面均勻度，故可 利用CMP製程將其移除。請參閱第16圖，待所有未通過 AEI之膜層皆移除後，即可於基底302上依序重新形成一 第二底層332、一第二介電層330、與一第二覆蓋層334。 而第二底層332係可與第一底層306相同，包含有SiN。 而此完成重工之積體電路元件300即可重新預備進行金屬 内連線圖案之製作。 根據本發明所提供之第三較佳實施例，當金屬内連線圖 案320未通過蝕刻後檢測(AEI)，例如微粒之遮罩（masking) 效應導致金屬内連線圖案320蝕刻不完全時，即可利用本 發明所提供之重工方法即時進行積體電路元件300上膜層 之重工，減低積體電路元件300報廢的情形。 縱上所述，本發明所提供之重工方法，係可在積體電路 元件上之膜層，如底層、介電層、或覆蓋層未通過測試時， 或因其他因素造成膜層的刮損時，即時進行重工，快速而 有效的移除該等必須重新製作的膜層。而當積體電路元件 上的金屬内連線圖案未通過蝕刻後測試，或遭受因其他因 15 200921844 素造成金屬内連線圖案的 之方法立時進行重1亦可根據本發明所提供 作的卵& β ㈣而有效的移㈣等必須重新製 作的Μ層，故可減少 因報廢所4、 ㈣料讀報廢的情形，避免晶片 ^成之損失’同時降低生產成本。 實施例，凡依本發明申請專 皆應屬本發明之涵蓋範圍。 以上所述僅為本發明之較佳 利範圍所做之均等變化與修飾， 【圖式簡單說明】 第1圖係為—f知金屬内連線結構之剖面示意圖。 第2圖至第6圖係本發明所提供之積體電路重工方法之第 一較佳實施例之示意圖。 第7圖至第10圖係為本發明所提供之積體電路重工方法之 第一較佳實施例之示意圖。 第Π圖至第16圖係本發明所提供之積體電路重工方法之 第二較佳實施例之示意圖。 【主要元件符號說明】 100 基底 104 阻障層 10卜110底層 114 覆蓋層 200 積體電路元件 102 介電層 106 金屬層 112 介電層 116 金屬内連線圖案 202 基底 16 金屬内連線層 206 第一底層 第一介電層 210 第一覆蓋層 第二介電層 222 第二底層 第二覆蓋層 250、 260乾蝕刻製程 積體電路元件 302 基底 金屬内連線層 306 第一底層 第一介電層 310 第一覆蓋層 金屬内連線圖案 322 保護層 第二介電層 332 第二底層 第二覆蓋層 350、360乾蝕刻製程 17200921844 IX. Description of the Invention: [Technical Field] The present invention relates to a method for reworking a composite circuit component, and more particularly to a method for removing a metal-layer defect in an integrated circuit component. [Prior Art] The manufacturing of integrated circuit components is extremely complicated, and it usually takes hundreds of different process steps to complete n. In this (4) the financial situation cannot meet the process requirements, that is, the rework of integrated circuit components is required. . Please refer to the figure of Fig. i for the section of the conventional metal interconnect structure. In recent years, in order to meet the high integration and high-level human body requirements of the integrated circuit components, the long circuit elemental junction tends to form a multi-layer metal (four) wire structure to increase the connection of the (four) wire to the component or the wire. In the metal interconnect process, a bottom layer 101 and a dielectric layer 102 are sequentially formed on the substrate (10), and a trench is formed therein by using lithography, rhyme, etc. to define a desired metal. Inner wiring pattern. A barrier layer 104 and a metal layer 1〇6 are sequentially formed in the trench to form a desired metal interconnect pattern. Then as the first! The figure is shown by: redundancy - underlying U0, a dielectric layer 112 and - cover layer 2, hard mask layer (not shown), and lithography, etching, etc. A metal interconnect pattern 116 is required underneath to prepare the next 200921844 metal interconnect layer. Please continue to see Figure 1. However, in the foregoing steps, for example, in the deposition process, or in the I-etch process, if the particle contamination occurs, or the metal interconnection pattern 116 is incompletely etched due to the masking effect of the particles, or the crystal is caused by external factors. Defects such as scratches on the round surface make it impossible to perform the next process step when the wafer is unable to perform the next process step. Failure to do so will result in a reduction in the yield of completed integrated circuit components; serious defects may even result in wafers being scrapped. SUMMARY OF THE INVENTION One of the objects of this invention is to provide a rework process for removing defects of integrated circuit components such as metal interconnect film layers, which has reduced the cost loss caused by the scrapping of integrated circuit components. According to the scope of the patent application provided by the present invention, a method of reworking a plurality of integrated circuits is provided. The method of re-comprising includes providing a substrate including a first underlayer and a first-dielectric layer, followed by a -d-etching process to remove the first dielectric layer; performing a chemical polishing (CMP) process. Finally, a second underlayer and a second dielectric layer are sequentially formed on the substrate. " In accordance with the scope of the application paste of the present invention, a method of reworking the integrated circuit component 200921844 is further provided. The method of reworking includes providing a substrate including a first layer, a first dielectric layer, and a first cladding layer, and the first cladding layer and the first dielectric layer are formed at least A metal interconnect pattern. After the first step, a first dry etching process and a second dry etching process are sequentially performed to remove the first covering layer and the first dielectric layer, respectively. After the first cover layer and the first dielectric layer are removed, a CMP process is performed, and the first bottom layer of the first layer is removed. Finally, a second underlayer, a _th dielectric layer and a second overlayer are sequentially formed. According to the rework method provided by the present invention, when a defect is detected in the film of the metal interconnect, or the metal When the formation of the interconnect pattern is not up to standard, the film layer must be re-formed quickly and efficiently. Therefore, the scrapping of the integrated circuit component can be reduced, the loss of the wafer due to scrapping can be avoided, and the production cost can be reduced. Please refer to FIG. 2 to FIG. 6 'FIG. 2 to FIG. 6 are schematic diagrams showing a first preferred embodiment of the integrated circuit rework method provided by the present invention. As shown in FIG. 2, firstly, a product is provided. The body circuit component 2 includes a substrate 202. The substrate 202 may include at least one metal interconnection layer 204. The substrate 202 includes a first bottom layer 206 and a first dielectric layer 208. The first underlayer 206 may include silicium nitride (hereinafter referred to as SiN); and the first dielectric layer 208 may include 200921844 fluoride silicon glass (hereinafter abbreviated as FSG). Referring to Figures 2 and 3, the integrated circuit component 200 is subjected to deposition and is not subjected to the detection, i.e., dry etching is performed to remove the first dielectric layer 208. It is noted that the dry etch 250 has a high selectivity ratio for the first dielectric layer 208 and the first bottom layer 206. For example, the dry etch process 250 can utilize oxygen and gas stone compounds, such as The octafluorocyclopentene (C5Fs) as a reactive gas may preferably have a ratio of 2:3, but is not limited thereto. The dry etching process 250 of the above reactive gas constitutes the first dielectric layer 2〇8 < FSG The scribe rate is about 65 angstroms per second (A/sec); the rate of SiN constituting the first bottom layer 206 is about 4 A/sec. See Figure 4. Waiting for the first dielectric layer After the 208 is removed, a second dielectric layer 220 may be formed on the first underlayer 206 as shown in FIG. 4. The second dielectric layer 220 is the same as the first dielectric layer 208, and may include FSg. And the first dielectric layer 208 and the second dielectric layer 220 are used as an inter-metal dielectric layer (IMD). Next, please refer to FIG. 3 and FIG. 5. After the dry etching process 250 is used to remove the first dielectric layer 208, a chemical mechanical polish (hereinafter referred to as CMP) may also be used. The process removes the first underlayer 206. Since the dry etch process 250 has a high etch ratio to the first dielectric layer 208 and the first 200921844 bottom layer 206, even if the first etch process 250 is worn out, it does not affect too much ( Uniformity) 'So you can use the CMP process to move the map. When all of the film bottom layer 206 which has not been detected after deposition is dry etched its surface uniformity, please refer to the 6th bottom 202 to re-form a second bottom layer 222, after the white removal, the same as the base first bottom layer 206, The second dielectric layer 220 is formed by including SiN. 'The bottom layer 222 can be connected to the second bottom layer 222. Please refer to Fig. 7 to Fig. 10, and Fig. 7 to Fig. 3/筮芝丨〇丨〇 diagram is the integrated circuit method provided by the present invention. A schematic diagram of the second preferred embodiment. As shown in Fig. 7, first, an integrated circuit component 2 is provided which includes a substrate 202, and the substrate 202 may include at least one metal interconnect layer 204. The substrate 202 includes a first underlayer 2〇6, a first dielectric layer 208, and a first cap layer 21〇. The first underlayer 2 〇 6 may include SiN ’. The first dielectric layer 208 may include fsG, and the first cladding layer 210 may include bismuth oxynitride (Sincon® XynitHde, hereinafter referred to as SiON). Please refer to Figures 7 to 8. When the integrated circuit component 2 is detected after deposition and does not pass the detection, a dry button engraving process 260 is performed to remove the first cap layer 210. After the first cap layer 21 is removed, the first dielectric layer 2〇8 is removed using another dry etch process 250. It is noted that the dry etch process 250 has a high etching selectivity ratio of the first dielectric layer 208 to the first bottom layer 206 of 200921844, such as an etch rate of 65 A/sec for the FSG constituting the first dielectric layer 208; The etching rate for the SiN constituting the first underlayer 206 was 4 A/sec. For example, the dry etching process 250 may utilize oxygen and a fluorocarbon such as octafluorocyclopentene (C5F8) as a reactive gas, and the preferred ratio may be 2:3, but is not limited thereto. The etching rate of the FSG constituting the first dielectric layer 208 by the dry etching process of the above reactive gas is about 65 angstroms per second (A/sec); and the etching rate of the SiN constituting the first underlayer 206 is It is about 4 A/sec. Please refer to Figure 9. After the first cap layer 210 and the first dielectric layer 208 are removed, a second dielectric layer 220 and a second cap layer 224 are sequentially formed on the first underlayer 206 as shown in FIG. The second dielectric layer 220 is the same as the first dielectric layer 208, and may include an FSG, and the first dielectric layer 208 and the second dielectric layer 220 are used as a metal interlayer dielectric layer. The second cover layer 224 may include SiON as the first cover layer 210. In addition, after the dry etching process 250 for removing the first dielectric layer 208, the first underlayer 206 can also be removed by a CMP process, and the result of the CMP process is as shown in FIG. 5 above. Since the dry etching process 250 has a high surpass ratio to the first dielectric layer 208 and the first underlayer 206, even if the first underlayer 206 is worn out in the dry etching process 250, the surface uniformity is not excessively affected. Therefore, it can be removed by a CMP process. Referring to FIG. 10, after all the layers that have not been detected by the deposition are removed, a second bottom layer 222, a second dielectric layer 220, and a first layer are sequentially formed on the substrate 202 by 11 200921844. Two cover layers 224. The second bottom layer 222 can be identical to the first bottom layer 206. According to the first and second preferred embodiments of the present invention, the film layer formed on the integrated circuit component 200, such as the first underlayer a%, the first dielectric layer 208, and the first cap layer 21 When the film is scratched by the post-deposition test or due to other factors, the rework method of the integrated circuit component 2 can be performed by using the rework method provided by the present invention. 2GG scrap situation, but also reduce the loss caused by wafer scrap. Next, reference is made to Figs. 11 to 16 which are schematic views of a third preferred embodiment of the integrated circuit resurfacing method of the present invention. As shown in Fig. 11, first, an integrated circuit component 3 is provided which includes a substrate 302 which may include at least one metal interconnect layer 304. The substrate 302 includes a first underlayer 3〇6, a first dielectric layer 3〇8 as a metal interlayer dielectric layer, and a first cap layer 31〇. As previously mentioned, the first underlayer 3 〇 6 may comprise SiN, the first dielectric layer 308 may comprise FSG, and the first cladding layer 31G may comprise si 〇 N. In addition, there is a metal interconnect pattern 32〇 formed by the lithography or etching process in the first cover layer 310 and the first dielectric layer, and the first bottom layer 3〇6 is as shown in FIG. It is exposed to the bottom of the metal interconnect pattern 32〇. 12 200921844 Please refer to Figure 12. The method of rework provided by the present invention can be carried out if the integrated circuit component 300 does not pass an after-etching-inspection (AEI). First, a protective layer 322 is formed on the first cap layer 310. The material of the cap layer 322 may be a photoresist and formed on the first cap layer 310 by a spin on coating process. An etching process is then performed to etch back the protective layer 322 to an opening lower than the metal interconnect pattern 320. Please refer to Figure 13. Next, a dry etching process 35 is performed to remove the first cap layer 310. The dry etching process 350 has a high etching selectivity ratio for the first cladding layer 31 and the protective layer 322. For example, the dry etching process 350 can utilize oxygen, fluoroform (CH3F), and gas. As the reaction gas, a preferred ratio thereof may be 1:12:24, but is not limited thereto. The dry etching process 350 containing the above reactive gas has a etch rate of 45 A/sec for the SiON constituting the first cap layer 310 and 0 A/sec for the photoresist constituting the protective reed 322. It is worth noting that the reaction gas used to etch SiON also has a certain ability to insulate SiN, for example, the etching rate of SiN by dry etching process using oxygen, trifluoroantimony, and gas as a reactive gas. It is 35 A/sec. Therefore, it is possible that the first underlayer 306 is also consumed in the dry etching process, and even the copper wires under the first underlayer 306 are exposed. However, since the protective layer 322 is filled in the metal interconnect pattern 320, the etching reaction rate of the reactive gas of the etching process such as the photoresist is extremely low, so the setting of the protective layer 322 is set. The first underlayer 306 can be prevented from contacting the reactive gas of the dry etching process 350, so that the first underlayer 306 can be protected from being etched while protecting the copper wires underneath. It is also worth noting that since the protective layer 322 is etched back to the opening lower than the metal interconnect pattern 320, that is, no protective layer 322 remains on the first cap layer 310, the dry etching process is 350 The first cover layer 310 can be completely removed. Please refer to Figure 13 and Figure 14. After the first cap layer 310 is removed, another dry etch process 360 is performed to remove the first dielectric layer 306. After the protective layer 322 is removed, a second dielectric layer 330 and a second cladding layer 334 are sequentially formed on the first bottom layer 306 as shown in FIG. 14 to prepare for re-forming the metal interconnect. Line pattern. The second dielectric layer 330 is the same as the first dielectric layer 308, and may include an FSG, and the first dielectric layer 308 and the second dielectric layer 330 are both used as a metal interlayer dielectric layer. The second cover layer 334 may include SiON as the first cover layer 310. The dry etch process 360 has a high etch selectivity ratio for the first dielectric layer 308 and the first bottom layer 306, such as an etch rate of 65 A/sec for the FSG constituting the first dielectric layer 308; The etch rate of SiN of 306 is 4 A/sec. For example, the dry etching process 360 can utilize oxygen and a fluorocarbon such as octafluorocyclopentene ('C5F8) as a reactive gas, and a preferred ratio thereof can be 2:3, but is not limited thereto. 14 200921844 In addition, as shown in FIG. 15, after the dry etching process 360 for removing the first dielectric layer 308, the first bottom layer 306 can also be removed by a CMP process. Since the dry etching process 360 has a high etching ratio to the first dielectric layer 308 and the first bottom layer 306, even if the first bottom layer 306 is worn out in the dry etching process 360, the surface uniformity is not excessively affected. It can be removed using a CMP process. Referring to FIG. 16 , after all the layers that have not passed through the AEI are removed, a second bottom layer 332 , a second dielectric layer 330 , and a second cover layer 334 may be sequentially formed on the substrate 302 . . The second bottom layer 332 can be the same as the first bottom layer 306 and includes SiN. On the other hand, the integrated circuit component 300 of the rework can be re-prepared for the production of the metal interconnection pattern. According to the third preferred embodiment of the present invention, when the metal interconnect pattern 320 does not pass the post-etch detection (AEI), for example, the masking effect of the particles causes the metal interconnect pattern 320 to be incompletely etched. The rework method of the integrated circuit component 300 can be performed in real time by the rework method provided by the present invention, and the situation in which the integrated circuit component 300 is scrapped can be reduced. In the longitudinal direction, the rework method provided by the present invention can cause the film layer to be scratched when the film layer on the integrated circuit component, such as the bottom layer, the dielectric layer, or the cover layer fails the test, or due to other factors. In time, rework is performed immediately, and the layers that must be reworked are quickly and efficiently removed. When the metal interconnection pattern on the integrated circuit component is not tested by etching, or subjected to a method of causing a metal interconnection pattern due to 15 200921844, the egg may be provided according to the present invention. & β (4) and effective shift (4), etc., which must be re-created, so it can reduce the situation of scrapping 4, (4) scrapping and avoiding the loss of wafers while reducing production costs. The embodiments are intended to be within the scope of the present invention. The above description is only for the uniform variation and modification of the preferred range of the present invention. [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view showing the structure of the metal interconnect. 2 to 6 are views showing a first preferred embodiment of the integrated circuit rework method provided by the present invention. 7 to 10 are schematic views showing a first preferred embodiment of the integrated circuit rework method provided by the present invention. Figures 16 through 16 are schematic views of a second preferred embodiment of the integrated circuit rework method provided by the present invention. [Main component symbol description] 100 substrate 104 barrier layer 10 110 underlayer 114 overlay layer 200 integrated circuit component 102 dielectric layer 106 metal layer 112 dielectric layer 116 metal interconnect pattern 202 substrate 16 metal interconnect layer 206 First underlayer first dielectric layer 210 first overlayer second dielectric layer 222 second underlayer second cap layer 250, 260 dry etch process integrated circuit component 302 base metal interconnect layer 306 first bottom layer first Electrical layer 310 first cover metal interconnect pattern 322 protective layer second dielectric layer 332 second bottom layer second cover layer 350, 360 dry etching process 17