TWI362755B - Manufacturing method of thin film transistor - Google Patents

Description

1362755 0710057ITW 23954twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing an active device, and more particularly to a method of manufacturing a thin film transistor. [Prior Art] With the rapid development of technology and the maturity of technology, liquid crystal displays (LCDs) have been widely used in everyday life, and Thin Film Transistors (TFTs) are applications. Drive components in liquid crystal displays. The channel material of the transistor is divided into two types: an amorphous silicon (a-Si) and a poly-silicon (p-Si). In general, amorphous germanium thin germanium transistors have lower leakage current, but their electron mobility is lower, which does not exceed 1 cm2/Vsec, which is not suitable for current high-speed component applications. demand. However, polycrystalline germanium thin film transistors have higher electron mobility (about 2 to 3 orders of magnitude higher than amorphous germanium) than amorphous amorphous thin films, but have higher leakage currents. Cannot be applied to LCD monitors with large sizes. Therefore, in order to effectively improve the leakage current of the polycrystalline germanium film transistor, it is generally convenient to reduce the leakage current by the structure of the shallow doped drain on both sides of the gate of the thin film transistor. 1A to 1D are schematic views showing a conventional method of fabricating a thin film transistor. Referring to FIG. 1A, the conventional method for fabricating a thin film transistor includes the steps of forming a poly-silicon island 120 on a substrate 11A. Referring to FIG. 1B, a patterned photoresist layer 125 is formed, and then an ion implantation process S11 is performed as a mask in FIG. 5 1362755 0710057ITW 23954twf.doc/p. A source/drain 121 is formed in the polysilicon island 120 below the two sides of the patterned photoresist layer 125. Then, the patterned photoresist layer 125 is removed. Referring to FIG. 1C, a gate insulating layer 130 is formed on the substrate 110 and covers the polysilicon island 120; then a gate 140 is formed on the substrate 110. Then, using the gate 140 as a mask, a shallow doping ion implant is performed.

A lightly doped drain ion implantation process S120 is formed in the polycrystalline germanium island 12 below the two sides of the gate 140 to form a shallow doped non-polar region 123' and a polycrystal directly under the gate layer 140. Shixia Island 120 is a passage area 127.

Referring to FIG. 1D, a patterned dielectric layer 150' is formed on the substrate 11'', and a portion of the gate insulating layer 130 is removed to expose a portion of the source electrode 121. Then, a patterned conductor layer 160' is formed on the patterned dielectric layer 15A and the patterned conductor layer 16 is electrically connected to the source/non-polar. Thus, the process of the conventional thin film transistor is substantially completed. In the polar region, the photoresist layer 125 and the gate 140 must be separately formed for the ionic implant mask for the nucleation electrode 121 and the shallow doping method. In other words, the ray mask is the best in the world. Therefore, in order to reduce the manufacturing number I of the crystals of the second embodiment, a conventional schematic diagram of the conventional method of forming the thin film patterns 2A to 2E has been developed. ^Test, = another method of conventional thin film transistor 2A, the conventional method of making a thin film transistor includes the following steps. On the substrate, 21G is sequentially formed - a polycrystalline stone island 220, a gate insulating layer 230 and a gate layer 240a. Next, a patterned photoresist layer 250 is formed over the gate layer 240a, wherein the patterned photoresist layer 250 has a photoresist layer structure applied to the base photoresist layer structure 2' and the gate photoresist layer structure 25 For example, it is connected to the base photoresist layer structure. Please refer to ® 2B for the ion implantation process S21〇, and (4) Form the gate/source 221 in the polycrystalline stone island 22 below the two sides of the interrogation layer 240a. Please refer to FIG. 2C' to strip a portion of the thickness of the base photoresist layer structure 25〇b by electro-agglomeration or other anisotropic button to expose part of the gate and 曰jOa and then 'remove part of the gate layer 24〇a to form the gate 240b. Please refer to ® 2D for the shallow doping ion implantation process sno to form the shallow doping poles in the polycrystalline stone island 22 below the two sides of the gate layer 240b and on the gate layer 24〇b The polycrystalline island 220 directly underneath is a channel region 127. Then, the remaining base photoresist layer structure 250b is removed. The kiss is formed on the substrate 21G with reference to Fig. 2E', respectively, to form a patterned dielectric layer 260 except for a portion of the gate insulating layer 23() to expose a portion of the source/drain 221. Then, a patterned conductor layer is formed on the patterned dielectric layer 26, and the pattern = conductor layer 270 is connected to the source/drain 221. Value: It is noted that although this manufacturing method can reduce the need for a plasma ashing or other materializing side process to remove the damaged patterned photoresist layer MG (ie, the base photoresist layer structure (4), And increase 7 1362755 0710057ITW 23954twf.doc/p, the procedure for the overall manufacturing is not reduced. [Section σ gate etching secondary etching] [Invention content] There is Rong, the invention is connected to reduce the number of (four) fresh A method for fabricating a ferroelectric crystal, a method for fabricating a thin film transistor, wherein the step package === into a polycrystalline stone island. Then, a closed insulating layer if! ' is formed in sequence and covers the polycrystalline $island. After that, the shape is formed by patterning the photoresist layer for the conductor layer to form a gate, _ = the width of the photoresist layer. Then, proceeding; implant process 2 Formed in the polycrystalline stone island below the two sides of the layer - source / no pattern: light 2 = two, then shift =: [the formation of shallow doping in the polycrystalline plume ==== After ??:, the dielectric layer is formed to expose part of the source/drain, and the gate is insulated. _, job = pattern = wave : /, on the patterned dielectric layer, , , the middle source / the secret conductor layer is divided into the source / 3⁄4 pole electrical connection. = The embodiment of the present invention, the source of the ion ion implant iHr Doping concentration can be between 5Ei4 and coffee

In accordance with an embodiment of the present invention, the doping concentration of the implanted ions may be between 1E13 and S 8 1362755 0710057ITW 23954twf.doc/p ions/cm2. According to an embodiment of the present invention, the buffer layer may be formed on the substrate before the formation of the polycrystalline island. According to an embodiment of the invention, the edge of the patterned photoresist layer and the edge of the gate may be 1.5 to 2 microns apart. According to an embodiment of the invention, the material of the gate may include copper (Cu), aluminum (A1), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), giant (Ta). • Shixi Huahe (WSi2), Shixihua Titanium (Tisi2), Shixihua Formation (TaSi2), Shixi Huadu (Mosi2) or cobalt telluride (CoSi2). Based on the above, the present invention utilizes a method of making a pattern so that the patterned photoresist layer required to form the gate is larger than the gate electrode, and the ion implantation process is performed by patterning the photoresist layer and the gate mask, respectively. In order to form the source/drain and the shallow doped drain region, the number of process masks of the thin film transistor can be reduced, and the process cost and time can be reduced. The above, as well as the objects, features and advantages of the present invention will become more apparent and understood. [Embodiment] Figs. 3A to 3F are views showing a method of fabricating a thin film transistor according to an embodiment of the present invention. Referring to FIG. 3a, the thin film transistor of the present embodiment = manufacturing method includes the following steps. First, a multi-stone island 320 is formed on the substrate 31. In more detail, the step of forming the polycrystalline stone island 32 例如 is, for example, first forming an amorphous germanium layer (not shown) on the substrate 310, and forming an amorphous germanium layer by, for example, chemical vapor deposition. (chemical 9 1362755 0710057ITW 23954twf.doc / p vapor deposition, CVD) process or plasma enhanced chemical vapor deposition (PECVD) process. Next, a laser annealing process is performed on the non-Crystal layer to convert the amorphous layer into a polycrystalline layer. Then, a photolithography process and an etching process are performed on the polysilicon layer to form polycrystalline islands 320 on the substrate 310. In addition, before the formation of the polycrystalline islands 320, a buffer layer 311' may be formed on the substrate to reduce diffusion of metal ions in the substrate 310 into the polycrystalline islands 320. The buffer layer 311 may be formed by a low pressure CVD (LPCVD) process or a PECVD process. In more detail, the buffer layer 311 is, for example, a single layer of cerium oxide or a double layer structure of cerium oxide/cerium nitride. Referring to FIG. 3B, a gate insulating layer 33 is formed on the substrate and covers the polysilicon island 320. In more detail, the gate insulating layer 33 is formed by a PECVD process. Next, a conductor layer 340 is formed on the gate insulating layer 33 on the substrate. In more detail, the conductor layer 340 may be formed by first forming a gate material layer on the gate insulating layer 330 by a physical vapor deposition process or a sputtering process, and the gate material is formed. The material of the layer may be copper (Cu), aluminum (A1), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), button (Ta), Shi Xihua crane (wsiz), titanium telluride (Tisy, 矽化钮(丁丁匕), bismuth molybdenum (M〇Si2) or cobalt bismuth (CoSb). Then, a patterned photoresist layer 410 is formed on the conductor layer 34. Please refer to Figure 3C, by wet The etching is performed by etching to form the idle electrode 341' in the shape of 1362755 07100571TW 23954twf.doc/p and to make the width of the gate 341 smaller than the width of the patterned photoresist layer 41. In more detail, the patterned photoresist layer 41 is patterned. The edge of the crucible and the edge of the gate 341 may be between 1.5 and 2 microns apart, as shown in Figure 3C.

Please refer to FIG. 3D 'Ion implantation S310 process with the patterned photoresist layer 41 as a mask' to form a source/no in the polycrystalline stone island 320 below the two sides of the patterned photoresist layer. Extreme 321. In more detail, the ions implanted in the ion implantation process S310 may be n-type dopants, wherein η, the dopant may be hetero, and the doping concentration of the implanted ions may be 疋; 丨 at 5Ε14 Between 1Ε16 i〇ns/cm2. Please refer to ® 3E 'Removal of patterned photoresist layer 41〇, shallow doping ion implantation process S32〇 with questioner 341 as mask, and polycrystalline stone island 320 below both sides of interpole 341 The shallow doped non-polar region 323 is formed therein, and the gate, 341 fp square polycrystalline stone island 32 is the one-channel milk. More precisely, the ions implanted in the shallow doping ion implantation process (4) can

== Acoustics wherein the n-type dopant may be a phosphorus ion, and the implanted ions = the impurity trace may be between the old 3 to 1E14iGnsW. In order to dissipate the second impurity, since the source/track is formed by patterning the photoresist layer 410 edge disk θ, the edge of the source/dot electrode 321 is aligned. In addition, the shallow doped region 323 is formed by a shallow implant ion implantation process for the mask, because the edge of the doping region 323 is aligned with the edge of the gate 341. "Monthly with reference to Fig. 3F, the gate insulating layer 33〇 is shaped by one-eighth 350' and then is part of the dielectric layer gauge and the ship's ^ part of the source (4). In more detail, the method of removing a portion of dielectric = 1362755 0710057ITW 23954twf.doc/p gate insulating layer 330 includes forming a source/drain conductor layer 36 on the lithography process and etching/dielectric layer 350. The layer 360 is electrically connected to the source/drain 321 . /', pole/' and pole conductors In addition, the ion crystal design requirements for doping in the ion implantation process can be!! Type or p-type dopant or P-channel metal oxide semiconductor.

Advantages of the above-mentioned materials 'this correction thin _ crystal manufacturing method includes the following use of the secret engraving method, so that the layer of the gate layer _, the age of the «Sister layer and the gate area 3 (four) sub-planting process, (10) into the source level Compared with the prior art, the fabrication of the thin film transistor of the present invention, as well as a photomask, can reduce the number of process masks of the thin film transistor.

According to the actual thin film electricity to form the η channel, compared with the f-knowledge technology, it is possible to produce a symmetrical shallow doped polar region by using the (four) bit error. The patterned photoresist of the _ layer is used as a mask and _ metal wet. The side of the side has the advantage of uniform isotropic, = polycrystalline islands for ion implantation process, so the shallow doped bungee areas on both sides of the channel area are more symmetrical. Second, compared to the conventional technology, after the source/drain formation is formed, 'the pattern=resistance is ashed or other anisotropy is part of the glory and I need to remove the part again. After the doping layer, the shallow ion ft is changed to form a shallow doping impurity region. In the invention, the pattern of the gate layer is used as a mask, and the shallow impurity ion implantation (4) money doping is performed 12 1362755 0710057ITW 23954tw£doc/p area. Therefore, the manufacturing method of the thin film transistor of the present invention requires less processing procedures than the prior art. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some modifications and changes within the spirit and scope of the present invention. The protection of the present invention is attached to the application of the application

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 2A to Fig. 2E are diagrams showing another method of manufacturing a thin film transistor which is conventionally shown. The manufacturing method of the conventional thin film transistor is the thin one in the embodiment of the present invention. [Description of main component symbols] 110, 210, 310: substrate

120, 220, 320: polycrystalline stone islands 121, 221, 321 . source /; and poles 123, 223, 323: shallow doped germanium and polar regions 125, 250, 410: patterned photoresist layer 127 325: channel region 130, 230, 330: gate insulating layer 140, 240b, 341: gate 150, 260, 350: dielectric layer 13 1362755 0710057ITW 23954twf.doc / p 160, 270, 360: source / bungee Conductor layer S110, S210, S310: ion implantation process S120, S220, S320: shallow doping ion implantation process 240a: gate layer 250a: top photoresist layer structure 250b: base photoresist layer structure 311: buffer layer 340: Conductor layer 14

Claims (1)

Patent application scope: A method for manufacturing a thin film transistor, comprising: forming a polycrystalline germanium island on a substrate; forming an idle insulating layer on the substrate, and covering the polycrystalline stone island formation-conductor layer On the gate insulating layer; = forming a patterned photoresist layer on the conductor layer; by the patterned photoresist layer for forming a gate, wherein the gate is wider than the layer Width; the visibility is smaller than the patterned photoresist, and the patterned photoresist layer is used as a mask to perform the multi-in-line process under the two sides of the patterned photoresist layer. The polycrystalline; the inner formation-source removes the patterned photoresist layer; the stomach is a channel region; the gate is a two-wing rotor implanting process, for the region, wherein the shallow doping, and Forming a shallow-doped drain between the shallow and the doped regions; forming a dielectric layer on the gate insulating layer to remove a portion of the dielectric layer from the gate layer and the _(four); pole/drain And form - the slain s violent road out part of the source and (four) chemical " electric layer and a pattern between The method of manufacturing the film transistor according to the first item of the patent range 1362755 0710057ITW 23954twf.doc/p, which is based on the source ^2=:= layer, wherein the son of Nazi Zhiren The doping concentration of the heterosome is between 5E14 and 1E16 i〇ns/cm2. 3. The method of fabricating a thin film transistor according to the above item, wherein the doping concentration of the ion implanted in the shallow doping ion implantation process is between 1E13 and 1E14 ions/cm2. 4. The manufacturer of the thin film transistor according to claim 1 of the patent application scope The method of forming a buffer layer on the substrate before the process is performed on the island sand island. 5. The method of fabricating a thin film transistor according to claim 1, wherein the edge of the patterned photoresist layer is 1.5 to 2 micrometers from the edge of the gate. The method for manufacturing a thin film transistor according to the first aspect of the invention, wherein the material of the gate comprises copper, sho, crane, chrome, indium, chin, la, shixihua crane, shredded mash, shattered Group, ^Mb molybdenum or;