TWI360213B - Chip package carrier, chip package and method for - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a circuit board, and more particularly to a chip package carrier, a chip package, and a method of fabricating the same. [Prior Art] Today's semiconductor technology is developed, and many chips have a large-scale, two-degree arrangement of transistor elements and a plurality of pads disposed on the surface of the wafer. In order to be able to package these wafers, these wafers are typically mounted on a chip package carrier to form a chip package, while current wafer packages are typically copper foil substrates (Copper Clad Laminate). , CCL). 1A to 1E are schematic flowcharts showing a method of manufacturing a conventional chip package. Referring to FIG. 1A and FIG. 1B, a conventional method for manufacturing a chip package includes the following steps. First, a copper foil substrate 11 is provided which includes a dielectric core layer 112 and a layer of copper 114 disposed on opposite sides of the dielectric core layer 112, respectively. Next, the copper foil substrate 11 () is sequentially subjected to mechanical drilling, eleetroless plating, electro-difficulty, and etch process to form a copper circuit layer 114 and conductive vias τ, wherein the copper circuit layers 114疋 is composed of a plurality of traces i 1 , a plurality of wafer contacts U4b and a plurality of fresh balls 114c. Referring to FIG. 1C, after the copper wiring layer 114, two solder mask layers 120 are formed respectively, and the anti-recording layer 120 in the crucible exposes the crystal 1360213 24880twf.doc/n chip pads 114b and the solder ball pads. 114c. Next, a nickel-gold layer 30 is formed on each of the wafer pads 114b and the respective solder ball pads 114c. After the formation of the nickel gold layer 130, the conventional wafer package carrier 1a has been completed. Referring to FIG. 1D, a wafer 14 is adhered to one of the solder resist layers 120, and the wafers 140 are electrically connected to the wafer contacts I14b by wire bonding. Thereafter, a wire 150 between the wafer 140 and a plurality of wires connected to the wafer 140 and the die pads 1141 is coated with a potting resin ι6. Referring to Figure 1E, a plurality of solder balls 170 are then formed on the solder ball pads. After forming these solder balls 17 ,, a unit singulation was performed. Thus, a single chip package 1 〇〇 has been completed. Portable electronic devices such as mobile phones, personal digital assistants (PDAs), and digital cameras, which are currently used by modern people, have been oriented toward the body and miniaturized. _ Potential ^ In order to make the crystal package (10) The chip package 100 can be developed toward a thinner profile by being able to accommodate a portable electronic device that is compact in size and to enable the portable electronic device to accommodate more electronic components. To this end, various companies and companies are now developing thinner copper foil substrates 11 (). However, once the thickness of the copper foil substrate 11 is too thin, a certain plate 110 of the copper foil becomes brittle and is easily damaged by the external force. Therefore, the thickness of the plate 110 is very thin. The substrate 11G cannot be used with the existing production equipment. The current process (as shown in Figure u to Figure 1E) is manufactured to 'must be manufactured using two devices. However, the cost of this (four) special production equipment is very expensive' plus the thin _ substrate UG is very fragile and the capacity is 1360213 248S〇hvf.doc/n == rate = crack, etc. J Ming provides a wafer county carrier for mounting wafers. A semiconductor chip package has a relatively thin thickness. The method for manufacturing a chip package can reduce the number of wafers. The chip package includes a circuit substrate, the circuit substrate includes a conductive pattern, and the right one is T-^. : the radio and television layer covers these first-connected turns; two; a circuit layer extends to the guide = two = medium, the pattern layer is transmitted; the substrate. The encapsulant is disposed on the circuit substrate: board. ^, the connection line is electrically conductive, and the above-mentioned chip package further includes a plurality of the first ρ)'s, and the conductive bumps are respectively connected in the embodiment of the present invention, and the conductive pattern layers are formed by the 1360213 24880 twf.doc/ n Some of the first pads. In an embodiment of the invention, the bottom surfaces of the first pads are substantially aligned with the surface of the first dielectric layer. In an embodiment of the invention, the first circuit layer includes a plurality of second pads, and the wafer is electrically connected to the circuit substrate through the second pads. In an embodiment of the invention, the chip package further includes a plurality of bonding wires, and the wafers are connected to the second pads through the bonding wires. In an embodiment of the invention, the chip package further includes a protective layer covering the first, wiring layer and exposing the second interfaces. In one embodiment of the invention, the circuit substrate further includes a second green, a second dielectric layer, and a plurality of second conductive blind via structures. The second second dielectric layer is disposed between the second male "line layers, wherein the second dielectric layer has a plurality of second blind holes extending from the blind holes to the first circuit layer. These second conductive layers Two of the second blind holes are disposed, and the second circuit layer is connected to the first circuit layer through a conductive structure. The second circuit layer: In one embodiment, the second circuit layer includes a plurality of Too^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ a wafer-impregnated carrier board comprising: a carrier substrate; the conductive substrate is disposed on the carrier substrate, and includes a conductive via 4 structure layer, a first dielectric layer and a plurality of first structures. The layer is disposed on the bearing plate and includes a plurality of 1360213 24880 twf.doc/n first pads, wherein each of the first pads has a bottom surface of the carrier substrate. The first circuit layer is disposed above the conductive pattern layer. And between the first dielectric layer and the first circuit layer, and covering the conductive pattern layer The "carrier: board" wherein the first dielectric layer does not cover the bottom of the first interface ^ 丨 covers the surface other than the bottom surface of the first pads. One death " electricity 2 has more than a plurality of holes extending from the first-line layer to the conductive pattern layer. & some conductive-blind hole structures are placed in these first-blind holes ^ and the conductive pattern layer is connected to the first-line layer by these first-conductive blind via structures. In the present invention, the wire receiving plate comprises a "first material" and a second material layer disposed between the first material layer and the conductive pattern layer. In an embodiment of the invention, the material of the first material layer comprises a metal or a ceramic. In an embodiment of the invention, the material of the first material layer comprises copper, aluminum or aluminum copper alloy. The material of the above-mentioned material layer includes the material of the above-mentioned material layer, including the above-mentioned conductive pattern layer, which is a metal or a 13⁄4 molecular material in one embodiment of the invention. Recorded in an embodiment of the invention. In one embodiment of the invention, the first pads are comprised. θ In the present invention - the above-described chip package carrier further comprises - the anti-glaze layer H circuit layer comprises a plurality of second interfaces. Lining coverage

< S 10 1360213

In an embodiment of the invention, the circuit substrate further includes a second circuit layer, a second dielectric layer, and a plurality of second conductive blind via structures. The second circuit layer is disposed above the first circuit layer, and the second dielectric layer is disposed between the & one circuit layer and the second circuit layer, wherein the second dielectric layer has a plurality of extending from the second circuit layer to The second blind hole of the first circuit layer. The second conductive holes are respectively disposed in the m, and the (four) two circuit layers are transparent. The second conductive blind holes are connected to the first circuit layer. In an embodiment of the invention, the wafer package carrier further includes a barrier layer' and the second circuit layer includes a plurality of second slits. The solder resist layer covers the first circuit layer and exposes the second pads. A substrate and a layer of conductive material disposed on the carrier substrate. The pattern is patterned to form a layer of conductive material to form a layer of conductive patterns.

The above method for removing a carrier substrate The present invention further provides a method of manufacturing a chip package. First, in the embodiment of the present invention, the loading of the carrier substrate is performed.

For example, the carrier substrate includes a second material 1360213 24880 twf.doc/n layer between the first material layer and the conductive material layer, wherein the second material layer is made of a different material than the conductive material layer. In an embodiment of the invention, the material of the first material layer comprises metal or taman. In an embodiment of the invention, the material of the first material layer comprises copper or aluminum. In an embodiment of the invention, the material of the second material layer comprises a metal or a polymer material. In an embodiment of the invention, the material of the second material layer comprises a recording. In one embodiment of the invention, the method of removing a carrier substrate includes stripping a first material layer. In an embodiment of the invention, the above method of electrically connecting a wafer to a wiring substrate comprises wire bonding. In the method of the present invention, the method for forming a circuit substrate includes: first, forming a first dielectric layer on the carrier substrate, wherein the first dielectric layer covers the carrier substrate and the conductive pattern layer. Next, a first conductive layer is formed on the first dielectric layer. Then, a plurality of _th blind holes are formed, wherein the first-blind holes extend from the first conductive layer to the conductive pattern layer/,: the first conductive blind holes are formed in the first blind holes/the eve wall, a ^ 苜 肀. Next, a portion of the conductive layer is removed to form a first wiring layer. In an embodiment of the invention, the method of forming the first dielectric reed conductive layer comprises laminating - Coated Copper (RCC) on a carrier substrate. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In one embodiment of the known month, the method, the first dielectric layer is exposed and some of the first-blind holes are formed on the circuit layer, wherein the solder resist layer is partially covered with a solder mask, and the solder resist layer is in the present invention. - every ~ circuit layer. Including: first, a method of forming a second dielectric substrate is further formed - a second conductive layer is on the second dielectric layer. Next, the J holes 'where the second blind holes are guided from the B to form a plurality of second turns. The contacts are formed into a plurality of second conductive blinds, 9 extending to the younger-line, and then removing a portion of the second conductive layer to open; and two of the second blind holes. In one of the present inventions, a circuit layer is used. The method of conducting a conductive layer comprises forming a second dielectric layer and a second * present hair gel copper on the carrier substrate. The drilling process or the process of the process is performed by a laser method including a second dielectric hole 2: a second blind hole of the bare earth in one embodiment of the invention, on the edge layer, wherein the soldering prevention The layer is partially covered by the first package; the solder resist layer is on the second solid, and the carrier substrate of the present invention can make the circuit substrate become a nesting H ^ package substrate is not easily damaged. Therefore, the wafer of the present invention is manufactured using a production facility. Thus, the wafer-sealed chip package carrier of the present invention can be manufactured at a low cost without requiring special production equipment, and at the same time, can improve the yield. In addition, by removing the carrier substrate from the 13 5 1360213 24880 twf.doc/n circuit substrate, the present invention can produce a thinner wafer package ′ to conform to the trend of today's portable electronic devices. The above features and advantages of the present invention will become more apparent from the following description. [Embodiment] FIG. 2A is a cross-sectional view of a chip package according to an embodiment of the present invention. Referring to FIG. 2A, the chip package 200a includes a circuit substrate 3A, a wafer 210, and an encapsulant 220. The circuit substrate 300a of FIG. 2A has a two-layer circuit structure. In detail, the circuit substrate 300a includes a conductive pattern layer 31, a first circuit layer 320a, a first dielectric layer 330, and a plurality of first conductive via structures 340a. The conductive pattern layer 31 includes a plurality of first pads 312, and each of the first pads 312 has a bottom surface B. In this embodiment, the conductive pattern layer 310 may include only the first pads 312. That is, these g conductive pattern layers 310 are composed of these first pads 312. The first circuit layer 320a is disposed above the conductive pattern layer 310, and the first dielectric layer 330 is disposed between the conductive pattern layer 31 and the first circuit layer 32A &amp; The first dielectric layer 330 has a plurality of first blind vias 332 extending from the first wiring layer 32A to the patterned layer 310. In addition, the first dielectric layer 33 覆盖 covers the surface other than the bottom surface B of the first pads 312, and does not cover the bottom surfaces B. In the present embodiment, the bottom surface B of the first pads 312 is substantially aligned with the surface 334 of the first dielectric layer 330. However, these CS) 14 1360213 24880 tw doc/n pads 312 may also be out of line with the surface 334 of the first dielectric layer 330. For example, the first pads 312 may be recessed first because of their thin thickness. The surface 334 of the dielectric reed 330. The first conductive blind via structures 340a are respectively disposed in the first drain holes 332, and the conductive pattern layer 310 is connected to the first circuit layer 320a through the first conductive blind via structures 340a. These first conductive blind via structures 34 may be located above the first pads 312, i.e., the first conductive blind via structures 340a may be via in the pad structure. These first conductive blind via structures 340a can be conformally formed in these first blind vias 332, respectively (as shown in Figure 2A). Of course, these first conductive blind via structures 340a may be conductive pillars that fill the first blind vias 332. The wafer 210 is disposed on the wiring substrate 3A and electrically connected to the wiring substrate 300a. In this embodiment, the wafer 21A can be adhered to the circuit substrate 3 (10) &amp; the first circuit layer 320a includes a plurality of second pads 322 and ^ traces 324, wherein the wafer 210 is electrically transmitted through the second pads 322. The connecting plate 300a. There are many methods for electrically connecting the wiring substrate 3A to the ground wafer 210. The wafer 210 shown in Fig. 2A is electrically connected to the wiring substrate 300a by wire bonding. In detail, the chip package 2A further includes a plurality of bonding wires W, and the wafer 210 is connected to the second pads 322 through the bonding wires w, thereby electrically connecting the circuit substrates 3A. In addition to the above-described method of wire bonding, the wafer 21 is also in the form of a flip chip or other electrically connected circuit substrate. Therefore, 'emphasis here' 2A is only an example of 'not limited to the solar panel 210 and the circuit substrate 3〇〇a electrically connected to the side 22〇: tW 21〇 is _ίτ line bonding way electrical connection line 2 3 〇〇a %, the package knee 220 not only covers the wafer 21, but also covers the f = wire W'_ wafer (10) can be electrically connected to the circuit substrate 300a normally, to avoid short circuit and open circuit.

The chip package 20A may further include a plurality of conductive bumps 23A, and the conductive bumps 230 are respectively connected to the first through-cuts 312. In detail, some of the conductive bumps 230 are adhered to the bottom surface B of the first pads 312. The two conductive bumps 23A may be solder balls, and the outer shape of the conductive bumps 23 may be spherical, cylindrical, needle-like or other suitable shape. In this embodiment, the chip package 2A may further include a fresh-proof layer 350. The solder resist layer 350 covers the traces of the first wiring layer 32A; and exposes the second pads 322. As such, the anti-recording layer 350 can protect these traces 324 from damage.

It is worth noting that the upper and lower surfaces of the conventional wafer sealing body are covered by two layers of solder mask (refer to Figure 1E), and the two layers of the fresh-keeping layer respectively expose the wafer pads on the upper surface. Solder ball pad with lower surface. However, in the κ embodiment, the second pads 322 electrically connected to the wafer 21 are exposed by the solder resist layer 350, and the first pads 312 connecting the conductive bumps 23 are made by the first Dielectric layer 330 is exposed. Therefore, the first dielectric layer 330 not only provides a function of electrically insulating the conductive pattern layer 31A from the second wiring layer 320a, but also serves as an anti-existing protection for the 16 1360213 24880 twf.doc/n second brother-$pad 312. Solder layer. Further, the color of the solder resist layer 35 is usually / the color of the second-electrode layer 330 is significantly different. Therefore, the relative two surfaces of the circuit substrate can be clearly seen that the colors of the two are different. In addition, the anti-correlation layer 350 may cover the surrounding area of the top surfaces of the second pads 322, that is, the solder resist layer 35G may be of the type of SGider Mask Defined (SMD), as shown in FIG. 2A. In other embodiments not shown, the solder resist layer 350 may also be of the type defined by the non-slip layer definition (10). However, the first dielectric layer 330 covers only the bottoms of the first pads 312, and the surfaces other than B' and does not cover the bottom surfaces B. In other words, the first dielectric layer 330 is not covered by the bottom surface B of the first pads 312, and is not like a solder mask defined type of the solder mask layer, and the first dielectric layer 33 is also not completely These first pads 312 are exposed instead of a solder mask of a type defined by a non-solderproof layer. In addition, the circuit substrate 300a may further include a plurality of oxidation resistant layers 36, and the oxidation resistant layers 360 may be formed on the second pads 322. The oxidation resistant layer 360 may be a nickel gold layer or made of other oxidation resistant materials, and the anti-oxidation layer 360 functions to protect the second pads 322 from oxidation to ensure the wafer 210 and the wiring substrate 3a The quality of the electrical connection between. Figure 2B is a cross-sectional view of a chip package in accordance with another embodiment of the present invention. Referring to Fig. 2B, the wafer package body 200 of the present embodiment is similar to the chip package 200a of the foregoing embodiment, and the difference between the two is that the circuit substrate 300b of the chip package 200b has a three-layer wiring structure. The circuit substrate 300b includes a conductive pattern layer 31, a first 17 1360213 24880 twf. doc/n circuit layer 320b, a first dielectric layer 330, these first conductive blind via structures 340a, and a first pass layer 370. a second dielectric layer 380 and a plurality of second conductive blind via structures 340b. The second circuit layer 370 is disposed above the first circuit layer 320b of the circuit substrate 300b, and the second dielectric layer 380 is disposed between the first circuit layer 320b and the second circuit layer 370, wherein the second dielectric layer 380 has A plurality of second blind vias 382 extending from the second wiring layer 370 to the first wiring layer 320b. The second conductive blind via structures 340b are respectively disposed in the second blind vias 382, and the second trace layers 370 are connected to the first trace layers 320b through the second conductive via via structures 340b. The second conductive blind via structures 34 〇 b may have the same shape as the first conductive blind via structures 34 〇 a 'that the second conductive blind via structures 340 b may be conformally formed in the second blind vias 382 , respectively ( As shown in FIG. 2B), or the second conductive blind via structures 34A may be conductive pillars filling the second blind vias 382. In this embodiment, the second circuit layer 370 includes a plurality of second pads 372 and a spur line 374, and the wafer 210 is electrically connected to the circuit substrate 300b through the second interfaces 372, that is, the wafer 210 is electrically connected. The second pads 372 are electrically connected to the circuit substrate. The wafer may be electrically connected to the circuit substrate 3b by wire bonding, flip chip bonding or the like. The wafer 2 shown in Fig. 2B is electrically connected to the wiring substrate 300b' by wire bonding, but Fig. 2B is merely illustrative, and does not limit the manner in which the wafer 21A is electrically connected to the wiring substrate 3b. _Please refer to FIG. 2A and FIG. 2B at the same time, it is worth mentioning that the thickness di of the circuit substrate 3〇〇a of FIG. 8 and 8 can be less than 丨(9) micrometers, and the circuit shown in FIG. 1360213 24880 twf.doc/n The thickness D2 of the substrate 300b may be 150 microns or less. It can be seen that the chip packages 200a, 200b of the present embodiment have a very thin thickness, and thus the crystal moon packages 200a, 200b are suitable for use in today's portable electronic devices. μ In addition, 'must be explained', although the circuit substrate 3〇〇a shown in FIG. 2A and the circuit substrate 3〇〇b shown in FIG. 2B have a two-layer line structure and a three-layer line structure, respectively, In the illustrated embodiment, the circuit substrate may have a wiring structure of four or more layers. Therefore, it is particularly emphasized here that the circuit boards 3a, 3A, which are disclosed in Figs. 2A and 2B are all exemplified, and the number of layers of the line structure of the circuit board of the present embodiment is not limited. Only the structure of the chip package of the present invention will be described above, and the method of manufacturing the chip package of the present invention will not be described. In the following, the chip package 200b in the drawing will be described as an example, and the method of manufacturing the chip package of the present invention will be described in detail with reference to Figs. Therefore, it is emphasized herein that the method of fabricating the chip package disclosed in Figs. 3A to 3L below is not intended to limit the present invention. I, 3A to 3L are cross-sectional views of the method of manufacturing the wafer sealing body of Fig. 2B. Referring to FIG. 3A, in relation to the method of fabricating the chip package of the present embodiment, first, a carrier substrate 240 and a conductive material layer 31 disposed on the carrier 240 are provided. For example, the conductive material layer 310 may be made of copper, quartz, or copper, or other suitable metal, and the carrier substrate 24 may include a material layer 242 and a first material layer 242 and conductive A second material layer 244 between the material layers 1360213 24880twf.doc/n 310'. The material of the first material layer 242 may be metal or ceramic, and the material of the second material layer 244 may be metal or polymer material, wherein the material of the second material layer 244 is different from the conductive material layer 310'. The above polymer material has a viscosity, that is, the second material layer 244 made of a polymer material may be adhered between the first material layer 242 and the conductive material layer 310'. When the first material layer 242 and the second material layer 244 are both metal, the material of the first material layer 242 may be copper, aluminum or other suitable metal material, and the material of the second material layer 244 may be nickel or other different materials. The metal material of the conductive material layer 310'. Referring to FIG. 3A and FIG. 3B, the conductive material layer 310 is patterned to form a conductive pattern layer 310 ′, wherein the conductive pattern layer 310 is disposed on the carrier substrate 240, and each of the first pads 312 of the conductive pattern layer 310 is disposed. There is a bottom surface B with respect to the carrier substrate 240 as shown in FIG. 3B. In the above, the method of patterning the conductive material layer 310 may be to perform a lithography and a remnant process on the conductive material layer 310'. Since the material of the second material layer 244 is different from the conductive material layer 310', when the conductive material layer 31 is etched and etched, the process can be performed only by etching the conductive material layer 31 without damaging the second material layer 244. Chemicals. Thus, the second material layer 244 can serve as an etching st〇p layer that etches the conductive material layer 310'. Next, a wiring substrate 300b (refer to Fig. 3H) is formed on the carrier substrate 240, wherein the wiring substrate 3b includes a conductive pattern layer. The circuit board 300b will be described in detail below with reference to Figs. 3C to 3H.

20 1360213 24880twf.doc/n It must be noted that although the circuit substrate has a three-layer circuit structure, it is a wafer package of other embodiments not shown. (4) The manufacturing method can also be used to manufacture two layers (such as Fig. 2A shows a circuit board 3A), a four-layer or four-layer or more of any layer of the secret structure of the substrate. Referring to FIG. 3C, regarding the formation of the circuit substrate 3, first, the first dielectric layer 330 is formed on the carrier substrate 24, and the first tortoise layer 330 covers the carrier substrate 240 and is electrically conductive. The pattern layer 31 is. The first dielectric layer 330 may be formed of a resin, a prepreg or an insulating material thereof, so that the first dielectric layer 33 can cover the first pads 312. Next, a first conductive layer 32b is formed on the first dielectric layer 33, wherein the first conductive layer 32Gb may be made of copper, galvanium or other suitable metal material. The first dielectric layer 330 and the first conductive layer 320b may be sequentially formed on the carrier substrate 240, that is, the first dielectric layer 330 and the first conductive layer 32〇b may be formed at different times. Of course, the first dielectric layer 330 and the first conductive layer 32〇b may also be formed at the same time. For example, the method of forming the first dielectric layer 330 and the first conductive layer 320b' includes pressing a backing copper foil onto the carrier substrate 240. Referring to Figure 3D, a plurality of first blind vias 332 are formed, wherein the first blind vias 332 extend from the first conductive layer 32〇b to the conductive pattern layer 310. In this embodiment, the first blind vias 332 may be formed by a laser drilling or plasma etching process. The laser used in the above laser drilling process may be a carbon dioxide laser, an ultraviolet laser (UV_YAG laser) or other suitable laser.

21 S 1360213 24880twf.doc/n This-field = some of the first hole 332 is formed by the laser drilling process, this: the bottom of a blind hole 332 will remain - some from the first dielectric layer 33 These defects affect the electrical quality of the circuit substrate. Therefore, the method of manufacturing the circuit substrate of the present embodiment further includes de-molding the first blind vias 332. In addition to the laser drilling process and the plasma remnant process, the first blind vias 332 may be formed by exposing and developing the first dielectric layer 33. In detail, the 'first dielectric layer 330' may be a developable high/knife material, i.e., the first dielectric layer 33 is photosensitive. Therefore, these first blind vias 332 can also be formed on the first dielectric layer through the exposure and development processes. Referring to FIG. 3E', a plurality of first conductive via structures 340a are formed in the first blind vias 332. The first conductive blind via structure 34A is connected to the first conductive layer 320b, and the conductive conductive layer 31b, that is, the first conductive blind via structure 340a enables the first conductive layer to be electrically connected to the conductive pattern layer 310. . In addition, these first conductive blind via structures (10) can be formed by electroless plating processes and electroplating processes. Referring to FIG. 3E and FIG. 3F, afterwards, a portion of the first conductive layer 32〇j is removed to form the first wiring layer 320b. In this embodiment, the method of removing the first conductive layer 320b may adopt a lithography and etching process. After the first wiring layer 320b is formed, a circuit substrate having a two-layer wiring structure (refer to FIG. 2A) is substantially completed, and in other embodiments not shown, the subsequent processing may include forming a solder resist. The layer is on the second circuit layer 320b, wherein the solder resist layer partially covers the first circuit layer 32%. '· twenty two

'(.S 1360213 2488〇twf.doc/n See ® 3G, then form a second dielectric layer 38〇•路层上上. After that, form a second conductive layer (not shown) at: Electrical: 380. Next, 'a plurality of second blind vias 382 are formed, wherein: the second blind vias 382 extend from the second conductive layer to the first wiring layer = after forming a plurality of second conductive blind via structures 340b Then, a portion of the second conductive layer is removed to form a second wiring layer 37. The second dielectric layer 380, the second conductive layer, and the second line are: • the second blind The hole 382 and the second conductive blind via structure 3 are formed in the same manner as the first dielectric layer 330, the first conductive layer 320b, the second layer 370, the first blind vias 332, and the first The electric blind hole structure ^ is the same 'is the same' and will not be repeated here. • After the second wiring layer 370 is formed, a circuit substrate 300b having a three-layer wiring structure is substantially completed. Meanwhile, a circuit board 300b is included. The wafer package carrier 2 〇 2 of the carrier substrate 240 is substantially completed. The wafer package carrier 202 It is manufactured by the upstream circuit board factory, and the wafer package carrier 202 is sent to the downstream wafer packaging factory after the manufacturing is completed to perform the process of subsequently assembling the wafer. In the above, the circuit substrate 300b may further include solder resist. Layer 35. In other words, after the second wiring layer 370 is formed, a solder resist layer may be formed on the wiring layer 370, wherein the solder resist layer 350 partially covers the second wiring layer 370 and exposes the second layer The pad 372. Referring to FIG. 3H, the 'circuit substrate 3〇〇b may further include a plurality of oxidation resistant layers 360. In detail, the oxidation resistant layers 360 may be formed on the second pads 372. Thus, When the wafer package carrier 202 is in transit 23

1J0UZ1J 24880twf. doc/π to the downstream crystal; i package the factory, these anti-oxidation layer second pads 372 to avoid oxidation" 曰 extension 3 (1 ;;; from the diagram redundant to Figure 3H disclosed line formation H, The circuit substrate 3 ()% _ 抑 amp amp 制造 所以 所以 所以 所以 所以 所以 所以 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Out

: 曰, four layers, five layers, six materials, any layer of the secret line of the board 0

It will be understood from the teachings of Figs. 3C to 3H how to manufacture a circuit substrate having a wiring structure of at least two layers or any other two. Therefore, it is emphasized here that the secret path method shown in Figs. 3C to =1 is used to make the number of layers of the line structure which the circuit board has.

360 can protect these μμ, / _ _ 31 ', after the arranging of the wafer 21 on the circuit substrate 3 〇〇 b will electrically connect the 曰 210 to the circuit substrate 300b. In this embodiment, the method for electrically connecting the circuit board 3 〇〇b to the circuit board 3 〇〇b may be a wire bonding level! These V lines W are formed between the wafer 210 and the second pads 372. In other embodiments not shown, the method of electrically soldering the substrate to the wafer 210 may also be a flip chip bonding or other suitable 3()% sentence&gt; FIG. 3J, and then forming the encapsulant 220 on the circuit substrate. The encapsulant 22 encases the wafer 21〇. In the present embodiment, the method of encapsulating the colloid 22 includes sealing and post-sealing 24 1360213 24880 twf.doc/n baking (PMC), and post-sealing baking, for example, encapsulation The colloid 220 is fed to a temperature of about 1803⁄4 for 4 hours of baking. Of course, depending on the product requirements, the temperature and time for baking the encapsulant 22 也 are also different. Referring to FIG. 3J and FIG. 3K, the carrier substrate 24 is removed. Thus, the first dielectric layer 330 can completely expose the bottom surface B of the first pads 312, and a chip package 2b is substantially fabricated. • From the above and the drawings, the first dielectric layer 33G, which can be used as the solder resist layer of the first pads 312, is not formed by an exposure and development process, and the first dielectric layer 330 does not cover these. The bottom surface B of the first pad 312 closely surrounds the sides of the first interfaces. Therefore, the first dielectric layer 33 can automatically align the first pads 312 without exposure and development processes, and does not cover the bottom surfaces B, thereby becoming the solder resist of the first pads 312. Floor. Thus, the 'th dielectric layer 330 can be said to have a self-aligned structure (sdf_aUgned structure). - Regarding the method of removing the carrier substrate 240., when the first material layer 242 and the first material layer 244 are both metal, the method of removing the carrier substrate 24 can perform an etching process on the carrier substrate 240. When the second material layer 244 is a viscous polymeric material, the method of removing the carrier substrate 240 can include stripping the first material layer 242. Referring to FIG. 3K and FIG. 3L, the chip package 2〇〇b may further include some conductive bumps 23G » In detail, after removing the carrier substrate, the conductive bumps 230 may be formed, wherein the conductive bumps are formed. Block 23〇 is connected to these first ports 312, respectively, 25 1360213 24880twf.doc/n. Thus, by these conductive bumps 230, the wafer package 2GGb K is assembled on a wiring board having a large line size such as a domain board. After forming the conductive bumps 230, the individual dicing can be performed to form a single chip package 2b. As described above, the present invention can make the circuit substrate strong by carrying the substrate, so that the chip package substrate and the chip package are not easily damaged during the manufacturing process, and 4 can be manufactured by a production facility. in this way,

The (9) package and the crystal package board of the present invention do not need to be manufactured by special production equipment, and the yield of the chip package and the wafer package carrier board can be improved. The invention is capable of manufacturing a chip package having a thinner thickness, and the thickness of the circuit substrate can be up to (10) micrometers or less. The wafer difficult body and the present invention can be carried today. The development trend of electronic devices. &lt;战τ

In addition, the 电&quot; electrical layer can be used as the anti-corrosion layer of these first-junctions, and the first-dielectric layer can be automatically aligned with these first-contact 塾's by the exposure-free process and will not cover these The first contact connects the bottom surfaces of the conductive bumps. In the conventional solder cake phase-welding method, these anti-follant layers (ie, the first dielectric layer) have a disadvantage of exposure=missing, and can further improve the hearing. Bribe "the yield of the domain board. Although the present invention has been disclosed above, it is intended to limit the invention, and any person having ordinary knowledge in the technical field without departing from the spirit and scope of the present invention can be used. Make some changes, so 26 1360213 24880twf.doc/n The invention is defined by the Weiwangwei attached to the t-materials. [Figure 1A to Figure 1E is a conventional wafer. FIG. 28 is a cross-sectional view showing a wafer body according to an embodiment of the present invention. FIG. 2 is a perspective view of a chip package according to another embodiment of the present invention. FIG. 3A to FIG. 3L are cross-sectional views showing the manufacturing method of the wafer wafer package of FIG. 2. [Main component symbol description] 100, 200a, 200b: wafer sealing body 100a, 2〇2: wafer package carrier 110 : Copper foil substrate 112 : dielectric core layer 114 ′ : copper foil 114 : copper wiring layer 114 a , 324 374: wafer bonding Sook trace 114b 114c:. Sook solder balls 120, 350: solder resist layer

27 1360213 24880twf.doc/n 130 : Nickel gold layer 140, 210 : wafer '150 : wire - 160 : encapsulation resin 170 : solder ball 220 : encapsulant 230 : conductive bump 240 : carrier substrate ® 242 : material layer 244: second material layer 300a, 300b: circuit substrate • 310: conductive pattern layer - 310': conductive material layer 312: first pads 320a, 320b: first wiring layer 320b': first conductive layer • 322, 372 : second pad 330 : first dielectric layer 332 : first blind hole 334 : surface 340a : first conductive blind hole structure 340b : second conductive blind hole structure 360 : oxidation resistant layer 370 : second circuit layer 28 1360213 24880twf.doc/n 380: second dielectric layer 382: second blind hole B: bottom surface Dl, D2: thickness W: bonding wire T: conductive bonding

Claims (1)

1360213 100-8-5 X. Patent Application Range: Γ〇Λ. Japanese pedicure 5 1. A chip package comprising: a circuit substrate comprising: a conductive pattern layer comprising a plurality of first pads, wherein each The first pad has a bottom surface; a first circuit layer is disposed on a side of the conductive pattern layer that is relatively away from the first interfaces; a first dielectric layer is disposed between the conductive pattern layer and the first circuit layer, wherein the first dielectric layer covers the conductive pattern layer and the first pads and exposes the first pads The first dielectric layer has a plurality of first blind vias extending from the first circuit layer to the conductive pattern layer; and a plurality of first conductive blind via structures respectively disposed on the first blind vias The conductive pattern layer is connected to the first circuit layer through the first conductive blind via structures; At least one wafer disposed on the circuit substrate and electrically connected to the first circuit layer of the circuit substrate; and an encapsulant disposed on the circuit substrate and covering the wafer. 2. The chip package of claim 1, further comprising a plurality of conductive bumps, the conductive bumps respectively connecting the first pads. 3. The chip package of claim 1, wherein the conductive pattern layers are composed of the first pads. 4. The chip package of claim 1, wherein the bottom surfaces of the first pads are substantially aligned with the surface of the first dielectric layer . 5. The chip package of claim 1, wherein the first circuit layer comprises a plurality of second pads, and the wafer is electrically connected to the circuit substrate through the pads. 1. The chip package according to claim 5, further comprising a plurality of bonding materials, the "connecting the bonding pads through the bonding wires." The wafer soldering layer of the fifth aspect, wherein the solder resist layer covers the first wiring layer and exposes the second circuit layer of the chip package 2 according to the first item a second blind hole between the first circuit layer and the second circuit layer; and a rectifying layer extending to the first conductive blind hole structure, The second secret layer passes through the second "double blind hole circuit layer" of the fifth side. The first conductive mesh structure is connected to the first. 9. The second circuit layer includes a plurality of second packages </ RTI> electrically connected to the circuit substrate. The chip package of the invention of claim 8, wherein the circuit substrate further comprises a solder resist layer </ RTI> and exposes the second pads. U. — a chip package carrier board, a carrier substrate; a replacement page of the month of 100-8-5, the solder mask layer covering--including: a circuit substrate disposed on the carrier substrate, and comprising: - conductive a pattern layer disposed on the carrier substrate and including a plurality of Each of the first pads has a bottom surface opposite to the carrier substrate; a first circuit layer disposed above the side of the conductive pattern layer away from the first pads; a dielectric layer disposed between the conductive pattern layer and the first circuit layer, and covering the conductive pattern layer, the first pads and the carrier substrate 'the first medium (four) exposing the first And the first dielectric layer having a plurality of ships extending from the first circuit layer to the first blind via of the conductive pattern layer; The first conductive hole structure is disposed in the first blind holes, and the conductive pattern layer is connected to the first circuit layer by the first conductive blind structures. h it Μ 第 第 第 第 “ “ “ “ “ “ “ “ “ “ “ 封 封 封 封 封 封 封 封 封 封 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载 承载The wafer package carrier board according to claim 12, wherein the material of the material layer comprises a metal or a ceramic competition. The wafer sealing board according to claim 12, 32 1360213 · i1·”- The material of the material layer in the production includes copper, and the domain is 100-8-5: in the replacement page, the wafer package carrier board described in the 12th patent section, wherein the first The material of the material layer includes metal or polymer materials. According to the scope of patent item 12; _, the material of the τ 5 haidi material layer includes nickel. The middle layer is made up of 11 pins, and the i conductive pattern layer is composed of the first pads. 18. The wafer package carrier according to claim 2 further includes a scale layer and the first circuit layer comprises a plurality of second interfaces, the fresh layer covering the first circuit layer, and Exposing the second pads. 19. The wafer package of claim 5, wherein the circuit substrate further comprises: - a second circuit layer disposed above the first circuit layer; a second dielectric layer disposed on the first a circuit layer and the second dielectric layer of the 彳 have a plurality of second blind holes from the second circuit; and a plurality of second conductive blind holes respectively disposed in the second In the blind via, the second circuit layer is connected to the first circuit layer through the second conductive blind via structures. 20. The wafer comprising: a solder mask according to claim 19, wherein the second wiring layer comprises a plurality of second pads, the solder mask covering the second wiring layer, and exposing the plurality of Two pads. A method for manufacturing a chip package, comprising: providing a carrier substrate and a conductive material 33 100-8-5 layer disposed on the carrier substrate; conducting: a layer of electrically conductive material to form a conductive pattern layer, Wherein the pattern layer comprises a plurality of first interfaces; Ί海中二=!第=the conductive pattern layer on the line base m fine material connection Covering: the sheet is formed on the circuit substrate, and the package is wrapped to remove the carrier substrate. 22·If you want to use the wafer dragon body of the 21st item, you will also include the conductive bumps of the shaft connecting the secret pads. - The manufacture of the wafer package described in paragraph 21 of the /VI application patent area == The method of carrying the substrate comprises performing the carrier substrate The method of claim 12, wherein the carrier substrate comprises a “material layer” and a second material layer disposed between the material layer and the conductive material layer, wherein The material of the second material layer is different from the conductive material layer. The method of manufacturing the chip package of claim 24, wherein the material of the first material layer comprises a metal or a ceramic. The method of manufacturing a chip package as described in claim 24, wherein the material of the first material layer comprises copper or aluminum. The method of manufacturing the chip package according to claim 24, wherein the material of the second material layer comprises a metal or a polymer material. 28. The method of fabricating a chip package according to claim 24, wherein the material of the second material layer comprises nickel. 29. The method of fabricating a chip package according to claim 21, wherein the method of electrically connecting the wafer to the wiring substrate comprises wire bonding. The method of manufacturing the chip package of claim 21, wherein the method of forming the circuit substrate comprises: forming a first dielectric layer on the carrier substrate, wherein the first dielectric layer covers the Carrying a substrate and the conductive pattern layer; forming a first conductive layer on the first dielectric layer; forming a plurality of first blind vias, wherein the first blind vias extend from the first conductive layer to the conductive a pattern layer; forming a plurality of first conductive blind via structures in the first blind vias; and removing portions of the first conductive layer to form a first trace layer. The method of manufacturing a chip package according to claim 30, wherein the method of forming the first dielectric layer and the first conductive layer comprises pressing a backing copper foil onto the carrier substrate. 32. The method of fabricating a chip package according to claim 30, wherein the first blind vias are formed by a laser drilling process or a plasma etching process. 33. The method of fabricating a chip package of claim 30, wherein the forming the first via holes comprises exposing and developing the first dielectric layer 35 1360213 100-8-5. 34. The method of fabricating a chip package of claim 30, further comprising forming a solder resist layer on the first wiring layer, wherein the solder resist layer partially covers the first wiring layer. The method of manufacturing the chip package of claim 30, wherein the method of forming the circuit substrate further comprises: forming a second dielectric layer on the first circuit layer; Forming a second conductive layer on the second dielectric layer; forming a plurality of second blind vias, wherein the second blind vias extend from the second conductive layer to the first wiring layer; forming a plurality of second conductive layers a blind via is formed in the second blind vias; and a portion of the second conductive layer is removed to form a second trace layer. The method of fabricating a chip package according to claim 35, wherein the method of forming the second dielectric layer and the second conductive layer comprises: laminating a backing copper clad on the carrier substrate. The method of fabricating the chip package of claim 35, wherein the second blind vias are formed by a laser drilling process or a plasma etching process. 38. The method of fabricating a chip package of claim 35, wherein the forming the second via holes comprises exposing and developing the second dielectric layer. 39. The method of fabricating a chip package of claim 35, further comprising forming a solder resist layer on the second wiring layer, wherein the solder resist layer partially covers the second wiring layer. 36 1360213 Annual incentives. Huaizheng Secret Page I