TWI356495B - Semiconductor device and method of fabricating the - Google Patents

Description

1356495 UMCD-2007-0411 26061twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit structure and a method of fabricating the same, and more particularly to a semiconductor device and a method of fabricating the same . [Prior Art] With the development of electronic component technologies such as communication, the operation speed of the transistor is becoming faster. However, because of the limited speed of movement of electrons and holes in the helium channel, the speed range of the transistor is also limited. The use of mechanical stress in the channel (MechanicaUtress) to change the speed of electrons and electricity; the speed of movement in the taste channel is a way to increase the transistor_distance. Taking a p-channel MOS (hereinafter referred to as apM〇s) as an example, it has been conventionally proposed to use a material such as bismuth telluride (SiGe) crystal as a main component of a source or a drain region of a transistor. Taking bismuth telluride as the main component of the source or the bungee region, compared with the material properties of ruthenium, since the ruthenium has a large atomic volume, a channel-compression stress can be applied, so The pole or bungee zone increases the mobility of the hole, which in turn increases the efficiency of the component. The technical method of using the Si Xihua fault (SiG crystal and other materials as the main component of the transistor source or the polar region is to completely remove the portion of the substrate towel that is intended to form the source or the non-polar region, and then reuse the selection. The selective area epitaxy growth technique is used to backfill the bismuth telluride. However, in the process of a typical MOS device (MOS), because of different design requirements, XJMCD-2007-0411 2606 The amount of ltwf.doc/n often occurs when the lengths of the channels of the plurality of transistors are the same, but the widths of the source or the drain regions are different along the length of the channel. "So, use the predetermined source in the substrate or not. The partial portion of the polar region is completely formed; the manner of the enamel enamel will cause different compression tensions in the channel regions of the respective transistors. On the other hand, when etching is performed, the size of the etched regions may also be different. The effect of the etch is such that a larger area will be etched faster 'causing a deeper etched depth and a side profile (pr〇flle). The tilt is more so that each The strain tension of each transistor is different. The strain tension of each transistor is different, which will result in different performance between the transistors, resulting in a decrease in the reliability of the semiconductor device. SUMMARY OF THE INVENTION The present invention is to provide a semiconductor device that can provide The same strain strain is applied to the channel region of each transistor. The present invention provides a semiconductor device comprising a plurality of transistors and a plurality of strain layers. Each of the transistors includes a source and a drain region on the substrate, and a source and a drain. a gate structure on the channel region between the polar regions. The channels of the transistors have the same length, but at least one source or the non-polar region has a width along the length of the channel along the channel region and other sources or immersions The regions are different in width along the length of the channel. The strain layers include a plurality of first strain layers and a plurality of second strain layers 'embedded in the substrates on both sides of each gate structure. The first width of the channel length direction is the same 'and the second width phase of each first strain layer along the length of the channel

Claims (1)

1356495 UMCD-2007-0411 26061twf.doc/n X. Patent application scope: f-year U-month-day revision replacement page 100-year-old November 2010 Article replacement 1. Page 1. A semiconductor component, including: Most electric BB Each of the transistors includes a source and a non-polar region on a substrate, and a gate structure is disposed over a channel region between the source and the drain region, wherein the plurality of transistors The lengths of the channels are the same, but at least one source or one of the drain regions is different in width along the length of one of the channel regions from the width of the other source or drain regions along the length of the channel; And a plurality of strain layers, including a plurality of first strain layers and a plurality of second Lu strain layers, respectively buried in the substrate on each side of the gate structure, wherein each of the first strain layers is along the channel A first width is the same in the length direction, and each of the second strain layers is the same in a second width along the length of the channel. • The semiconductor element described in the first aspect of the invention is wherein the first visibility is equal to the second width. Wherein the first width of the semiconductor as described in claim 1 is not equal to the second widths. Wherein, when the semiconductor component of the first aspect of the patent range, the hexagonal (four) crystal is a germanium channel gold oxide semiconductor (NM〇s), the strained layers are tensile strain layers; When the crystal is a p-type channel metal oxide semiconductor (PMOS), the strain-domain strain-shrinking layer is obtained. 5. The semiconductor device according to the fourth aspect of the invention, wherein each layer J includes: the first semiconductor compound a layer of the compressive strain comprising the second semiconductor compound telecrystal layer. 1356495 UMCD-2007-0411 26061twf.dbc/η. 6. The semiconductor device according to claim 5, wherein the first semiconductor compound crystal layer is a carbonized dream or an N-type carbonized germanium; the second semiconductor compound epitaxial layer is germanium germanium. Or p-type doped bismuth telluride. 7. The semiconductor device of claim 1, wherein at least one of the strained layers has a width along a length of the channel that is less than one of the source or drain regions along a length of the channel. The width. 8. The semiconductor device of claim 1, wherein at least one of the first transistors or the first source or the drain region of the first transistor has the same length along the length of the channel The third width. 9. The semiconductor device of claim 8, wherein the at least one of the second source or the second region of the second transistor has the same length along the length of the channel The fourth width, however, the fourth widths are not equal to the third widths. 10. The semiconductor device according to claim 9, wherein in the plurality of transistors, at least - the third source of the third transistor or the drain of the third transistor is positively along the length of the channel Different fifth width discs have a sixth width. 11. A semiconductor device comprising: a first source or drain region and a second source or drain region disposed between the first and the second source or the non-polar region Including a track zone, the direction of the channel length of the channel zone is - the _ direction, the direction of the channel width of the pass zone 3 is H direction, and is perpendicular to the first direction, wherein the first-hetero-polar region The second source dislocation region is in the first direction or the second direction system in the 23 1356495 iJMCD-2007-04 i] 26061 twf.doc/n month revision correction page 100 November 04 An asymmetry; a gate structure located on the channel region; and a first-first strain Zhan embedded in the substrate on either side of the interpole structure, the first strain layer and the second strain layer being along The width in the first direction is the same, wherein the second strain layer partially overlaps the projection surface of the second source or the drain region projecting the surface of the substrate, and the projection of the second strain layer is Within the projection surface of the second source or drain region. 12. The semiconductor device of claim 2, wherein the first source or the drain region and the second source or drain region have the same width along the first direction, and the second The width of the source or the non-polar region along the first direction is greater than the width of the first source or the non-polar region in the second direction. The semiconductor device of claim 5, wherein the second source or the non-polar region has a width along the first direction that is greater than the first source or the non-polar region in the first direction. The width of the first source or drain region is the same as the width of the second source or the non-polar region along the second direction. 14. The semiconductor device according to claim 5, wherein the first strain layer and the second strain layer are smaller in the first direction than the first source or the bottom region One of the second source or the non-polar regions is in a width along the first direction. 15. The semiconductor component of claim 5, further comprising: the first source or the drain region and the second region not overlapping the first and second strain layers At least one of the source or bungee regions 24 1356495 « Corrected replacement page on November 4, 100 • UMCD-2007-0411 26061twf.d〇c/n 4 on 0 16. As stated in claim 11 a semiconductor component, wherein when the semiconductor component is an NMOS, the first and second strain layers are tensile strain layers; and when the semiconductor component is a PMOS, the first and second strain layers are compressive strain layers. 17. The semiconductor device of claim π, wherein each of the tensile strain layers comprises a first semiconductor compound epitaxial layer; each of the compressive strain layers comprises a second semiconductor compound epitaxial layer. The semiconductor device of claim 1, wherein the first semiconductor compound epitaxial layer is tantalum carbide or N-doped tantalum carbide; and the second semiconductor compound epitaxial layer is tantalum or It has a p-type doping error. 19. The semiconductor device of claim 11, further comprising a diison metal layer ′ completely covering the crane- or bungee region and the second source or the non-polar region, respectively. 25 1356495 UMCD-2007-0411 26061twf.doc/n XI, Schema: Isa _ Han ISC 122α 122c 102α 102b 102c 1356495 260611WU 102α figure 2 102α Figure 3 < s > 1356495 26061 TW_J 102α 122α 118α 103α Figure 4 Factory 102c 1356495 « for products' << j Korea § 1356495 g 1356495 OS- qsl I 1MU909Z: