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TWI351762B - High performance stress-enhanced mosfets using si: - Google Patents

High performance stress-enhanced mosfets using si: Download PDF

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TWI351762B
TWI351762B TW093129826A TW93129826A TWI351762B TW I351762 B TWI351762 B TW I351762B TW 093129826 A TW093129826 A TW 093129826A TW 93129826 A TW93129826 A TW 93129826A TW I351762 B TWI351762 B TW I351762B
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pfet
channel
layer
nfet
source
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TW093129826A
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TW200525759A (en
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Huajie Chen
Dureseti Chidambarrao
Omer H Dokumaci
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Ibm
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10P50/692—

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)

Description

九、發明說明： 【發明所屬之技術領域】 本發明大關於-半導體裝置與製造奴，尤制於在元 件製造時，將拉伸（tensile)應力盘壓输r ^ 、至难、compressive) 應力加於元件中之半導體裝置與製造方法。 【先前技術】 在半導體裝置基板内之機械應力可調節裝置性能。亦即， 半導體裝置内之應力已知可增進半導體裝置特性。因此，在η 型裝置（如NFETs)及/或ρ型裝置（pFETs)之通道中產生拉 伸及/或壓縮應力，可改善一半導體裝置之特性。然而，相同 之應力分量，不論是拉伸應力或壓縮應力，對於nS裝置與p 型裝置之特性造成有差別之影響。 舉例而言，已知一裝置，形成於一石夕層（或帽蓋）上，而 此夕層係猫日日成長於另一蟲晶成長之SiGe層，且此siGe芦在 其矽基板上經過鬆弛（relaxed)時，呈現較佳之性能特徵。在 此系統中，此矽帽蓋經歷雙軸向拉伸應變。當磊晶成長於矽上 時，一未經鬆弛之SiGe層具有與石夕基板相符合之晶格常數。 在鬆弛時（例如，經由一高溫過程）’ SiGe晶格常數會接近其 4 旧 M〇4106TW.doc 1351762 固有（intrinsic)且大於矽之晶格常數。經完全鬆弛之siGe層 具有接近其固有值之晶格常數。當矽層磊晶於其上時，矽層配 合經鬆弛SiGe層之較大晶格常數，因而物理性雙軸向應力（如 擴張）施加於SiGe層上之矽層。由於此被擴張之;5夕層增加了 N型裝置的性能，且在siGe層中之較高Ge濃度改善了 p型 裝置的性能，因而施加於石夕層上之物理性應力有利於形成在其 上之裝置（如CMOS裝置）。 在矽基板上SiGe中之鬆弛係經由差排（misfitdislocation) 而發生。對於一個被完美鬆弛的基板而言，可想像到柵狀差排 均勻間隔而鬆弛了應力。差排在SiGe層中對晶格常數產生助 益，藉由在基板中提供額外半平面的矽以成全其固有值。此等 穿過SiGe/石夕介面不相稱的應力隨後被安置，且此SiGe晶格常 數得以變大。 然而，這種傳統解決方式的問題是，它需要多層非常薄的 SiGe緩衝層（如，厚度大約為5〇〇〇入至15〇〇〇A)以在其表面 部份完成差排，同時避免在SiGe層與矽基板層之間的線差排 (threadingdislocation) ’藉此在多層SiGe層之表面上之間達 成一鬆弛之SiGe結構。同時，這種解決方式明顯地增加了製 4IBM04106TW.doc 7 1351762 結構分別形成在與pFET通道有關以及與nFET通道有關 之基板上。pFET結構與nFET結構之區域被蝕刻至一預定 深度。在pFET結構經蝕刻之區域中提供具有與此層之基本 晶格常數不同晶格常數之第一材料，以在此pFET通道中提 供一壓縮應力。在ηΡΕΤ結構經餘刻之區域中提供具有與 此層之基本晶格常數不同晶格常數之第二材料，以在πΕΤ 通道中提供一拉伸應力。將nFET與pFET結構之源 極與沒極區域摻雜。 本發明的又一方面，係一半導體結構，包含一半導體基 板’且一 pFET與nFET形成在此基板中之各別通道中。 在pFET通道之源極與汲極區域中之材料第一層具有與基板 之晶格常數不同於之一晶格常數。在nFET通道之源極與汲 極區域中之材料第二層具有與基板之晶格常數不同於之一晶 格常數。 【實施方式】 本發明係關於一種半導體裝置與製造方法，其提供 CMOS元件之在nFET通道附近之拉伸應力，與在 pFET通道附近之壓縮應力。在本發明之一實施例中，縱 4IBM04106TW.doc 向之拉伸應力非常接近nFET通道，同時壓縮應力非常接 近pFET通道。此外，在本發明中，提供一方法與 結構以將SiGe與Si:C兩者材料整合入CMOS科技 中。 舉例而言，在矽基板中之源極與汲極（S/D)區域中提供 一咼度拉伸Si:C膜（如嵌入者）以在此閘極區域下、通道中 nFET結構之上縱向地提供張力。相似地，在矽基板中之 區域中提供一尚度壓縮SiGe膜（如嵌入者）以在此閘極區域 下、通道中pFET結構之上縱向地提供壓力。類似於SiGe 層Si.C層相g溥（低於其臨界厚度）同時未被鬆弛（reiaxed)。 nFET的電晶體通道區域中的張力係來自Si:c層的應 力，同時，pFET通道區域中由Si:c提供壓縮應力。 由於SiGe層係嵌在pFET的s/〇區域中，仍可形成低 阻的矽化物。有趣的是，嵌入的（如次平面或共平面對次平面） Si:C膜可以比平面_hSi:c之對絲提供更大的應力，原因在 於膜表面並非自由。在本發明中，不同的厚度與Si:c之凸出， 不淪對表面係屬嵌入或共平面或升起，都算。要了解到的是， 藉由调整在SiGe層中Qe之濃度，可以調整pFET通道中之 4IBM04106TW.docIX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor devices and manufacturing slaves, in particular, in the manufacture of components, tensile stress plates are pressed into r ^ , to difficult, compressive stresses A semiconductor device and a manufacturing method applied to an element. [Prior Art] Mechanical stress in a semiconductor device substrate can adjust device performance. That is, the stress in the semiconductor device is known to enhance the characteristics of the semiconductor device. Therefore, tensile and/or compressive stresses are generated in the channels of the n-type devices (e.g., NFETs) and/or p-type devices (pFETs) to improve the characteristics of a semiconductor device. However, the same stress component, whether tensile or compressive, has a differential effect on the characteristics of the nS and p-type devices. For example, a device is known which is formed on a layer of a stone layer (or a cap), and the cat layer grows on a SiGe layer of another insect crystal growth day by day, and the siGe reed passes over the crucible substrate thereof. When relaxed, a better performance characteristic is exhibited. In this system, the bonnet cap undergoes biaxial tensile strain. When the epitaxial growth is on the crucible, an unsettled SiGe layer has a lattice constant consistent with the stone substrate. When relaxed (for example, via a high temperature process), the SiGe lattice constant will be close to its intrinsic and greater than the lattice constant of 矽. The fully relaxed siGe layer has a lattice constant close to its intrinsic value. When the tantalum layer is epitaxially deposited thereon, the tantalum layer conforms to the larger lattice constant of the relaxed SiGe layer, and thus physical biaxial stress (e.g., expansion) is applied to the tantalum layer on the SiGe layer. Since this is expanded; the 5th layer increases the performance of the N-type device, and the higher Ge concentration in the siGe layer improves the performance of the p-type device, so the physical stress applied to the layer is favorable for formation. A device thereon (such as a CMOS device). The relaxation in SiGe on the germanium substrate occurs via misfitdislocation. For a substrate that is perfectly relaxed, it is conceivable that the grid-like rows are evenly spaced to relax the stress. The difference in the SiGe layer contributes to the lattice constant by providing an additional half-plane enthalpy in the substrate to complete its intrinsic value. These disproportionate stresses passing through the SiGe/Shixi interface are then placed and the SiGe lattice constant is increased. However, the problem with this conventional solution is that it requires multiple layers of very thin SiGe buffer layers (eg, thicknesses of about 5 to 15 〇〇〇A) to complete the difference in the surface portion while avoiding A threading dislocation between the SiGe layer and the germanium substrate layer ' thereby achieving a relaxed SiGe structure between the surfaces of the multilayer SiGe layer. At the same time, this solution significantly increases the structure of the IBM04106TW.doc 7 1351762 formed on the substrate associated with the pFET channel and the nFET channel, respectively. The pFET structure and the area of the nFET structure are etched to a predetermined depth. A first material having a different lattice constant from the fundamental lattice constant of the layer is provided in the etched region of the pFET structure to provide a compressive stress in the pFET channel. A second material having a different lattice constant from the basic lattice constant of the layer is provided in the residual region of the ηΡΕΤ structure to provide a tensile stress in the π 通道 channel. The source and the gate region of the nFET and pFET structures are doped. In still another aspect of the invention, a semiconductor structure includes a semiconductor substrate and a pFET and nFET are formed in respective channels in the substrate. The first layer of material in the source and drain regions of the pFET channel has a lattice constant different from the substrate from one of the lattice constants. The second layer of material in the source and drain regions of the nFET channel has a lattice constant different from the substrate than one of the lattice constants. [Embodiment] The present invention relates to a semiconductor device and a manufacturing method which provide a tensile stress of a CMOS element in the vicinity of an nFET channel and a compressive stress in the vicinity of a pFET channel. In one embodiment of the invention, the tensile stress is very close to the nFET channel, while the compressive stress is very close to the pFET channel. Moreover, in the present invention, a method and structure are provided to integrate both SiGe and Si:C materials into CMOS technology. For example, a source of stretched Si:C film (such as an intervener) is provided in the source and drain (S/D) regions of the germanium substrate to be below the gate region and above the nFET structure in the channel. Provide tension longitudinally. Similarly, a late-compressed SiGe film (e.g., an intervener) is provided in the region of the germanium substrate to provide pressure longitudinally above the pFET structure in the channel under the gate region. Similar to the SiGe layer Si.C layer phase g溥 (below its critical thickness) is not reiaxed. The tension in the transistor channel region of the nFET is from the stress of the Si:c layer, while the compressive stress is provided by Si:c in the pFET channel region. Since the SiGe layer is embedded in the s/〇 region of the pFET, a low resistance telluride can still be formed. Interestingly, the embedded (eg, sub-planar or coplanar versus sub-planar) Si:C film can provide greater stress than the planar _hSi:c pair of wires because the film surface is not free. In the present invention, different thicknesses and Si:c protrusions are not counted for embedding or coplanar or rising of the surface. It is to be understood that the 4IBM04106TW.doc in the pFET channel can be adjusted by adjusting the concentration of Qe in the SiGe layer.

Claims (1)

丨99年 公告本 十、申請專利範園·· - L -種糾-半導聽構之妓，包含下列各步驟 在-基板甲形成-p型場效電晶體（pFET)通道與1 型場效電晶體（nFET)通道； 在該pFET通道上形成一 pFET閘極堆疊與在該 通道上形成一 nFET閘極堆疊； 在與該pFET閘極堆疊有關之源極/沒極區域提供一第一 層材料，該第-層材料具有一晶格常數，有別於該基板之一* · 本晶格常數，俾在該pFET通道中產生一愿縮（⑺师腦】代） 狀態；及 在與該nFET閘極堆疊有關之源極/沒極區域提供一第二 層材料’該第二層材料具有一晶格常數，有別於該基板之該基 本晶格常數，俾在該nFET通道中產生—_狀 2.如請求们之方法，其中該第—層材料為砂其具有之 Ge含量相對於矽，約大於0%。 月求員1之方法，其中該第二層材料為Si:C。 、、項3之方法’其中该Si:C之C含量為約4%或更低。 4IBM041067W.doc 19 1351762丨99 Announcement Ten, Applying for Patent Fan Park··- L-type Correction-Semiconducting Hearing, including the following steps in the formation of -p-type field effect transistor (pFET) channel and type 1 field An effect transistor (nFET) channel; forming a pFET gate stack on the pFET channel and forming an nFET gate stack on the channel; providing a first in the source/nomogram region associated with the pFET gate stack a layer material having a lattice constant different from one of the substrates*, the lattice constant, and a enthalpy ((7) division) state in the pFET channel; The source/drain region of the nFET gate stack provides a second layer of material. The second layer material has a lattice constant that is different from the base lattice constant of the substrate, and the germanium is generated in the nFET channel. - _ shape 2. The method of claimant, wherein the first layer of material is sand having a Ge content relative to 矽, greater than about 0%. The method of claim 1, wherein the second layer of material is Si:C. The method of item 3, wherein the Si:C C content is about 4% or less. 4IBM041067W.doc 19 1351762 Μ年/σ月”日修土/更主/糯象 案號：93129826 99年10月27曰修正·替換頁 5,如請求項！之方法’其中該第一層材料為未被鬆弛之 SCe ’且該第二層材料為未被鬆他之Si:c且形成厚度介於川 至 100nm。 6. 如請求項1之方法，其中： 該第一層材料係藉由在該nFET通道上放置一第一遮單 並钱刻該PFET之遠源極/沒極區域，且在該ρρΕτ通道 區域中選擇性成長該第一層材料而形成；以及 該第二層材料係藉由在該PFET通道上放置一第二遮單 並姓刻该nFET之該源極/汲極區域，且在該nFET通 道區域中選擇性成長該第二層材料而形成。 7. 如請求項6之方法，更包含下列各步驟： 於蝕刻該pFET閘極堆疊有關之該源極/汲極區娀 之前，在該第一遮罩下方與該nFET閘極堆疊之上提供/ 保護層，且於蝕刻之後選擇性成長該第一層材料；以及 於蝕刻該nFET閘極堆疊有關之該源極/汲極區城 之前，在該第二遮罩下方與該pFET閘極堆疊之上提供〆 保護層，且於蝕刻之後選擇性成長該第二層材料。 2〇 4IBM04106TW.doc ^51762-Μ年/σ月”日修土/主主/糯象案号:93129826 October 27, 1999 Revision·Replacement Page 5, as requested in the method of 'The first layer of material is not relaxed SCe And the second layer of material is unsaturated Si:c and formed to a thickness of from 100 to 100 nm. 6. The method of claim 1, wherein: the first layer of material is placed on the nFET channel a first mask and a source of the far-source/no-polar region of the PFET, and selectively growing the first layer of material in the ρρΕτ channel region; and the second layer of material is used in the PFET channel A second mask is placed on the source/drain region of the nFET, and the second layer of material is selectively grown in the nFET channel region. 7. The method of claim 6 further includes The following steps: providing/protecting a layer under the first mask and over the nFET gate stack before etching the source/drain region of the pFET gate stack, and selectively growing after etching The first layer of material; and the source/drain region of the nFET gate stack Provided 〆 protective layer over the second mask stack below the pFET gate electrode, after etching and selective growth in the second layer material. 2〇 4IBM04106TW.doc ^ 51762- 0辱Μ &gt;修5/更正/鱗ft 案號：93129826 99年10月27日修正-替換頁 8.如請求項1之方法，其中該第一層材料與該第二層材料成 長至厚度約1〇至lOOnm。 9·如請求項1之方法，其中該第一層材料與該第二層材料係 嵌在該基板中。 10. 一種製造一半導體結構之方法，包含下列各步驟： 在一基板中形成一 P型場效電晶體（pFET)通道與一 n 型場效電晶體（nFET)通道； 在與該pFET通道及該nFET通道有關之該基板上，分 別形成包含一閘極堆4、源極及汲極之一 pFET結構與一 nFET結構； I虫刻該pFET結構與該nFET結構之源極/汲極區域； 於該pFET之閘極堆疊形成後，在pFET結構之該 源極及汲極區域中形成一第一材料，其具有之一晶格常數 不同於該基扳之一基本晶格常數，俾在該pFET通道中提供 一壓縮應力； 於該nFET之閘極堆疊形成後，在結構之該 源極及汲極區域中形成一第二材料，其具有之一晶格常數 不同於該基板之該基本晶格常數，俾在該通道中提供 4IBM04106TW.doc 21</ br> </ br> <br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br><br> About 1 〇 to 100 nm. 9. The method of claim 1, wherein the first layer of material and the second layer of material are embedded in the substrate. 10. A method of fabricating a semiconductor structure comprising the steps of: forming a P-type field effect transistor (pFET) channel and an n-type field effect transistor (nFET) channel in a substrate; Forming, on the substrate related to the nFET channel, a pFET structure including a gate stack 4, a source and a drain, and an nFET structure; I inscribed the pFET structure and a source/drain region of the nFET structure; After the gate stack of the pFET is formed, a first material is formed in the source and drain regions of the pFET structure, and has a lattice constant different from a basic lattice constant of the substrate. a compressive stress is provided in the pFET channel; after the gate stack of the nFET is formed, a second material having a lattice constant different from the base crystal of the substrate is formed in the source and drain regions of the structure Grid constant, 提供 provide 4IBM04106TW.doc in this channel 21 /ϋ月修正/更主/搞見 案號：93129826 外年丨0月27日修正-替換頁 一拉伸應力；及 接雜該nFET及pFET結構之源極與汲極區域。 U·如請求項10之方法，其中該第一材料為SiGe，且該第二 材料為Si:C。 12. 如請求項u之方法，其中 s亥第一材料在該pFET通道中產生一壓縮應力；及 該第二材料在該nFET通道中產生一拉伸應力。 13. 如請求項1〇之方法，其中： 該第一材料係藉由在該nFET結構與該pFET結構上放 置一保護層，並在該pFET通道之源極與汲極區域中成長 該第一材料而形成；及 該第二材料係藉由在該pFET結構上與該pFET結構及 該n FET結構之源極與汲極區域上放置—保護層，並在該 nFET通道之源極與汲極區域中成長該第二材料而形成/ 如請求項1G之絲，其巾雜—材料無第二材料係嵌在 該基板中。 4 旧 M04106TW.doc 丨公告冬?月厂日修正/更 正/補充- 案號：93129826 98年11月5曰修正-替換頁 基^Γ71()之妓’其巾該第―材料與該第二材料係自該 土珉之一表面伸出。 Θ求項1G之方法’其中該第—材料與該第：材料之 巧10 至 l〇〇nm。 17 求項10之方法，其中該第一材料為未被鬆弛之SiGe。 类8’:清求項1G之方法’更包含之步料當場（in situ)將p 雜物_至該第—機，且將η類摻雜物雜至該第二材 料，以分別形成該pFET與nFET之該源極與汲極區域。 19. 一種半導體結構，包含： —P型場效電晶體（pFET)通道，形成於一基板中； 一 η型場效電晶體（nFET)通道’形成於該基板中； —第一層材料’位於該pFET通道之源極與汲極區域中， 且具有一晶格常數不同於該基板之一基本晶格常數，俾在該 pFET通道中產生一第一應力狀態； 一第二層材料，位於該nFET通道之源極與汲極區域中， 且具有一晶格常數不同於該基板之一基本晶格常數，俾在該 4IBM04106TW.doc 23 1351762- , _ 1· I II Ρ· ί -、 ‘1- J- 專^月修王/更正/箱充 案號：93129826 99年丨0月27日修正-替換頁 nFET通道中產生一與該第一應力狀態不同之第二應力狀態。 20.如請求項19之結構，其中該第一層材料為SiGe，且該第 二層材料為Si:C。 24 4 旧 M04106TW.doc/ ϋ月修正/主主/搞见 Case No.: 93128826 丨月丨27月27 Revision-Replacement page A tensile stress; and the source and drain regions of the nFET and pFET structure. U. The method of claim 10, wherein the first material is SiGe and the second material is Si:C. 12. The method of claim u, wherein the first material produces a compressive stress in the pFET channel; and the second material produces a tensile stress in the nFET channel. 13. The method of claim 1, wherein: the first material is formed by placing a protective layer on the nFET structure and the pFET structure, and growing the first in a source and a drain region of the pFET channel. Forming a material; and the second material is placed on the pFET structure and the pFET structure and the source and drain regions of the n FET structure - a protective layer, and a source and a drain of the nFET channel The second material is grown in the region to form/as the filament of claim 1G, and the second material of the towel-material is embedded in the substrate. 4 Old M04106TW.doc 丨 Announcement Winter? Month Factory Day Correction/Correction/Supplement - Case No.: 93928926 November 5, 1998 Revision - Replacement Page Base ^Γ71() 妓 'The towel is the first - material and the second The material extends from the surface of one of the soils. The method of claim 1G wherein the first material and the first material are 10 to l 〇〇 nm. The method of claim 10, wherein the first material is SiGe that is not relaxed. Class 8': the method of claim 1G' further includes the step of in-situ p-contamination_to the first machine, and the η-type dopant is mixed to the second material to form the The source and drain regions of the pFET and nFET. 19. A semiconductor structure comprising: - a P-type field effect transistor (pFET) channel formed in a substrate; an n-type field effect transistor (nFET) channel 'formed in the substrate; - a first layer of material' Located in the source and drain regions of the pFET channel and having a lattice constant different from a basic lattice constant of the substrate, 俾 generating a first stress state in the pFET channel; a second layer of material located at The nFET channel has a source and a drain region, and has a lattice constant different from a basic lattice constant of the substrate, and is in the 4IBM04106TW.doc 23 1351762-, _ 1· I II Ρ· ί -, ' 1- J- Special ^月修王/Correct/Box Fill Case No.: 93192926 99年丨27月27 Revision-Replacement page The nFET channel produces a second stress state that is different from the first stress state. 20. The structure of claim 19, wherein the first layer of material is SiGe and the second layer of material is Si:C. 24 4 Old M04106TW.doc
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