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TWI348705B - Circuit and method for generating data output control signal for semiconductor integrated circuit - Google Patents

Circuit and method for generating data output control signal for semiconductor integrated circuit

Info

Publication number
TWI348705B
TWI348705B TW096130877A TW96130877A TWI348705B TW I348705 B TWI348705 B TW I348705B TW 096130877 A TW096130877 A TW 096130877A TW 96130877 A TW96130877 A TW 96130877A TW I348705 B TWI348705 B TW I348705B
Authority
TW
Taiwan
Prior art keywords
circuit
control signal
data output
output control
semiconductor integrated
Prior art date
Application number
TW096130877A
Other languages
English (en)
Other versions
TW200822141A (en
Inventor
Dong-Uk Lee
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200822141A publication Critical patent/TW200822141A/zh
Application granted granted Critical
Publication of TWI348705B publication Critical patent/TWI348705B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
TW096130877A 2006-11-13 2007-08-21 Circuit and method for generating data output control signal for semiconductor integrated circuit TWI348705B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060111431A KR100829455B1 (ko) 2006-11-13 2006-11-13 반도체 메모리 장치의 데이터 출력 제어신호 생성회로 및방법

Publications (2)

Publication Number Publication Date
TW200822141A TW200822141A (en) 2008-05-16
TWI348705B true TWI348705B (en) 2011-09-11

Family

ID=39368638

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096130877A TWI348705B (en) 2006-11-13 2007-08-21 Circuit and method for generating data output control signal for semiconductor integrated circuit

Country Status (3)

Country Link
US (2) US7570542B2 (zh)
KR (1) KR100829455B1 (zh)
TW (1) TWI348705B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI679851B (zh) * 2015-06-04 2019-12-11 美商英特爾公司 數位延遲鎖定迴路（ｄｌｌ）訓練技術

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100829455B1 (ko) * 2006-11-13 2008-05-15 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 출력 제어신호 생성회로 및방법
US7783452B2 (en) * 2007-03-08 2010-08-24 Advantest Corporation Signal measurement apparatus and test apparatus
KR100857450B1 (ko) * 2007-08-10 2008-09-10 주식회사 하이닉스반도체 반도체 메모리 장치의 출력 인에이블 신호 생성 회로 및방법
JP5600235B2 (ja) * 2007-10-11 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置、およびアドレスラッチの高速化方法
KR100925393B1 (ko) 2008-09-05 2009-11-09 주식회사 하이닉스반도체 반도체 메모리 장치의 도메인 크로싱 회로
US8094507B2 (en) 2009-07-09 2012-01-10 Micron Technology, Inc. Command latency systems and methods
KR101090469B1 (ko) * 2009-07-31 2011-12-06 주식회사 하이닉스반도체 데이터제어회로
KR20110040538A (ko) * 2009-10-14 2011-04-20 삼성전자주식회사 레이턴시 회로 및 이를 포함하는 반도체 장치
KR101075493B1 (ko) * 2010-02-26 2011-10-21 주식회사 하이닉스반도체 파이프 래치 회로와 그의 동작 방법
US8149038B1 (en) * 2010-03-22 2012-04-03 Altera Corporation Techniques for phase adjustment
KR101136985B1 (ko) 2010-08-18 2012-04-19 에스케이하이닉스 주식회사 반도체 메모리 장치의 데이터 출력 회로
KR101208961B1 (ko) 2011-01-28 2012-12-06 에스케이하이닉스 주식회사 레이턴시 제어 회로 및 방법
US8482315B2 (en) * 2011-08-23 2013-07-09 Apple Inc. One-of-n N-nary logic implementation of a storage cell
US9882709B2 (en) * 2016-05-10 2018-01-30 Macom Connectivity Solutions, Llc Timing recovery with adaptive channel response estimation
US10135606B2 (en) 2016-10-27 2018-11-20 Macom Connectivity Solutions, Llc Mitigating interaction between adaptive equalization and timing recovery
KR102730501B1 (ko) * 2017-01-11 2024-11-14 에스케이하이닉스 주식회사 반도체장치
KR102777474B1 (ko) * 2019-09-06 2025-03-10 에스케이하이닉스 주식회사 반도체장치
KR102771909B1 (ko) * 2020-09-15 2025-02-25 삼성전자주식회사 메모리 장치 및 그것의 클록 라킹 방법
CN113268220B (zh) * 2021-07-21 2021-09-21 南京后摩智能科技有限公司 基于时间域的存内乘法电路和基于时间域的存内乘加电路
US12155391B2 (en) 2021-12-09 2024-11-26 Rambus, Inc. Clock buffer

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1124785A (ja) * 1997-07-04 1999-01-29 Hitachi Ltd 半導体集積回路装置と半導体メモリシステム
JP2000067577A (ja) * 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP2000065902A (ja) * 1998-08-25 2000-03-03 Mitsubishi Electric Corp 半導体装置
JP2000163961A (ja) * 1998-11-26 2000-06-16 Mitsubishi Electric Corp 同期型半導体集積回路装置
JP4190662B2 (ja) * 1999-06-18 2008-12-03 エルピーダメモリ株式会社 半導体装置及びタイミング制御回路
US6446180B2 (en) 1999-07-19 2002-09-03 Micron Technology, Inc. Memory device with synchronized output path
JP2001339283A (ja) * 2000-05-26 2001-12-07 Mitsubishi Electric Corp 遅延回路およびそのための半導体回路装置
US7369445B2 (en) * 2001-07-20 2008-05-06 Samsung Electronics Co., Ltd. Methods of operating memory systems including memory devices set to different operating modes and related systems
DE10210726B4 (de) * 2002-03-12 2005-02-17 Infineon Technologies Ag Latenz-Zeitschaltung für ein S-DRAM
KR100486250B1 (ko) * 2002-07-10 2005-05-03 삼성전자주식회사 고주파수 동작을 위한 동기식 반도체 장치의 레이턴시제어 회로 및 그 방법
DE10330796B4 (de) * 2002-10-30 2023-09-14 Hynix Semiconductor Inc. Registergesteuerter Delay Locked Loop mit Beschleunigungsmodus
KR100468776B1 (ko) * 2002-12-10 2005-01-29 삼성전자주식회사 클락 지터의 영향을 감소시킬 수 있는 동기식 반도체메모리장치
KR100516694B1 (ko) * 2003-04-02 2005-09-22 주식회사 하이닉스반도체 반도체 메모리 장치
KR100522433B1 (ko) 2003-04-29 2005-10-20 주식회사 하이닉스반도체 도메인 크로싱 회로
KR100543937B1 (ko) 2003-10-31 2006-01-23 주식회사 하이닉스반도체 데이터 출력제어회로
KR100540487B1 (ko) 2003-10-31 2006-01-10 주식회사 하이닉스반도체 데이터 출력제어회로
KR100540472B1 (ko) 2003-10-31 2006-01-11 주식회사 하이닉스반도체 데이터 출력에 관한 동작마진이 향상된 메모리 장치
KR100532973B1 (ko) * 2004-04-30 2005-12-01 주식회사 하이닉스반도체 메모리 장치의 데이타 출력 드라이버 제어 장치
TWI267870B (en) 2004-05-10 2006-12-01 Hynix Semiconductor Inc Semiconductor memory device for controlling output timing of data depending on frequency variation
US7245551B2 (en) * 2004-08-19 2007-07-17 Micron Technology, Inc. Read command triggered synchronization circuitry
KR100636929B1 (ko) 2004-11-15 2006-10-19 주식회사 하이닉스반도체 메모리 장치의 데이터 출력 회로
KR100608371B1 (ko) * 2004-12-03 2006-08-08 주식회사 하이닉스반도체 메모리 장치의 데이타 출력 제어 방법 및 그 장치
US7443741B2 (en) * 2005-07-07 2008-10-28 Lsi Corporation DQS strobe centering (data eye training) method
KR100656464B1 (ko) * 2005-12-28 2006-12-11 주식회사 하이닉스반도체 반도체 메모리의 출력 인에이블 신호 생성장치 및 방법
KR100829455B1 (ko) * 2006-11-13 2008-05-15 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 출력 제어신호 생성회로 및방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI679851B (zh) * 2015-06-04 2019-12-11 美商英特爾公司 數位延遲鎖定迴路（ｄｌｌ）訓練技術

Also Published As

Publication number Publication date
US20080111596A1 (en) 2008-05-15
KR100829455B1 (ko) 2008-05-15
TW200822141A (en) 2008-05-16
US7813215B2 (en) 2010-10-12
US7570542B2 (en) 2009-08-04
US20100039878A1 (en) 2010-02-18

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