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TWI346461B - Phase frequency detector and phase-locked loop - Google Patents

Phase frequency detector and phase-locked loop

Info

Publication number
TWI346461B
TWI346461B TW097109813A TW97109813A TWI346461B TW I346461 B TWI346461 B TW I346461B TW 097109813 A TW097109813 A TW 097109813A TW 97109813 A TW97109813 A TW 97109813A TW I346461 B TWI346461 B TW I346461B
Authority
TW
Taiwan
Prior art keywords
phase
locked loop
frequency detector
phase frequency
detector
Prior art date
Application number
TW097109813A
Other languages
English (en)
Other versions
TW200840222A (en
Inventor
Shen Iuan Liu
Che Fu Liang
Hsin Hua Chen
Original Assignee
Mediatek Inc
Univ Nat Taiwan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mediatek Inc, Univ Nat Taiwan filed Critical Mediatek Inc
Publication of TW200840222A publication Critical patent/TW200840222A/zh
Application granted granted Critical
Publication of TWI346461B publication Critical patent/TWI346461B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0898—Details of the current generators the source or sink current values being variable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW097109813A 2007-03-22 2008-03-20 Phase frequency detector and phase-locked loop TWI346461B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US89628507P 2007-03-22 2007-03-22
US11/861,505 US7592847B2 (en) 2007-03-22 2007-09-26 Phase frequency detector and phase-locked loop

Publications (2)

Publication Number Publication Date
TW200840222A TW200840222A (en) 2008-10-01
TWI346461B true TWI346461B (en) 2011-08-01

Family

ID=39774057

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097109813A TWI346461B (en) 2007-03-22 2008-03-20 Phase frequency detector and phase-locked loop

Country Status (3)

Country Link
US (1) US7592847B2 (zh)
CN (1) CN101272143B (zh)
TW (1) TWI346461B (zh)

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KR101203370B1 (ko) * 2009-07-24 2012-11-21 쟈인 에레쿠토로닉스 가부시키가이샤 클록 데이터 복원 장치
KR100989848B1 (ko) * 2009-08-31 2010-10-29 동국대학교 산학협력단 클럭 및 데이터 복원 회로
JP5537192B2 (ja) * 2010-03-04 2014-07-02 スパンション エルエルシー 受信装置及びゲイン設定方法
US8400199B2 (en) * 2010-11-26 2013-03-19 Mediatek Inc. Charge pump, phase frequency detector and charge pump methods
CN102651647B (zh) * 2011-02-23 2015-01-07 联咏科技股份有限公司 延迟锁相回路及时脉信号产生方法
KR20120119343A (ko) * 2011-04-21 2012-10-31 에스케이하이닉스 주식회사 지연고정루프
US8461890B1 (en) * 2011-07-20 2013-06-11 United Microelectronics Corp. Phase and/or frequency detector, phase-locked loop and operation method for the phase-locked loop
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US9584303B1 (en) * 2015-10-28 2017-02-28 Futurewei Technologies, Inc. Reference-less frequency detector with high jitter tolerance
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CN107579736B (zh) * 2016-07-05 2023-09-19 综合器件技术公司 混合锁定检测器
US10860320B1 (en) 2016-12-06 2020-12-08 Gsi Technology, Inc. Orthogonal data transposition system and method during data transfers to/from a processing array
US10998040B2 (en) 2016-12-06 2021-05-04 Gsi Technology, Inc. Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
US10854284B1 (en) 2016-12-06 2020-12-01 Gsi Technology, Inc. Computational memory cell and processing array device with ratioless write port
US10891076B1 (en) 2016-12-06 2021-01-12 Gsi Technology, Inc. Results processing circuits and methods associated with computational memory cells
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US10770133B1 (en) 2016-12-06 2020-09-08 Gsi Technology, Inc. Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits
US10943648B1 (en) 2016-12-06 2021-03-09 Gsi Technology, Inc. Ultra low VDD memory cell with ratioless write port
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CN107005244B (zh) * 2017-02-08 2020-05-05 香港应用科技研究院有限公司 通过溢出计数器的减少计数使用查找表搜索的直接调制合成器的增益校准
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CN112118008B (zh) * 2019-06-20 2024-02-20 瑞昱半导体股份有限公司 锁相环电路
CN113541913B (zh) * 2020-11-05 2022-08-02 中兴通讯股份有限公司 时钟校准方法、时钟校准装置、电子设备和可读介质
CN114650058B (zh) * 2022-04-08 2024-07-05 福州大学 基于bbpd模块实现自校准的时间交织flash adc电路
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US12184292B2 (en) * 2022-07-22 2024-12-31 The Regents Of The University Of Michigan Sub-sampling phase locked loop (SSPLL) with saturated reference feedback
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Also Published As

Publication number Publication date
CN101272143B (zh) 2010-09-01
US7592847B2 (en) 2009-09-22
TW200840222A (en) 2008-10-01
US20080231324A1 (en) 2008-09-25
CN101272143A (zh) 2008-09-24

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees