TWI237875B - Process for planarizing array top oxide in vertical MOSFET DRAM arrays - Google Patents

Abstract

The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

Description

Revised 1237875

_ Case No. 92115613 V. Description of the invention (1) The technical field to which the invention belongs The invention relates to a semiconductor process, in particular _ dynamic transistor dynamic random access memory ff vertical (dynamic random access memory, hereinafter referred to as " AM) A method for flattening an oxide layer (array t ο poxide, AT 0) on an array by chemical mechanical polishing (hereinafter referred to as CMP) technology in the component clothing. Previous technology "-· 0 With the development of miniaturization of various electronic products, the design of DRAM components must also meet the requirements of high accumulation and high density. The trench capacitor DRAM device structure is one of the high-density DRAM architectures widely used in the industry. It is to etch a deep trench in a semiconductor substrate and make a trench capacitor in it, so it can effectively reduce the size of the memory cell and make good use of chip space. Compared with the conventional transistor, the gate, drain and drain A flat type, vertical M0S transistor trench DRAm (or vertical transistor trench DRA Μ) is a vertical drain, gate and source The placement design is formed on the upper half of the trench to form a vertical channel, so as to achieve the purpose of reducing the area of a unit DRAM element and increasing the accumulation of semiconductor elements. When making vertical transistor trench DRAM, it is known that After finishing the active area of the substrate and the insulation, apply a fluid anti-reflective material

Page 71237875 _Case No. 92115613_Year Month Day Amendment __ V. Description of the Invention (2) Anti-reflection coating (ARC) is used in conjunction with the subsequent reactive ion etching (RIE) process. The planarization of the oxide layer (A TO) on the array is also known as the ARC-RIE planarization process. However, due to the height difference between the peripheral area (suppo: rt regi ο η) and the array area ·, the ARC coated on the transition area between the peripheral area and the array area tends to be thick, resulting in the -RIE process being unable to Clearing the ARC on the transition area completely causes a defect, and this defect may cause a broken character line. In addition, it is known to make vertical and direct transistor trench DRAMs. When removing pad nitride, polysilicon and silicon nitride stacked layers are used to protect the mask. Nitride is facing the resistance of BHF. Poor decoration ability. Poor, it is also a need to overcome and improve the conventional technology. * · SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a method for flattening the oxide layer (ATTO) on the array by the CMP technology in the process of the vertical transistor DRAM device. To achieve the above object, a preferred embodiment of the present invention discloses a method for fabricating a vertical transistor dynamic random access memory device, which includes the following steps: providing a semiconductor substrate including a vertical transistor memory parameter array region, a periphery The circuit region and a transition region between the vertical transistor memory array region and the peripheral circuit region, where ^ ^ the vertical transistor memory array region contains a plurality of vertical ^ transistors ^ ·

Page 8 1237875 _Case No. 92115613_ 年月 日 _ί ± ^ _ V. Description of the Invention (3) The memory unit and the plurality of array active areas, the peripheral circuit area includes a plurality of peripheral active areas. The trench insulation is isolated from each other, and there is a first entire oxide layer and a first pad nitride layer above each active area of the array, and a second pad oxide layer and A second pad nitride layer; depositing a protective dielectric layer on the semiconductor substrate; forming an etching array (EA) photoresist layer on the protective dielectric layer, which covers the peripheral circuit area and part of the transition area; Using the EA photoresist layer as an etching mask, etching the protective dielectric layer not covered by the EA photoresist layer, exposing the first pad nitride layer in the vertical transistor memory array region; removing the EA light A protective layer; protecting the second plastic nitride layer in or around the peripheral circuit area i with the protective dielectric layer, removing the first pad nitride layer in the vertical transistor memory array area, and in the active area of the array A depression formed A hole; forming a side wall on the side wall of the recessed hole; depositing a dielectric layer covering the protective dielectric layer, the vertical transistor memory array area and the transition area on the peripheral circuit area, and simultaneously filling up The recessed hole; performing a chemical mechanical polishing (CMP) process, using the second silicon nitride layer as a polishing stop layer to polish the dielectric layer and the protective dielectric layer on the peripheral circuit area; on the semiconductor substrate Depositing a silicon layer; forming an etched peripheral area (ES) photoresist layer on the stone layer, shielding the vertical transistor memory array area and a part of the transition area, and exposing the peripheral circuit area; The ES photoresist layer is a mask, and the #etched layer is used to define an array etching mask. The ES photoresist layer is removed; the array etching mask is used to protect the vertical transistor memory array area. Sequentially remove the second pad silicon nitride layer and the second pad oxide layer in the peripheral circuit area, exposing the 1 ^ · page 9 1237875

Case No. Q911 Q V. Description of the invention (4) Λ_η is the base of the peripheral active area; who ^ a is on the base of the peripheral active area, ^ a rolling process, the mask is etched on the exposed array. _Formation into a sacrificial oxide layer; and remove the sign of the special attached and the month and month OIL and detailed explanations, the details of the use of the clear. Members for inspection only. Those who participate in the review process are kindly requested to make plans, with limitations to make the content inside and add to the technical know-how. Please refer to Figure 1 to Figure + for this embodiment. Figures 1 to 10 are used to make vertical transistor Indra μ according to the preferred embodiment of the present invention. A schematic cross-sectional view of the method of solidifying the body. Please look at Figure 1 first, Figure—A j ^ ^ ^ ^ ^ ^ ^ ", ju, n 0, for the definition of active regions 11, 21 and trench insulation 12, 22, 32 on the semiconductor substrate 10, and then flatten A cross-sectional view. As shown in FIG. 1, the semiconductor substrate 10 has a nearly flat surface that is planarized by chemical mechanical polishing (CMP), and includes at least a vertical MOSFET array region. l) a peripheral circuit (support) region 2 and a transition region (transiti ο nregi 〇η) between the vertical transistor memory array region 1 and the peripheral circuit region 2 3. in the vertical transistor memory array region 1 It contains a plurality of vertical transistors. The body memory unit 3 1 and the plurality of active regions 1 1, among which the plurality of vertical transistor memory cells 3 1 and the plurality of active regions 1 1 are separated by trench insulation 1 2 In the surrounding electricity

Page 10 1237875 _ Case No. 92115613 V. Description of the invention (5) Year Month Revision Road area 2 contains a plurality of active areas 2 1, which are isolated from each other by trench insulation 2 2. Above the active region 11, there is a pad of oxide layer 14 and a pad of nitride layer 15, and above the active region 21, there is a pad of oxide layer 24 and a pad of nitride layer 25. The structure of the vertical transistor memory cell 31 is a conventional technology, and it includes at least a capacitor electrode 33, a Trench Top Oxide (TTO) layer 34, and a vertical transistor polycrystalline silicon gate 35, of which the TTO layer 34 is used. The capacitor electrode 33 and the vertical transistor polysilicon gate 35 are insulated. As shown in FIG. 2, a protective dielectric layer 42 is then deposited on the surface of the semiconductor substrate. According to a preferred embodiment of the present invention, the protective dielectric layer 4 2 φ is formed by a high density plasma chemical vapor deposition (High Density Plamsa Chemical Vapor Deposition, hereinafter referred to as HDPCVD) method, and its thickness is between 500 and 1000. Angstrom, preferably around 750 angstroms. Before the deposition of the protective dielectric layer 42, the fluorinated nitride layer 25 can be etched away with about 50 angstroms to about 200 angstroms, preferably about 100 angstroms, of hydrogen fluoride acid / glycol (HFEG). . This can improve subsequent chemical mechanical polishing (CMP) performance. The role of the HDP protective dielectric layer 4 2 is to ensure compliance with the tritium gasification layer 25 in the peripheral circuit area 2, so that when the pad nitride layer 15 in the vertical transistor memory array area 1 is subsequently removed by hot phosphoric acid, , Will not be attacked by hot dish acid. Next, a #etched array (Etch Array, EA) photoresist layer 5 2 is formed on the protective dielectric layer 4 2, which covers the peripheral circuit area 2 and a part of the transition area 3. As shown in FIG. 3 Then, using the EA photoresist layer 5 2 as the last engraved mask, enter

Page 111237875 _Case No. 92115613_Year Month Date__ V. Description of the Invention (6) An etching process, such as isotropic wet etching, etches the protective dielectric layer not covered by the EA photoresist layer 5 2 4 2 To expose the pad nitride layer 15 of the vertical transistor memory array region 1. Subsequently, the opened vertical electro-memory memory array region 1 can be cleaned by using a buffered hydrofluoric acid (BHF) buffer. This step is also called a deglaze process. As shown in FIG. 4, the EA photoresist layer 52 is then removed. Then, the pad nitride layer 25 in the peripheral circuit region 2 is protected by the protective dielectric layer 42, and the pad nitride layer 15 in the vertical transistor memory array region 1 is removed / into the active region 1 by using hot phosphoric acid or other methods. A recessed hole 4 4 is formed above 1. Then, the pad oxide layer 14 in the vertical transistor memory array region 1 is removed, and a new pad oxide layer 14 'is grown again. The surface of the polysilicon gate 35 is also oxidized to form a thin oxide layer 70 having a thickness of only a few tens of angstroms. As shown in Figure 5, a sidewall 45 is formed on the sidewall of the recessed hole 44, preferably a silicon nitride sidewall. To form the silicon nitride sidewall sub-system, a silicon nitride film with a thickness of about 350 angstroms is deposited on the surface of the semiconductor substrate, and the silicon nitride film covers the sidewall and bottom of the recessed hole 44, and then the nitrogen is anisotropically etched back. Siliconized film. As shown in FIG. 6, an HDPCVD process is then performed to deposit an HDPCVD layer 46 on the surface of the semiconductor substrate 10, and the HDPCVD layer 46 covers the protection on the vertical transistor memory array region 1, the transition region 3, and the peripheral circuit region 2. The dielectric layer 42 also fills the recessed holes 44.

Page 121237875 _Case No. 92115613 Rev. _ V. Description of the Invention (7) As shown in Fig. 7, a chemical mechanical polishing (CMP) process is performed, and the silicon nitride layer 25 is used as a polishing stop layer. The fiDPCVD layer 46, the thin oxide layer 70, and the protective dielectric layer 42 are polished, and the polycrystalline silicon gates 35 of the vertical transistor memory cells 31 near the transition region 3 are exposed. As shown in FIG. 8, next, a silicon layer (not shown) is deposited on the surface of the semiconductor substrate 10, which may be polycrystalline silicon or amorphous silicon. Then, a #etched peripheral support (ES) photoresist layer 54 is formed on the silicon layer, and the ES photoresist layer 54 covers the vertical transistor memory array region 1 and a part of the transition region 3 and is exposed. Peripheral circuit area 2. Then, an etching process is performed, using the E S photoresist layer 54 as an etching mask, the silicon layer is etched, and an array etching mask 4 8 is defined. The E S photoresist layer 54 is subsequently removed. As shown in FIG. 9, the vertical transistor memory array region 1 is protected by an array etching mask 48, and the silicon nitride layer 25 and the pad oxide layer 24 of the edge circuit region 2 are sequentially removed. The pad silicon nitride layer 25 and the pad oxide layer 24 can be removed by a known wet chemical method. For example, the pad silicon nitride layer 25 is removed with a hot phosphoric acid solution, and the pad silicon nitride layer 25 is diluted with The hydrofluoric acid solution was removed. Before removing the silicon nitride layer 25, a deglaze process may be performed again, and a hydrofluoric acid buffer solution (BHF) with a volume ratio of 40: 1 (water: hydrofluoric acid) is used to open the periphery. The circuit area 2 is cleaned by the oxidation residue. After the pad oxide layer 24 is removed, an oxidation process is required to form a sacrificial oxide layer 2 4 ′ on the active region of the peripheral circuit region 2. According to a preferred embodiment of the present invention, due to multiple chemical solutions ''

Page 131237875 _ Case No. 92115613-Amendment-V. Description of the invention (8) Cleaning may cause erosion to the trench insulation structure 2 2 of the peripheral circuit area 2 and the trench insulation structure 2 2 and the active area 2 1 A gap (not shown) is created between the gaps. For this purpose, a silicon nitride backfilling step may be performed after the pad oxide layer 24 is removed. As shown in FIG. 10, the array etching mask 4 8 is then removed. Finally, the gate 62 is defined in the peripheral circuit area 2.

To sum up, the present invention has the advantage that the conventional ARC-RIE planarization process is replaced by the CMP process, so that the polysilicon gate 35 near the vertical transistor memory cell 31 of the transition region 3 is not left over. There are oxidation residues to avoid the electrical failure of the capacitor element. In addition, the planarization of the AT0 layer by CMP can obtain a flatter ▲ circle surface, which is convenient for subsequent gate definition. The above advantages show that the present invention has been combined with the industrial availability, novelty, and progress stipulated by the Patent Law. ^ ^ = Requirement, apply in accordance with the Patent Law. Please check and give examples. The claims of the present invention shall all be within the scope of the equivalent changes and repairs made to the patent scope of the present invention, which are described above only at the end of the patent section of the present invention.

1237875 _Case No. 92115613_ 年月 日 __ Brief Description of Drawings Brief Description of Drawings Figures 1 to 10 are schematic cross-sectional views of a method for manufacturing a vertical transistor memory device according to a preferred embodiment of the present invention, where: Figure 1 is The definition of the active area and trench insulation on the semiconductor substrate is completed, and then a flattened cross-sectional view is applied. Figure 2 is a schematic diagram of forming a protective dielectric layer and an Etch Array (EA) photoresist layer on the surface of the semiconductor substrate; Figure 3 is a schematic view of the EA photoresist layer as an etching mask, and the protective dielectric layer that is not covered by the EA photoresist layer is etched. Figure 4 is the removal of the pad nitride layer and pad oxide layer of the vertical transistor shoulder to form a new layer. Schematic diagram of the oxide layer; Figure 5 is a schematic diagram of the formation of sidewalls in the recessed holes above the active area; Figure 6 is a schematic diagram of the HDPCVD deposition; Figure 7 is a chemical mechanical polishing (CM.P) process to remove the HDPCVD layer and the thin oxide layer Figure 8 is a schematic diagram of forming an ES photoresist layer and an array etching mask on the surface of a semiconductor substrate. Sook nitrogen fossil Xi layer circuit region and a schematic diagram of the pad oxide layer is removed; FIG ten array etching mask is removed and forming a gate region in the peripheral circuit schematic.

Page 15 1278785 _Case No. 92115613 _ Revised diagrams Brief description of diagrams Symbol descriptions. 1 Vertical transistor memory array area 2 Peripheral circuit area 3 Transition area 10 Semiconductor substrate 11 Active area 12 Trench insulation 14 Pad oxidation Layer 15 pad silicon nitride layer 21 active area 22 trench insulation 2 pad oxide layer 25 pad silicon nitride layer 31 vertical transistor memory cell 32 trench insulation 33 capacitor electrode 34 ττ'ο layer 35 vertical transistor 'bulk polysilicon gate Electrode 42 protective dielectric layer 44 recessed hole 46 HDPCVD layer 48 array engraved mask 52 ΕΑ photoresist layer 54 ES photoresist layer 62 gate

Page 16

Claims (1)

1237875 Case No. 92Π5613 Amendment VI. Patent Application Scope 1. A manufacturing method, which includes a direct-current crystal memory array in the array region of the lower part, includes ionization, and is above the oxide layer. The layer should be de-layered, layer-deposited, deposited on the sinking layer, and provided for half a week's vertical electric train step conductor base circuit circuit edge circuit body array multiple peripheral crystal dynamic random access memory element square and perimeter The memory cell and a plurality of Mo in each of the array and a semiconductor with the protection peripherals, the first pad of the EA light protection medium except the EA, the protection removed from the array, the depression, and the vertical first pad remaining two. The resistive layer of the dielectric layer on the substrate is the electric layer, the nitrided layer, the photoresistive layer, the dielectric layer, the electric layer of the active hole of the crystal array, the bottom of the transistor, the area of the active array, the main nitrided oxide deposition, and The etching exposure includes a vertical transistor memory array and a region between the vertical transistor memory, where a number of The vertical transistor is recorded in the peripheral circuit area and separated by trench insulation. The active area area and the active area layer are included in the layer, and the layer and a mask are protected into a button part. In the meantime, there are two pad nitride layers on the dielectric etched transition etched directly on the dielectric array; a layer; a column (EA) photoresist layer, the area of which is not the EA photoresist layer A crystal-covered memory array region protects the second nitrogen pad memory array region in the peripheral circuit region from forming a recessed hole in the first pad nitrogen region; a sidewall is formed on the side wall; and the peripheral circuit region is covered. The protection medium memory array region and the transition region, circle Page 171237875 _ Case No. 92115613 _ Year Month Amendment _ 6. The scope of the patent application fills the recessed hole at the same time; and a chemical mechanical polishing (CMP) process is performed, using the second silicon nitride layer as a polishing stop layer Grind the dielectric layer and the protective dielectric layer on the peripheral circuit area. 2. The method for manufacturing a vertical transistor dynamic random access memory device as described in item 1 of the scope of patent application, wherein the method further includes the following steps after the chemical mechanical polishing (CMP) process: A silicon layer is deposited on the semiconductor substrate; an etched peripheral region (ES) photoresist layer is formed on the silicon layer, shielding the vertical transistor memory array 'region and a part of the transition region, and exposing the peripheral circuit region; The ES photoresist layer is used as a mask, and the stone layer is etched to define an array etching mask; and the ES photoresist layer is removed. 3. The method for manufacturing a vertical transistor dynamic random access memory device as described in item 2 of the patent application scope, wherein the method further includes the following steps after removing the ES photoresist layer: etching the mask with the array Protect the vertical transistor memory array region, and sequentially remove the second pad silicon nitride layer and the second pad oxide layer from the peripheral circuit region to expose the substrate of the peripheral active region, and perform an oxidation process. Forming a sacrificial oxide layer on the exposed substrate of the peripheral active area; and removing the array etching mask. Page 18 1237875 Case No. 92115613 Amendment VI. Application for Patent Scope 4. The method for making a vertical transistor dynamic random access memory device as described in item 2 of the application scope, wherein the silicon layer is made of polysilicon Make up. 5. The method for manufacturing a vertical transistor dynamic random access memory device as described in the second item of the scope of the patent application, wherein the silicon layer is composed of amorphous silicon. 6. As the first item of the scope of the patent application The method for manufacturing a vertical transistor dynamic random access memory device, wherein the vertical transistor memory unit includes at least a capacitor% pole, a Trench Top Oxide (TT0) layer, and a vertical transistor silicon. The gate, wherein the TTO layer is used to insulate the capacitor electrode and the vertical transistor polycrystalline silicon gate. 7. The method for manufacturing a vertical transistor dynamic random access memory device as described in item 1 of the scope of patent application, wherein before depositing the protective dielectric layer, hydrofluoric ethylene glycol (hydrofluoric ethylene glycol, (HFEG) The second pad nitride layer is engraved with a predetermined thickness. 8. The method for making a vertical transistor dynamic random access memory element as described in item 7 of the scope of patent application, wherein the predetermined thickness is about 50 angstroms to about 200 angstroms. Page 191237875 _ Case No. 92115613_ Year Month Date __ VI. Patent Application Scope 9. A method for manufacturing a vertical transistor dynamic random access memory device, comprising the following steps: providing a semiconductor substrate including a vertical A crystal memory array region, a peripheral circuit region, and a transition region between the vertical transistor memory array region and the peripheral circuit region. The vertical transistor memory array 'column region includes a plurality of array active regions. A plurality of peripheral active regions are included in the peripheral circuit region. Above each active region of the array, there is a first pad oxide layer and a first hafnium nitride layer, and above each peripheral active region, It has a second pad oxide layer and a second integrated nitride layer; a protective dielectric layer is deposited on the semi-spider substrate; and an etching array (EA) photoresist layer is formed on the protective dielectric layer and covers the Peripheral circuit area and part of the transition area; using the EA photoresist layer as an etching mask, etching the protective dielectric not covered by the EA photoresist layer Layer, exposing the first pad nitride layer in the vertical transistor memory array area; removing the EA photoresist layer; removing the first pad nitride layer in the vertical transistor memory array area; depositing a dielectric An electrical layer covering the protective dielectric layer, the vertical transistor memory array region, and the transition region on the peripheral circuit region, and filling the recessed hole at the same time; performing a chemical mechanical polishing (CMP) process to the second The silicon nitride layer is a polishing stop layer that polishes the dielectric layer and the peripheral circuit area. Page 20 1237875 _ Case No. 92115613_year_i ±± _ 6. The protection dielectric layer in the scope of patent application; depositing a silicon layer on the semiconductor substrate; forming an etched peripheral area on the silicon layer ( ES) a photoresist layer, which shields the vertical transistor memory array region and a part of the transition region, and exposes the peripheral circuit region; using the ES photoresist layer as an etching mask, etching the silicon layer, and defining a Array etching mask; and removing the ES photoresist layer. 10. The method for making a vertical transistor dynamic random access memory device as described in item 9 of the scope of the patent application. After removing the ES photoresist layer in the method, the method further includes the following steps: The array etching mask protects the vertical transistor memory array area, and sequentially removes the second pad silicon nitride layer and the second pad oxide layer from the peripheral circuit area to expose the substrate of the peripheral active area. An oxidation process, forming a sacrificial oxide layer on the exposed substrate of the peripheral active area; and removing the array etching mask. Page 21