TW200428594A - Process for planarizing array top oxide in vertical MOSFET DRAM arrays - Google Patents

Abstract

The present invention provides a process for planarizing array top oxide (ATO) in vertical MOSFET DRAM arrays. In contrast to the prior art ARC-RIE planarization method for EA/ES (etch array/etch support) module, the present invention takes advantage of chemical mechanical polishing (CMP) technique to overcome residue problems that used to occur at the transition region or array edge. It might cause capacitor device failure when ATO residue is left on the transition region.

Description

200428594 V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a semiconductor process, and more particularly to a dynamic random access memory (vertical 1 transist 〇r) In the process of DRAM) device, chemical mechanical polishing (hereinafter referred to as CMP) technology is used to planarize the array top oxide (ATTO). With the development of previous technologies toward the miniaturization of various electronic products, the design of DRA M components must also meet the requirements of high accumulation and high density. The trench capacitor DRAM device structure is the high-density DRA widely used in the industry. First, the deep trench is engraved in the semiconductor substrate and the capacitance of the trench is engraved in the trench. Therefore, the size of the memory unit can be effectively reduced, and the chip space can be properly used. Compared with the traditional transistor, where the source, gate, and drain are placed in a plane, the vertical M0S transistor trench DRAM (or straight transistor trench DRAM) uses the drain, gate, and source electrodes. A vertical placement gauge is formed on the upper half of the trench to form a silk-shaped channel, so as to achieve the purpose of reducing the area of a unit DRAM element and increasing the production of semiconductor elements. v. It is also known that when making vertical transistor trench DRAM,

200428594

After the production of the moving area and insulation, an anti-reflection coating (ARC) with fluidity is applied together with a subsequent reactive ion etching (RIE) process to perform an oxidation layer on the array ( AT0) planarization, which is the ARC-RIE planarization process that is well known to those in the industry. However, due to the height difference between the support region and the array region, the ARC coated on the transition region between the peripheral region and the array region is often thick, so that the RIE process cannot convert the ARC on the transition region. Complete removal will cause a defect, and this defect may cause the character line to open. In addition, it is known to make vertical transistor trench DRAM. When removing the pad nitride layer, a polycrystalline silicon layer and a silicon nitride stacked layer are used to protect the mask, and the nitride layer is facing the resistance of BHF. Poor etching ability is also the place where the conventional technology needs to be overcome and improved. SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a method for AT layer oxidation by using CMP technology in the fabrication process of a vertical transistor dram element. In order to achieve the above object, a preferred embodiment of the present invention discloses a method A method for fabricating a vertical transistor dynamic random access memory device includes the following ρ1 = π for a semiconductor substrate, including a vertical transistor memory, product V, a peripheral circuit area, and a vertical transistor memory 200428594 V. Description of the invention (3) The transition region between the f Ϊ ^ region and the peripheral circuit region, which makes the == ί body region contain a plurality of vertical transistor domains' in the peripheral circuit region: ionization: where On each of the array main regions; a pad K layer and a first pad on top of the nitrogen pad have a second pad oxide; there is a second pad oxidation; Γ ′ ;: a semiconductor substrate is deposited on each of the peripheral active regions; Protect the dielectric layer · The first pad nitride layer; Yu Cheng Yi #etched array (ΕΑ) photoresist layer, which covers the protective medium, the layer forms a portion of the transition region; with the ΕΑ light [和 上 二 2 = J road area with f The protection medium covered by the EA photoresist layer is a cover; the first pad of nitride reed is not etched into the memory array area?] 3 transistor ^ ^ ^ ^ milk 1 d, remove the EA photoresist layer; Layer by layer, the second pad nitride a in the peripheral circuit area is protected by the guaranteed dielectric layer, the first ridge in the vertical transistor memory array area is removed, and a recessed hole is formed in the active area of the array; The depression = a sidewall is formed on the side wall of the hole, and a dielectric layer is deposited to cover the protective dielectric layer, the vertical transistor memory array area and the transition area on the peripheral circuit area, and simultaneously fill the depression hole Performing a mechanical polishing (CMP) process, using the second hafnium silicon nitride layer as a polishing stop layer to polish the dielectric layer and the protective dielectric T-stop layer on the peripheral circuit area; on the semiconductor substrate Deposit a Shi Xi layer; form on the Shi Xi layer-etch the peripheral area (ES) photoresist layer, shield the vertical transistor memory array area and part of the transition area 'and expose the peripheral circuit area; use the ES Photoresist layer engraved mask for money Xi stone layer, serve to define a - Array

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V. Description of the invention (4) Column engraved masks; remove the second pad silicon nitride of the vertical transistor memory; the base active mask in the peripheral active area; the base array etching mask in the peripheral active area. The ES photoresist layer; sequentially oxidizing the bottom layer with the body array region; forming a sacrificial oxygen array etching mask on the bottom by performing an oxidation process to remove the peripheral circuit region layer to expose the process 'For the exposed layer; and to remove this, in order for your reviewers to better understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary explanation, and are not intended to limit the present invention. Embodiments Please refer to FIGS. 1 to 10, which are schematic cross-sectional views of a method for fabricating a vertical transistor memory device according to a preferred embodiment of the present invention. First, please refer to FIG. 1. FIG. 1 is a cross-sectional view after the definitions of the active regions Π, 21 and the trench insulations 12, 22, and 32 are completed on the semiconductor substrate 10. As shown in FIG. 1, the semiconductor substrate 10 has a nearly flat upper surface which is planarized by chemical mechanical polishing (CMP), and includes at least a vertical transistor memory array region (vertica 1 M 0 SFET array). _ region) l, a peripheral circuit support region 2 and a transition region between the vertical transistor memory array region 1 and the peripheral circuit region 2

Page 9 200428594 V. Description of the Invention (5) Transition region 3. The vertical transistor memory array region 1 includes a plurality of vertical transistor memory cells 3 1 and a plurality of active regions 1 1. Among the plurality of vertical transistor memory cells 3 1 and a plurality of active regions 1 1 It is isolated by trench insulation 1 2. The peripheral circuit area 2 includes a plurality of active areas 2 1, which are isolated from each other by trench insulation 2 2. Above the active region 11, there is a pad of oxide layer 14 and a pad of nitride layer 15, and above the active region 21, there is a pad of oxide layer 24 and a pad of nitride layer 25. The structure of the vertical transistor memory unit 31 is a conventional technology, and it includes at least a capacitor electrode 3 3, a Trench Top Oxide (TT0) layer 34, and a vertical transistor polycrystalline silicon anode 35, of which The TT 0 layer 34 is used to insulate the capacitor electrode 33 and the vertical transistor polysilicon gate 35. As shown in FIG. 2, a protective dielectric layer 42 is deposited on the surface of the semiconductor substrate 10. According to a preferred embodiment of the present invention, the protective dielectric layer 42 is formed by a high density plasma chemical vapor deposition (High Density Plamsa Chemical Vapor Deposition, hereinafter referred to as HDPC VD) method, and has a thickness of 50 to 100 0. Angstrom is preferably around π0 soil. Before depositing the protective dielectric layer 42, a pad of about 50 angstroms to about 200 angstroms, preferably about 100 angstroms, can be etched away with hydrofluoric acid / ethylene glycol (HFEG). Nitrided layer 2 5. This can improve subsequent chemical mechanical polishing (CMP) performance. The role of the HDP protection dielectric ^ 4 2 is to protect the hafnium nitride layer 25 in the peripheral circuit region 2 so that 3 shots are removed in the subsequent vertical transistor memory array region 1 with hot phosphoric acid.

Page 10 200428594 V. Description of the invention (6) The nitrided layer 15 is not attacked by hot phosphoric acid. Next, an Etch Array (EA) photoresist layer 52 is formed on the protective dielectric layer 4 2, which covers the peripheral circuit area 2 and part of the transition area 3. As shown in FIG. 3, then, using the EA photoresist layer 52 as an etching mask, an etching process is performed, such as isotropic wet etching, and the protective dielectric layer 42 not covered by the EA photoresist layer 52 is etched to expose A pad nitride layer 15 of the vertical transistor memory array region 1. Subsequently, a buffered hydrofluoric acid (BHF) can be used to clean the open vertical electro-memory memory array region 1 by oxidizing residues. This step is also called a deg 1 aze process. As shown in FIG. 4, the EA photoresist layer 52 is then removed. Then, the hafnium nitride layer 25 in the peripheral circuit region 2 is protected by the protective dielectric layer 42. The pad nitride layer 15 in the vertical transistor memory array region 1 is removed by using hot phosphoric acid or other methods. A recessed hole 4 4 is formed above the region 丨 丨. Then, the pad oxide layer 14 in the vertical transistor memory array region 1 is removed, and a new pad oxide layer 4 is formed again. As shown in FIG. 5, a sidewall f 4 5 ′ is preferably a silicon nitride sidewall on the sidewall of the recessed hole 44. A silicon nitride sidewall subsystem is formed half before. A silicon nitride film with a thickness of about 350 angstroms is deposited on the surface of the substrate, and the silicon nitride film covers the sidewall and bottom of the recessed hole 44, followed by anisotropic remnant. The silicon nitride film is etched.

200428594 V. Description of the invention (7) As shown in FIG. 6, an HDPCVD process is performed to deposit an HDPCVD layer 46 on the surface of the semiconductor substrate 10, and the HDPCVD layer 46 covers the vertical transistor memory array region 1, the transition region 3 and the protective dielectric layer 4 2 on the peripheral circuit area 2 and simultaneously fill the recessed holes 4 4. As shown in FIG. 7, a chemical mechanical polishing (CMP) process is then performed, using the silicon nitride layer 25 as a polishing stop layer to polish the HDPCVD layer 46 and the protective dielectric layer 42, and expose the vertical transistor near the transition region 3. The polycrystalline broken gate 35 of the memory unit 31. As shown in FIG. 8, next, a silicon layer (not shown) is deposited on the surface of the semiconductor substrate, which may be polycrystalline silicon or amorphous silicon. An etched support region (ES) photoresist layer 54 is formed on the silicon layer, and the ES photoresist layer 54 shields the vertical transistor memory array region 1 and a part of the transition region 3 and exposes the periphery. Circuit area 2. Then, an etching process is performed, using the ES photoresist layer 54 as an etching mask, the silicon layer is etched, and an array etching mask 48 is defined. The ES photoresist layer 54 is then removed. Said # 二 ， 2 2 不 ， Then, using the array coin engraving mask 4 8 to protect the vertical electrical second layer 52 5 = and ί 2 area 1, and sequentially remove the yttrium nitride of peripheral circuit area 2 ί f 24 Remove. The nitrogen-cutting layer 25 and erbium oxide 2⑽1 ^ are removed by a known wet chemical method, for example, the pad nitrogen is removed with a rhenium acid solution, and the pad silicon nitride layer 25 is diluted with hydrogen 200428594 V. Description of the invention (8), The acid solution was removed. Before removing the silicon nitride layer 25, a degrinding process can be performed again, using a nitrogen buffer solution (BHF) with a volume ratio of 40: i (water: hydrofluoric acid) to open The peripheral circuit area 2 is cleaned by oxidation residues. After the pad oxide layer 2 4 is removed, an oxidation process is further performed to form a sacrificial oxide layer 2 4 ′ on the active region of the peripheral circuit region 2. According to a preferred embodiment of the present invention, due to repeated chemical solution cleaning, the trench insulation structure 2 2 of the peripheral circuit area 2 may cause intrusion, and a gap may be generated between the trench insulation structure 2 2 and the active area 21 ( (Not shown) 'For this reason, after the pad oxide layer 24 is removed, a step of backfilling the nitride with nitride stone can be performed. As shown in FIG. 10, the array etching mask 48 is then removed. Finally, the gate 6 2 is defined in the peripheral circuit area 2. In summary, the present invention has the advantage that the CMP process is used to replace the conventional ARC-RIE planarization process, so that the polysilicon gate 35 of the vertical transistor memory cell 31 near the transition region 3 is not over Oxidation residues remain to avoid the electrical failure of the capacitor. In addition, the planarization of the AT0 layer by CMP can obtain a relatively flat wafer surface, which is convenient for subsequent gate definition. All the above advantages show that the present invention has fully complied with the statutory requirements of industrial availability, novelty, and progress as stipulated by the Patent Law. The application has been filed in accordance with the Patent Law. Please check and approve the patent in this case. The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall belong to the present invention patent.

200428594 V. Coverage of Invention Description (9). I »· Page 14 200428594 Brief Description of the Drawings Brief Description of the Drawings Figures 1 to 10 are schematic cross-sectional views of a method for manufacturing a vertical electro-mechanical memory device according to a preferred embodiment of the present invention. Explanation of Symbols of the Drawings 1 Vertical transistor memory array domain 2 Peripheral circuit area 3 Transition area 10 Semiconductor substrate 11 Active area 12 Trench insulation 14 Pad oxide layer 15 Pad silicon nitride layer 21 Active area 2 2 Trench insulation 24 Pad oxide layer 25 pads of silicon nitride layer 31 vertical transistor memory cell 32 trench insulation 33 capacitor electrode 34 TT0 layer 35 vertical transistor polycrystalline silicon gate 42 protective dielectric layer 44 recessed hole 46 HDPCVD layer 48 array engraving mask 52 EA photoresist layer 54 ES photoresist layer 62 gate

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Claims (1)

200428594, the active domain layer of the active domain is included in the package domain, and a protective medium is formed to form a moment and part of the overprint mask, which exposes the vertical body dynamic random access memory element. One and one intermediaries include a dynamic area domain, its area, and a peripheral circuit memory array area is formed on a wall to form a cover on the peripheral electromemory array area. 6. Patent application scope 1. A production vertical The electro-crystal method includes the following steps: providing a semiconductor substrate array region, a peripheral circuit region array region and a peripheral circuit region direct transistor memory array region memorizer unit, and a plurality of arrays including a plurality of peripheral mains, and Above each of the array oxide layer and a first pad of nitrogen, there is a second pad of oxygen sinking on the semiconductor substrate over the protective dielectric layer to cover the peripheral circuit area with the EA photoresist layer as the money cover. Protecting the dielectric layer, the first pad nitride layer in the storm domain; removing the EA photoresist layer; protecting the dielectric layer with the protecting dielectric layer, removing the vertical electro-crystallizing layer, A dielectric layer is deposited on the side of the recessed hole in the active area of the array. The overlying layer and the vertical transistor are recorded in the vertical transistor memory array in the vertical transistor memory crossing region. Note that there is a trench insulation between the peripheral circuit areas above each other, and there is a first gasification layer and an electrical layer of each of the surrounding active areas; an array (EA) photoresist layer, its crossing area; The first pad nitrogen depression hole in the second pad nitrogen area in the area of the transistor memory array area covered by the EA photoresist layer; the side wall; the protective dielectric field on the road area and the transition area, Page 16 200428594 6. The scope of the patent application fills the recessed hole at the same time; and a chemical mechanical polishing (CMP) process is performed, using the second silicon nitride layer as a polishing stop layer to polish the dielectric layer and the peripheral circuit area On the protective dielectric layer. 2. The method for fabricating a vertical transistor dynamic random access memory device as described in item 1 of the scope of patent application, wherein the method further includes the following steps after the chemical mechanical polishing (CMP) process: on the semiconductor substrate Depositing a silicon layer on the silicon layer; forming an etched peripheral region (ES) photoresist layer on the silicon layer, shielding the vertical transistor memory array region and a part of the transition region, and exposing the peripheral circuit region; using the ES The photoresist layer is an etching mask, and the stone layer is etched to define an array etching mask; and the ES photoresist layer is removed. 3. The method for manufacturing a vertical transistor dynamic random access memory device as described in item 2 of the patent application scope, wherein the method further includes the following steps after removing the ES photoresist layer: etching the mask with the array Protecting the vertical transistor memory array area, sequentially removing the second pad silicon nitride layer and the second pad oxide layer from the peripheral circuit area, exposing the substrate of the peripheral active area; performing an oxidation process, Forming a sacrificial oxide layer on the exposed substrate of the peripheral active area; and removing the array etching mask. Page 17 200428594 6. Scope of patent application 4. The method for making a vertical transistor dynamic random access memory device as described in item 2 of the patent application scope, wherein the silicon layer is polycrystalline silicon (ρ ο 1 ysi 1 ic ο η ). 5. The method for making a vertical transistor dynamic random access memory element according to item 2 of the scope of the patent application, wherein the stone layer is composed of amorphous silicon (amorphous silicon). 6. The method for manufacturing a vertical transistor dynamic random access memory device as described in the first item of the patent application scope, wherein the vertical transistor memory unit includes at least a capacitor electrode and Trench Top Oxide (ΤΤΟ) Layer and a vertical transistor polycrystalline silicon gate, wherein the τTO layer is used to insulate the capacitor electrode and the vertical transistor polycrystalline silicon gate. 7 · The method for manufacturing a vertical transistor dynamic random access memory device as described in item 1 of the scope of patent application, wherein before depositing the protective dielectric layer, hydrofluoric ethylene glycol (hydrofluoric ethylene glycol, (HFEG) etch away the second pad nitride layer with a predetermined thickness. 8. The method for manufacturing a vertical transistor dynamic random access memory element as described in item 7 of the scope of the patent application, wherein the predetermined thickness is about 50 angstroms to about 200 angstroms. ' 200428594 VI. Scope of patent application A method for manufacturing a vertical transistor dynamic random access memory device includes the following steps: A semiconductor substrate is provided, including a vertical transistor memory array region, a peripheral circuit region, and a vertical intervening region. The transition area between the transistor memory array area and the peripheral circuit area, where a plurality of array active areas are included in the vertical electrical body array area, and the peripheral circuit area includes a plurality of peripheral active areas. Ff, above the active area of the array, there is a first pad oxide layer and a first pad nitride layer, and above each peripheral active area, there is a second pad oxide layer and a second pad nitride layer Depositing a protective dielectric layer on a semiconductor substrate; forming an etched array photoresist layer on the protective dielectric layer, which covers the peripheral circuit area and a portion of the transition area; ^ the EA photoresist layer is neodymium Engraving, etch the compliance-resistant dielectric layer not covered by the EA photoresist layer to expose the vertical transistor memory array area The first pad nitride layer; removing the EA photoresist layer; removing the first pad nitride layer in the vertical transistor memory array area; depositing a dielectric layer covering the protective dielectric on the peripheral circuit area An electrical layer, the vertical transistor memory array region and the transition region, and simultaneously filling the recessed holes; performing a chemical mechanical polishing (CMP) process, using the second silicon nitride layer as a polishing stop layer to polish the dielectric On the electrical layer and the peripheral circuit area 200428594 6. The protection dielectric layer in the scope of patent application; depositing a silicon layer on the semiconductor substrate; forming an etched peripheral area (ES) photoresist layer on the silicon layer to shield the A vertical transistor memory array region and a part of the transition region, and exposing the peripheral circuit region; using the ES photoresist layer as an etching mask, etching the silicon layer, and defining an array etching mask; and removing the ES photoresist layer. 10. The method for manufacturing a vertical transistor dynamic random access memory device as described in item 9 of the scope of the patent application, wherein after removing the ES photoresist layer, the method further includes the following steps: etching the mask with the array The cover protects the vertical transistor memory array area, and sequentially removes the second pad silicon nitride layer and the second pad oxide layer from the peripheral circuit area, exposing the substrate of the peripheral active area; performing an oxidation process, Forming a sacrificial oxide layer on the exposed substrate of the peripheral active area; and removing the array money mask. Page 20