TWI236740B - Chip package structure - Google Patents

Abstract

A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip chip bonding to and electrically connects the carrier or other chips, and there is a flip chip bonding gap between the chip and the carrier or other chips. The heat sink is disposed over the top chip and the area of heat sink is bigger than chip. The encapsulating material layer is filled with the flip chip bonding gap, and covers the carrier and the heat sink. The part of surface of heat sink that far away the chip is exposed. The encapsulating material layer is composed of single encapsulating material. Otherwise, the gap between the chip and the heat sink is between 0.03 mm to 0.2 mm for example. The thermal conductivity of encapsulating material layer is more than 1.2 W/m.K for example. Selectively, there is a plurality of stand off components disposed on the heat sink.

Description

1236740 _ Case No. 92129521 __i Yue Ri Zheng Zheng _ V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a chip package structure, and in particular to a chip package structure Chip package structure. [Previous Technology] In today's highly informative society, the market for portable electric devices (Portable electric deviCe) continues to expand rapidly. Chip packaging technology also needs to cooperate with the trend of digitalization, networking, regional connection, and user-friendly use of electronic devices. In order to meet the above requirements, it is necessary to strengthen the various requirements of high-speed processing, multifunctionalization, integration, miniaturization, and low cost of electronic components. Therefore, the chip packaging technology is also moving toward miniaturization and high cost. Densified development. Among them, the Flip Chip bonding (F / C bonding) technology uses a bump to bond to a carrier, which greatly shortens the wiring length compared to the conventional wire bonding method. It helps to improve the signal transmission speed between the chip and the carrier board, so it has gradually become the mainstream of high-density packaging. However, an important issue that comes with high-density packaging technology is how to solve the heat dissipation problem of a chip packaging structure with a high degree of accumulation. FIG. 1 is a cross-sectional view of a conventional chip packaging structure using a wire connection type. Referring to FIG. 1, the wafer 20 has an active surface 22, and a plurality of solder pads (not shown) are further disposed on the active surface 22. The wafer 20 is arranged on the carrier plate 30 with the active surface 22 facing upward. A plurality of contacts (not shown) are arranged on the surface of the carrier plate 30. The two ends of the plurality of wires 24 are respectively connected to the pads of the chip 20 and the contacts of the carrier board 30, and are electrically connected to the chip 20 and the carrier board 30. Moreover, the surface of the carrier board 30 far from the wafer 20 is further provided with a plurality of arrays.

11844twf1.ptc Page 9 1236740 _ Case No. 92129521_ Year, month, day and five. Description of the invention (2) Solder ball (S ο 1 derba 1 1) 3 2, that is, the chip package structure 1 〇 uses a ball grid array 歹丨 J packaging (Ball Grid Array packaging, BG A packaging), so that the chip packaging structure can be electrically connected to a printed circuit board (PCB) (not shown) in the future. In addition, a packaging material layer 34 is disposed on the carrier board 30 and covers the chip 20 and the wires 24 to provide protection. However, this chip package structure has the disadvantage of poor heat dissipation. ^ Figure 2 shows a cross-sectional view of a chip package wafer structure using conventional flip-chip bonding technology. Referring to FIG. 2 ', the wafer 50 has an active surface 52, and a plurality of solder pads (not shown) are further disposed on the active surface 52. A plurality of contacts (not shown) are arranged on the surface of the carrier board 80. The plurality of bumps 60 are arranged on the main substrate 5: ": dry up" and the bumps 60 are electrically connected to the wafer 50 through the pads and contacts on the wafer 50. Carrier board 80. Among them, a plurality of solder balls 排列 arranged in an array are arranged on the surface of j far from the wafer 50. In order to protect the wafer 50 from being damaged by moisture, the bump 60 connecting the wafer 50 and the carrier plate 80 is protected from shearing. [Shear forcd is damaged, so it is more formed—the packaging material only 702, between the knife 50 and the carrier board 80. It is known to form a thin layer of the packaging material. The liquid packaging material with a lower viscosity is filled into the f, and the crystals between the hairs are used. Join the gap, and then harden the packaging material and the carrier board 80. As described above, the chip package structure 40 has better electrical performance than the first-degree-connected chip package structure 10, as shown in the figure. It is a trend to reduce the thickness of the chip packaging structure. However, the time required to pay the bonding gap is longer, which is not in line with the industry ^ material = fill in the chip and because the packaging material uses natural hair, Requirements for production capacity.

1236740 ---- Case No. 92129521 V. Explanation of the invention (3) The month and month are corrected, so the number of bumps 6 between the wafer 50 and the carrier plate 80 and the size of the gap between the chip and the flip-chip bonding will affect the The flow mode of the packaging material causes incomplete filling of the packaging material to form voids, which affects the reliability of the package. In addition, since the chip 50 is directly exposed to the outside, the characteristics of the chip are marked on the chip. When the surface is 50, or when the wafer packaging structure 40 is moved by vacuum suctioning the wafer 50, the wafer 50 is easily damaged. To improve this disadvantage, another conventional chip packaging structure has been created. Figures 3A and 3B are cross-sectional views of another conventional chip packaging structure using flip-chip bonding technology. Please refer to Figure 3 1 2 3 A 'Wafer package structure 4 2 is based on the wafer package structure 40 of Figure 2 and a top mold layer (Over mo 1 d) 7 2 is added to protect the wafer 50 during the process. Mark and move without damage. However, the shape is reduced, and the interface structure 42 is generated. Therefore, the root chip package, the chip package, and the chip 50 can be avoided. Due to the poor thermal performance of the chip 50, the production capacity is easy to be exposed in the package. There are 44 scatterings between the cover crystals and the peeling of the packaging material (D e 1 am reliability. According to the structure in Figure 3 A, 4 4 is also in the structure 4 4 due to the board 8 0 and filling to avoid the disadvantage of having a seal above the interface. The process time required to form the top mold layer 72 will relatively cause the phenomenon of the interface between the material layer 70 and the top mold layer 72, thereby reducing the improvement of the chip package structure 42, part 3B. The invention disclosed in the invention of JP3 9 2 6 9 8 is that a person forms a packaging material layer 74 to cover the shortcomings of the peeling of the packaging material from the wafer 50 and the carrier plate 80. However, this design still contains material layers 7 4, resulting in a chip package structure

Page 11 1236740 _Case No. 92129521_Year Month Date__ V. Description of the invention (4) Therefore, the object of the present invention is to provide a chip package structure suitable for using a chip with excellent electrical performance in the chip package structure. The die-bonding technology joins the wafers and provides excellent heat dissipation of the chip package structure. Based on the above objectives, the present invention proposes a chip packaging structure, which is mainly composed of a carrier board, at least one wafer, a heat sink, a packaging material layer, and a plurality of thickness-off components. Wherein, the wafer has an active surface, and a plurality of bumps are arranged on the active surface. The chip is flip-chip bonded to the carrier with the active surface facing the carrier, and is electrically connected to the carrier. The heat sink is arranged on the wafer, and the area of the heat sink is larger than the area of the wafer. The packaging material layer is filled between the chip and the carrier board, and covers the heat sink and the carrier board, and the packaging material layer is formed of a single packaging material. These thickness retaining members are arranged on the heat sink. In addition, the chip packaging structure of this embodiment further includes, for example, a thermal conducting adhesive layer. The height of the thickness holder is equal to the thickness of the packaging material layer above the heat sink. The thermally conductive adhesive layer is, for example, disposed between the wafer and the heat sink. Based on the above objectives, the present invention further proposes a chip packaging structure, which is mainly composed of a carrier board, a chip set, a heat sink, a packaging material layer, and a plurality of thickness retaining members. The chip set is arranged on the carrier board and electrically connected to the carrier board. The chip set is mainly composed of a plurality of wafers, and at least one of the wafers is bonded to a carrier board or other wafers, and a flip-chip bonding gap is maintained. The heat sink is arranged on the chipset, and the area of the heat sink is larger than the area of the chipset. The packaging material layer is filled in the flip-chip bonding gap and covers the heat sink and the carrier board. The packaging material layer is formed of a single packaging material. These thickness retaining members are arranged on the heat sink.

11844twf1.ptc Page 12 1236740 _Case No. 92129521_ Year and month Amendment_ V. Description of the invention (5) In addition, the chip package structure of this embodiment further includes, for example, a thermally conductive adhesive layer. The height of the thickness holder is equal to the thickness of the packaging material layer above the heat sink. The thermally conductive adhesive layer is, for example, disposed between the uppermost wafer of the chipset and the heat sink. In addition, the wafer set of this embodiment is mainly composed of a first wafer and a second wafer, for example. The first chip has a first active surface, and the first chip is disposed on the carrier board with the first active surface facing away from the carrier board. The second wafer has a second active surface, and a plurality of bumps are disposed on the second active surface. The second chip is flip-chip bonded to the first chip with the second active surface facing the first chip, and is electrically connected to the first chip. The bumps maintain the flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the first chip and the carrier board, respectively. In addition, the chip set of this embodiment may be mainly composed of a first chip, a second chip, and a third chip. The first wafer has a first active surface, and a plurality of first bumps are disposed on the first active surface. The first chip is flip-chip bonded to the carrier with the first active surface facing the carrier, and is electrically connected to the carrier. The second wafer has a second active surface, and the second wafer is disposed on the first wafer with the second active surface facing away from the first wafer. The third wafer has a third active surface, and a plurality of second bumps are disposed on the third active surface. The third wafer is flip-chip bonded to the second wafer with the third active surface facing the second wafer, and is electrically connected to the second wafer. The first bump and the second bump maintain a flip-chip bonding gap. In addition, the chipset further includes a plurality of wires, for example. The two ends of each wire are electrically connected to the second chip and the carrier board, respectively.

11844twf1.ptc Page 13 1236740

Threshold value In the two embodiments of the chip packaging structure described above, the packaging material layer has: 彳, f coefficient, for example, greater than κ 2 watts / meter-hungry temperature (w / m · κ) 'its material two Γ: series resin . The material of the heat sink is, for example, metal. In the chip package structure, the pinch includes a plurality of arrayed solder balls and at least one passive component. It is also arranged on the surface of a carrier board without a wafer, for example. Passive element ^ = is configured on the carrier board and is electrically connected to the carrier board. The carrier board is, for example, a watch substrate or a lead frame. According to the above-mentioned chip packaging structure according to the present invention, since H i is provided with a heat sink having a larger area than the chip, it can provide a good heat dissipation path for μ and mounting structure, thereby improving the chip. Reliability of package structure. Fart ^ to make the above and other objects, features, and advantages of the present invention more clear ^ ^ / Dong's preferred embodiments will be described below, and in conjunction with the accompanying drawings, detailed explanation is as follows. [Embodiment] Figure ^ is a cross-sectional view of a chip package structure according to a first preferred embodiment of the present invention. Please refer to Figure 4, chip package structure! 〇 〇 is mainly composed of a carrier board i 8 〇, at least one wafer i 5 〇, a heat sink i 4 〇 and a packaging material layer 170. Among them, the carrier board 丨 8 is a packaging substrate such as an organic substrate, a flexible substrate, a flexible substrate, or a flip chip quad flat non-leaded packaging (F / C QFN packaging). ), Etc. Lead frames used in packaging processes. The upper and lower surfaces of the carrier plate 180 have, for example, a plurality of contacts (not shown). The chip 150 has an active surface 15 2, and the chip 150 is an active watch.

11844twfl.ptc Page 14 1236740 _Case No. 92129521_Year_Month__ V. Description of the invention (7) The surface 1 5 2 faces the carrier board 1 0 0 and the flip chip is bonded to the upper surface of the carrier board 180. For example, a plurality of solder pads (not shown) are arranged on the active surface of the wafer 150, and a plurality of bumps 160 are disposed on the solder pads on the active surface 15 of the wafer 150. The wafer 150 is electrically connected to the carrier board 180 through the bump 160 on the solder pad. That is, the wafer package structure 100 of this embodiment includes at least one wafer 150, and the wafer 150 is bonded to the upper surface of the carrier board 180 using a flip-chip bonding technology. However, in addition to the chip 150, in this embodiment, other chips or other components (such as resistors, capacitors, and other passive components) may be provided on the carrier board 180 in the package structure 100. The heat sink 140 is disposed on the chip 150, and the area of the heat sink 140 is larger than the area of the chip 150, so it has better heat dissipation efficiency. In addition, the heat sink 140 is not limited to being integrally formed, and may also be composed of multiple independent heat sinks. This design facilitates the flexible use of a large-area chip package structure. In addition, the packaging material layer 170 is filled between the chip 150 and the carrier board 180 and covers the heat sink 140 and the carrier board 180. Moreover, the packaging material layer 170 is formed of a single packaging material. The material of the packaging material layer 170 is, for example, a resin. At the same time, in order to ensure the heat dissipation effect, the thermal conductivity of the packaging material layer 170 is preferably greater than 1.2 Watt / meter-Kelvin temperature. In addition, the thickness of the packaging material layer 170 on the heat sink 140 is preferably 0.3 mm or less, and more preferably 0.1 mm or less. The material of the heat sink 1 40 is, for example, metal. In the present invention, the heat sink 1440 made of metal, which has a much larger area than the wafer 150, is mainly used to diffuse the heat generated by the wafer 150 in a wide range, so the one with the best thermal conductivity is the best. Generally, for example, copper plates, nameplates, iron plates, nickel plates or their surfaces are used.

11844twf1.ptc Page 15 1236740 --- Case number 92129521 _ year month day ____ V. Description of the invention (8) Those who mine gold. In addition, the heat sink must be able to withstand the pressure when forming the packaging process, so it is desirable to have a strength that is not easily bent. Although it varies according to the type of metal, but the heat sink 丨 4 〇 For example, it is better to have a thickness of 0.1 mm or more 'In addition, in order to increase the tightness of the interface between the packaging material layer 170 and the heat sink 140, the heat sink 1 For example, the surface of 40 may be subjected to a gold plating treatment, or the surface of the heat sink 1 40 may be subjected to a physical treatment such as surface chemical treatment or surface roughening. In addition, in order to have proper bonding between the heat sink i 4 〇 and the chip 150, for example, a heat conductive adhesive layer 145 is further disposed on the heat sink 140 and the chip 150.

As shown in the enlarged section). Thermally conductive adhesive layer 145 is generally made of silicon thermal conductive materials, silver poor, solder paste and other thermally conductive materials. Solder balls two to 95 are placed on the lower surface of the carrier plate 180: 1. . / + The 'solder ball 19o' is used for example after the configuration 100, for example, and printed circuit extension 3 f19 is used to provide a chip package structure 195, for example, it is used for the purpose of being connected to the carrier board 18o. Passive element connection. On the top surface, and electrically connected to the carrier plate 180, it is worth noting that the present invention is not structured. The conventional chip packaging structure diagram of the present day and month is a one-time forming of the chip packaging layer. 2. Interface peeling occurs on the packaging material of each part. Interface of knife-shaped packaging material

A cross-sectional view of the chip package structure of the embodiment. The chip package structure of the second preferred second preferred embodiment proposed by X Ming is the same as that of the first preferred embodiment, and the rest is the same as the first preferred embodiment, mainly because a plurality of crystals σ are added here. More details. please

1236740 fix

j # 129129521 V. Description of the invention (9) Same reference to FIG. 5 and FIG. 6 'wafer package structure 2 ^ n 28. --- Day-to-day film group ㈤,-2 fins: 2 to 5 * * Carrier board. Among them, the wafer group 2 50 is mainly composed of a plurality of crystals = material layers 2 70. At least one wafer is bonded to one of the wafers by flip-chip bonding technology. Therefore, at least _fee / inverse 280 or other crystals exist in the chipset 250, and the flip-chip bonding gap 256 is formed by using the flip-chip bonding, = bonding gap 256 '. The heat sink 240 is a protrusion disposed on the chipset 25 //, and is filled in the flip-chip bonding gap 256 'and is covered on 240. "And again, the thermal conductivity of the packaging material layer 270 is, for example, preferably greater than 12 watts / meter-Kelvin temperature. In order to have a proper bonding between the heat sink 2 4 0 and the chip 2 5 0, for example, more A thermally conductive adhesive layer 2 4 5 is arranged between the heat sink 24 0 and the uppermost chip of the chip 250. The thermally conductive adhesive layer 2 4 5 generally uses silicon, silver paste, solder paste and other materials with good thermal conductivity. Please refer to FIG. 5. The chipset 250 of the preferred embodiment is mainly composed of a first wafer 250a and a second wafer 250b. The arrangement relationship of each component is as follows. The first wafer 2 50a has a first active surface 252a, and the first wafer 250a is disposed on the carrier board 2 80 with the first active surface 252a facing upward. The second wafer 250b has a second active surface 252b, and the second active A plurality of bumps 260 are arranged on the surface 252b. The second wafer 2 5 0 b is bonded to the first wafer 2 5 0 a with the second active surface 2 5 2 b facing the first wafer 2 5 0 a, and Is electrically connected to the first chip 2 5 0 a. The bump 2 6 0 maintains the flip-chip bonding gap 2 5 6. In addition, the chipset 250 includes, for example, a plurality of wires 2 5 4b °, for example, a plurality of contacts (not shown) are arranged on the surface of the carrier plate 2 8 0, and the first chip 2 50 0a

11844twfl.ptc Page 17 1236740 _Case No. 92129521_ Year and Month ___ V. Description of the invention (10) The first active surface 252a and the second active surface 252b of the second wafer 250b are provided with, for example, a plurality of solder pads (not shown in the figure) Show). The bump 2 60 of the second wafer 2 5 0 b maintains the flip-chip bonding gap 2 5 6 between the first wafer 2 50 a and the second wafer 2 5 0 b. In other words, the second wafer 250b is bonded to the first active surface 252a of the first wafer 250a by a flip-chip bonding technique. The two ends of each wire 254b are, for example, electrically connected to the contacts of the soldering pad of the first chip 250a and the carrier 2800 respectively. Referring to FIG. 6, the chip set 250 of the preferred embodiment is composed of a first chip 250a, a second chip 250b, and a third chip 250c, for example. The chip set 2 50 further includes, for example, a plurality of wires 2 54b. Among them, the arrangement relationship of each element is as follows. The first wafer 250a is disposed on the carrier board 2800, and the first wafer 250a has a first active surface 252a, and a plurality of first bumps 260a are disposed on the first active surface 252a. The first chip 250a is bonded to the carrier plate 280 with the first active surface 2 5 2a facing the carrier plate 2 80, and is electrically connected to the carrier plate 280. The second wafer 250b has a second active surface 252b, and the second active surface 252b faces away from the first wafer 250a. In addition, a plurality of wires 2 5 4b are connected to the pads on the second active surface 2 5 2 b of the second chip 2 5 0 b and the contacts of the carrier board 2 0 0 to electrically connect the second Wafer 250b and carrier plate 2 80. The third wafer 250c has a third active surface 252c, and a plurality of second bumps 2 60b are disposed on the third active surface 252c. The third wafer 250c is flip-chip bonded to the second wafer 250b with the third active surface 252c facing the second wafer 250b, and is electrically connected to the second wafer 250b. The first bump 2 6 0 a and the second bump 2 6 Ob maintain the flip-chip bonding gap 2 5 6. In other words, the third wafer 250 c is bonded to the second active surface 252b of the second wafer 250b by flip-chip bonding technology, and the first wafer 250a is

11844twfl.ptc Page 18 1236740 _Case No. 92129521_Year_Day_Charm_ V. Description of the invention (11) The crystal bonding technology is bonded to the surface of the carrier plate 2 5 0 b. In the second preferred embodiment proposed in the present invention, the number of wafers is mainly increased compared with the first preferred embodiment, and at the same time, it is not limited that all wafers are bonded to the carrier board by flip-chip bonding technology. The most important feature of the present invention is that at least one wafer is included in the chip packaging structure, and the wafer is bonded to a carrier board or other wafers using a flip-chip bonding technology. Moreover, a heat sink is arranged above the chip. Both the heat sink and the carrier board and the flip-chip bonding gap have a packaging material layer. The packaging material layer is formed with the same packaging material at one time. As long as any embodiment conforming to the above-mentioned main features should fall within the scope of protection of the present invention. FIG. 7A is a cross-sectional view of a finished product after the chip packaging process is completed according to the preferred embodiment of the present invention. FIG. 7B is a cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention. The finished product is cut after the chip packaging process is completed. Please refer to FIG. 7A and FIG. 7B together. In order to meet the mass production requirements, the packaging process of the preferred embodiment after forming the packaging material layer 170, for example, cutting along the cutting line L (Dicing) to A plurality of chip package structures 100 are formed. Among them, each chip package structure 100 includes at least one chip 150. In addition, although the packaging material layer 170 shown in Figure 7A is connected as a whole, the process mold can also be adjusted to form multiple independent packaging material layers 170, that is, in the cutting line portion No packaging material layer is formed to reduce the time required for subsequent cutting. In addition, in the chip packaging structure according to the above two preferred embodiments of the present invention, for example, it has a design for maintaining the thickness of the packaging material layer. FIG. 8 shows a wafer according to a preferred embodiment of the present invention.

11844twf1.ptc Page 19 1236740

, 12129521, description of the invention (12) package structure plus thick family name Du package structure 102 is mainly based on the axis, the chip plus a plurality of thickness holders 142. Douzhizhi said that the chip packaging structure 100 is further added to the heat sink "0, noon and 2; the second and sixth degrees of the 9 degree holder I42, for example, is the configuration piece 1 40 above the seal belly as much as the holder 1 42 of For example, the height is equal to -i. There is no encapsulating material layer above. 17 Covering the thickness, that is, the thickness holder. 42 The thickness holder is not placed. 4 2 The heatable sheet 1 40 is bent. The thickness depends on the type of material. The thickness of the heat sink 140 can be thinner. Its thickness. If not. Not 4 meters but: as much as £. Tend to use a degree of bending of more than ° .05 mm = easy to cause heat dissipation. The weight of the sheet 140 itself is deformed due to wrinkles. The purpose of setting the thickness retaining member i 4 2 is to limit the thickness of the material layer 170 mainly on the stable thermal sheet 140. However, if the thickness is equal to the size There is no special material or method that will cause the chip package structure 102 to be defective due to the pressure of the sealing area being too large and the surface of the device exceeding the device surface. 142 The trust of the matching Jinxiang chip # 装 结构 102 Degree. As for the thickness, the needle can be placed several times on the heat sink 1 40. The resin is connected to the non-heating sheet U0 for centralized processing and cutting. The method is three-dimensional: 2 3 and 5 9 Β The edge of the picture is shown as the shape of the chip packaging structure shown in FIG. 8; Fig. 9A, the thickness retaining member 14 2 is a ball diagram, for example, there are eight places around the chip package structure 102. Please refer to the 9th side of the structure 10 "edge = example", which is set on each of the chip packages. Give Du a /, everywhere. The shape or arrangement of the degree holder 1 4 2 is only the thickness of the packaging material layer 1 7 on the surface of a piece of packaging structure 1 02,

1236740 said correction __ 一 ^ -92129521- 5. Description of the invention (丨 3) _ and not because the heat sink i 4 〇 when packaged is not limited to Figures 9A and 与. 7 can be changed, and in addition, the thickness of the holder package 丨 42 shown in the chip package structure i 〇 〇, also ^: not limited to the application of the chip package structure shown in Figure 4 〇 2 Or two f, for example, in the package structure of FIG. 5 and the sixth chip. It is worth noting that, in the manufacturing process according to the present chip package structure, the reduced-pressure transfer injection molding method of the preferred embodiment is outlined. The method of reducing the material layer is, for example, placing a wafer structure into a mold, and the main mold forming method refers to a method in which the package to be introduced is introduced into the hot-melt and melted material, and the i 2a is added to the mold. General transfer injection mold opening; ^ processing to harden the resin is a flip-chip bonding gap or wafer and heat radiation ^ 7 is not decompressed, which is likely to cause a decompression state in j mold ;. The packing material is insufficiently filled, and the best decompression state is the best: the column top: = the chip top view of the preferred embodiment of the packaging structure. Please refer to Figure 10, move ': 22 to 20 into the packaging material layer, the required package type is placed and suitable, > equipment (not shown) can be made according to the 31 and the lower mold 32 () ^ 'Fork tool 30 () is mainly from the upper mold, in order to achieve a more effective car two two soil dies' 1 () and the lower mold 32 ○ mold 31. The lower mold 3 2 0 spot mold and the ϋ ′ 5 edge step are the first to touch the upper mold. Next, the vacuum rubber seal ring 3 3 0 of the vacuum pump, vacuum pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump, pump pump. Then, put the gelatin cake 11844twfl.ptc Page 21 1236740 Case No. 92129521 V. Description of the invention (14) Complete the decompression transfer and control the molding temperature. The molding temperature is too high (tablet) (not shown) in the injection pipe 3 5 0 Inside, and maintain for 1 to 5 seconds to improve the real work in the South space, while raising the temperature in the mold to make the cake into a hot-melt packaging material. Finally, the upper mold 3 丨 〇 and the lower mold are completely tightly attached to each other, and at the same time, the plunger 3 6 0 is pulled up to introduce the sealing material in a molten state to fill the mold cavity 3 4 0 Inner large injection molding. Among them, the decompression transfer injection molding is in progress; it is better to be at least 5 degrees Celsius below the melting point of the bump 160, and the wind is warm and wide. At this time, the wafer is relatively thin compared to the packaging material in the molten state during molding ί ϋ T For the bonding of the wafer 150 to the carrier plate at 18 °, it is easy to see that the wafer is likely to occur during the decompression transfer injection molding process, and that the wafer structure according to the preferred embodiment of the present invention is underway. In the chip packaging process, the j = said that the package junction is smaller than 0.5 of the flip-chip bonding gap. The maximum particle size of the largest particle size f is greater than the flip-chip bonding; gap: 〇 :: : 'Making j' packing gap or filling material between the wafer and the hot plate is relatively ^ yet, the filling between the joints will cause incomplete filling. And. A is difficult, and even the friction of the wafer surface will cause the wafer ^ ^ 1 When and when the packaging material is filled. Guide added to the packaging material layer: Reliable ^ state = oxygen ^ except for the heat dissipation vermiculite, emulsified aluminum silicon nitride, boron nitride, nitrogen Aluminium alloys are used in the province of Germany, and, " Silicon wafer surface, so the added: "ϊ High, too easy to hurt ΐ 1/5-fold gap flip chip bonding. …, It is best not to take a large particle size for the filler ^ 11844twfl.ptc Page 22 1236740 No. 1 92〗 2 Contamination ?. 1 Modification V. Description of the invention (15) In the invention, the packaging material layer is formed. The chip packaging process of the preferred embodiment is packaged with a liquid packaging material, and another method is a decompression state and a lower-temperature process at normal temperature. At this time, packaging; Niu f pressurized, heat-hardened two-stage packaging material. If the production capacity is taken into account, it is set to print using dispensing but called "vacuum printing machine": = is ideal, and it can also be used commercially. Ί ί ΐ When feeding, the decompression state during the f-packing process is filled with 2 mm-mercury and the charge is less than 20 mm. Hg 2 may be filled with packaging materials. It is usually 2 to 5 cm. After the load of the material, the pressure of the hardened material is determined to be hardened + square centimeters of pressure. As for the heating, according to the sealing process ^ ^, for this chip packaging process, the hardening G =: 3, eight is best to be Celsius Above 4 ° and below hardening temperature: For shirts, heat for more than 3 minutes, so that the filling of the packaging material can be promoted before. < The drilling degree of Coco rises, and the sealing material used in the process should preferably have a liquid seal particle size of less than 1/3 times the flip-chip bonding gap and account for more than 1/3 of Codan's filling and filling material. When the particle exceeds the weight percentage, the blade is more likely to be blocked due to the large volume than the gap filled with the sealing material. The filling of the flip chip is incomplete. Addition to the packaging material layer & the silicon dioxide in the molten state used for the packaging material, if it is a charge ^ In addition to the conventional use of crystalline silica, alumina, silicon nitride, boron nitride Alas, it is thermally conductive, and it can also be a material with better conductivity. Heat transfer such as gasification junction In addition, in order to reduce the stress in the chip packaging structure, a warpage phenomenon occurs, and the liquid seal used / avoids the elastic dispersion of the carrier board, if the weight percentage of the elastic dispersion, / 枓 contains # 3 U Μ is better, and

11844twf1.ptc Page 23 1236740 _Case No. 92129521_Year Month__ V. Description of the invention (16) The maximum particle size of the elastic dispersion is preferably less than 1/3 times the flip-chip bonding gap. (Inventive application example) [Example 1] The area size is 8 mm X 8 mm, with 800 eutectic tin-lead bumps (melting point 18.3 degrees Celsius, pitch 0.52 mm), thickness 0 · A 3 mm wafer is bonded in a matrix arrangement on a packaging substrate (FR-5) with an area of 35 mm X 35 mm and a thickness of 0.4 mm. In order to allow the current to flow evenly, a stub wiring is added to the surface of the wafer. The flip-chip bonding gap is 50 to 75 microns. The heat sink is made of a copper plate of 20 mm x 20 mm and a thickness of 0.15 mm, and is fixed on the packaging substrate with a commercially available thermally conductive adhesive. In order to improve the bonding strength, the upper and lower surfaces of the copper plate are preferably roughened. Decompression transfer injection molding is performed using a transfer injection molding device with a decompression function. The vacuum in the mold cavity is about 1 mm-Hg. The packaging material is CV8 7 0 0 F2 made by Matsushita Electric Works (the maximum particle diameter of the filler is 20 microns, the average particle diameter is 5 microns, the filler material is all molten silicon, and the thermal conductivity is 0.9 W / m-Kay. Temperature), the thickness of the packaging material layer is 0.65 mm, and the molding area of the package is 29 mm x 29 mm. The encapsulation process is performed at 160 degrees Celsius and a pressure of 70 kg / cm 2 for 2 minutes, and then a post-curing process of 175 degrees Celsius and 4 hours can obtain a device with a structure as shown in FIG. 4. From the cross-section of the device, the thickness of the packaging material layer on the heat sink is 0.12 to 0.15 mm. [Example 2] Except that the package thickness of Example 1 was changed to 0.6 mm, everything else was the same, and the device as shown in Figure 4 was completed. From the cross-section of the device, the thickness of the packaging material layer on the heat sink is 0.08 to 0.11 mm.

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V. Description of the invention (17) ^ Example 3] Except for copper plates with a thickness of 0.22 meters, and other aluminum plates with a thickness of 1 meter instead of the thickness of the example. 丨 5. Cutting from the section of the device will become as in Section 4. Figure device. Degrees, 0.06 ~ 〇 · 〇〇 mm. See 'The thickness of the encapsulation material layer on the heat sink [Example 4] Manufactured on a steel plate with a thickness of 0.1 mm thick 9B as shown in the figure ^ 15 mm high, as in Example 2 0. 15 mm thick The steel plate is replaced with an adhesive at the four corners instead of being installed. The others are the same, as shown in Figure 8. The cut from the cross section of the device is 0.15 ~ 0.16 mm. Look at the thickness of the encapsulation material layer on the heat sink. [Example 5] In addition to replacing the stone eve of Example 1, the other 50% is replaced with alumina (and the material is replaced by 50% of the molten particle size of 1.5 microns). The other filler materials have a maximum particle size of 5 microns, and the heat transfer of the packaging material is used on average to obtain the structure of the device shown in Figure 4. [Example 6] The number in Example 2 was divided into 5 · W / m—Kelvin temperature. Silicon, the other 50% is replaced with nitride, and the mounting material is replaced with 50% of the molten particle size of 2 microns), other (the maximum particle size of the filling material is 7 microns, the average heat transfer of the packaging material ^ system]: 〖 ': The device is structured as shown in Figure 4. Use [Example 7] to remove the 9 W / m-Kelvin temperature of Example 4. The silicon, the other 50% is replaced with ^ chemical materials, and replaced with 50%. The diameter of the melted state is 1.5 microns. The maximum particle size of the outer charge material is 5 microns. The average field size is the same. The structure obtained is shown in Figure 12. Let the thermal conductivity of the ancestor and material be 5 W / m-Kelvin temperature. ^ Yes, Example 1] Using the wafer, packaging substrate and commercially available liquid L underfill material (Panasonic Electric Co., Ltd. cv 5 丨 8 3 F) in Example 1, and using a dispensing device to encapsulate the flip-chip bonding gap . Filler material obtained after hardening under certain conditions

Page 25 1236740 _Case No. 92129521_ Year Month Amendment_ V. Description of the invention (18) The chip package structure is shown in Figure 2. [Comparative Example 2] In Comparative Example 1, the wafer package structure of the structure shown in Figure 2, the mold and packaging material as in Example 2 were used and covered, and the resulting wafer package structure is shown in Figure 3A. [Comparative Example 3] The device of Example 2 is the same except that no heat sink is used. The resulting chip package structure is shown in Figure 3B. The test results of the chip packaging structures of the above examples and comparative examples are shown in Fig. 11. The chip packaging process of the preferred embodiment of the present invention uses the technology disclosed in Japanese Patent J P 3 9 2 6 98 in 2001. However, the present invention optimizes the package size and provides a heat sink so that the chip package structure has the best package reliability and heat dissipation. In summary, according to the chip package structure of the preferred embodiment of the present invention, because it contains a heat sink and the chip is covered with the same material at one time, compared with the conventional chip package structure, it has lower warpage and reliability High and highly heat dissipation effect. If a high thermal conductivity packaging material is used, the heat dissipation effect is better. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

11844twfl.ptc Page 26 1236740 _Case No. 92129521_ Year Month Amendment _ Brief Description of Drawings Figure 1 is a cross-sectional view of a conventional chip packaging structure using a wire connection type. FIG. 2 is a cross-sectional view of a chip package structure using a conventional flip-chip bonding technology. Figures 3A and 3B are cross-sectional views of another conventional chip packaging structure using flip-chip bonding technology. FIG. 4 is a cross-sectional view of a chip package structure according to a first preferred embodiment of the present invention. 5 and 6 are cross-sectional views of a chip package structure according to a second preferred embodiment of the present invention. FIG. 7A is a cross-sectional view of a finished product after the chip packaging process is completed according to the preferred embodiment of the present invention. FIG. 7B is a cross-sectional view of a chip packaging structure according to a preferred embodiment of the present invention. The finished product is cut after the chip packaging process is completed. FIG. 8 is a cross-sectional view of a chip package structure and a thickness retaining member according to a preferred embodiment of the present invention. Figures 9A and 9B are three-dimensional schematic diagrams of the chip package structure shown in Figure 8. FIG. 10 is a cross-sectional view of a chip packaging structure forming a packaging material layer in a decompression transfer injection molding mold according to a preferred embodiment of the present invention. Figure 11 shows the test results of the chip package structure according to the preferred embodiment of the present invention and the comparative example.

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Page 28 1236740 _Case No. 92129521_ Year, month, and day correction diagram brief description 2 0, 50: wafer 22, 52: active surface 2 4: wire 3 0, 8 0: carrier 3 2, 9 0: solder ball 3 4, 7 0, 7 4: encapsulation material layer 60: bump 7 2: top mold layer 1 0 0, 10, 2 0 0: chip package structure 1 4 0, 2 4 0: heat sink

1 4 2: Thickness holder 1 4 5, 2 4 5: Thermally conductive adhesive layer 1 5 0: Wafer 1 52: Active surface 1 6 0, 2 6 0: Bump 1 7 0, 2 7 0: Packaging material layer 1 8 0, 2 8 0: Carrier board 1 0 0, 2 9 0: Solder ball 195, 295: Passive element 250a

2 5 0 b: second wafer 2 5 0 c: third wafer 252a: first active surface 252b · second active surface

11844twf1.ptc Page 29 1236740 _Case No. 92129521_Year Month_Revision of the diagram 252c: the third active surface 2 5 4 b: the wire 2 5 6: the flip chip bonding gap 2 6 0 a · the first convex Block 260b: second bump 3 0 0: mold

3 1 0: Upper mold 3 2 0: Lower mold 3 3 0: Vacuum rubber seal ring 3 4 0: Mold cavity 3 5 0: Injection line 3 6 0: Plunger 3 7 0: Vacuum line L: Cutting line

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Claims (1)

1236740 _ Case No. 92129521_ 年月 日 __ VI. Scope of patent application 1. A chip package structure includes at least: a carrier board; a chip with an active surface, the active surface is provided with a plurality of bumps, the The chip is bonded to the carrier board with the active surface facing the carrier board, and is electrically connected to the carrier board; a heat sink is arranged on the chip, and the area of the heat sink is larger than the area of the chip A packaging material layer filled between the chip and the carrier board and covering the heat sink and the carrier board, the packaging material layer is formed of a single packaging material; and a plurality of thickness retaining members are disposed on the heat sink a. 2. The chip package structure described in item 1 of the scope of patent application, wherein the height of the thickness holders is equal to the thickness of the packaging material layer above the heat sink. 3. The chip package structure described in item 1 of the patent application scope further includes a thermally conductive adhesive layer disposed between the chip and the heat sink. 4. The chip packaging structure described in item 1 of the scope of patent application, wherein the thermal conductivity of the packaging material layer is greater than 1.2 Watts / meter-Kelvin temperature. 5. The chip packaging structure described in item 1 of the scope of patent application, wherein the material of the packaging material layer includes resin. 6. The chip package structure according to item 1 of the scope of patent application, wherein the material of the heat sink comprises metal. 7. The chip package structure described in item 1 of the scope of patent application, further comprising a plurality of solder balls arranged in an array, arranged on a table where the carrier board is far from the chip 11844twfl.ptc Page 31 1236740 _Case No. 92129521_ Year Month Amendment_ Sixth, the scope of patent application. 8. The chip package structure described in item 1 of the scope of patent application, further comprising at least one passive component disposed on the carrier board and electrically connected to the carrier board. 9. The chip packaging structure according to item 1 of the scope of patent application, wherein the carrier board includes one of a packaging substrate and a lead frame. 1 0. A chip packaging structure including at least: a carrier board; a chip set disposed on the carrier board and electrically connected to the carrier board, the chip set includes a plurality of wafers, and at least one of the wafers The flip chip is bonded to one of the carrier board and the wafers, and a flip chip bonding gap is maintained; a heat sink is arranged on the chip group, and the area of the heat sink is larger than the area of the chip group; A packaging material layer is filled in the flip-chip bonding gap and covers the heat sink and the carrier board. The packaging material layer is formed of a single packaging material; and a plurality of thickness retaining members are disposed on the heat sink. 1 1. The chip packaging structure described in item 10 of the scope of the patent application, wherein the height of the thickness holders is equal to the thickness of the packaging material layer above the heat sink. 12. The chip package structure according to item 10 of the scope of patent application, further comprising a thermally conductive adhesive layer disposed between the top surface of the chipset and the heat sink. 11844twfl.ptc Page 32 1236740 _Case No. 92129521_ Year Month Amendment_ VI. Patent Application Range 1 3. The chip package structure described in item 10 of the patent application range, wherein the thermal conductivity of the packaging material layer is greater than 1 . 2 Watt / meter-Kelvin. 14. The chip packaging structure according to item 10 of the scope of patent application, wherein the chip set includes at least: a first chip having a first active surface, and the first chip is backed by the first active surface And is disposed on the carrier board toward the carrier board; and a second wafer having a second active surface on which a plurality of bumps are disposed, the second wafer is oriented toward the second active surface The first wafer is flip-chip bonded to the first wafer and is electrically connected to the first wafer, wherein the bumps maintain the flip-chip bonding gap. 15. The chip package structure according to item 14 of the scope of patent application, wherein the chip set further includes a plurality of wires, and both ends of the wires are electrically connected to the second chip and the carrier board, respectively. 16. The chip packaging structure according to item 10 of the scope of patent application, wherein the chip set includes at least: a first chip having a first active surface, and the first active surface is provided with a plurality of first protrusions. Block, the first chip is bonded to the carrier board with the first active surface facing the carrier board, and is electrically connected to the carrier board; a second chip having a second active surface, the first chip The two wafers are disposed on the first wafer with the second active surface facing away from the first wafer; and a third wafer having a third active surface and the third active surface 11844twf1.ptc Page 33 1236740 _Case No. 92129521_ Year Month Amendment_ 6. There are a plurality of second bumps on the scope of the patent application. The third chip is covered with the third active surface facing the second chip. The die is bonded on the second wafer and is electrically connected to the second wafer, wherein the first bumps and the second bumps maintain the flip-chip bonding gap. 17. The chip package structure according to item 16 of the scope of patent application, wherein the chip set further includes a plurality of wires, and both ends of the wires are electrically connected to the first chip and the carrier board, respectively. 1 8. The chip packaging structure as described in item 10 of the scope of patent application, wherein the material of the packaging material layer includes resin. 1 9. The chip package structure described in item 10 of the scope of patent application, wherein the material of the heat sink includes metal. 20. The chip packaging structure described in item 10 of the scope of patent application, further comprising a plurality of arrayed solder balls arranged on the surface of the carrier board away from the chipset. 2 1 · The chip package structure according to item 10 of the scope of patent application, further comprising at least one passive component, which is arranged on the carrier board and is electrically connected to the carrier board. 2 2. The chip packaging structure according to item 10 of the scope of patent application, wherein the carrier board includes one of a packaging substrate and a lead frame. 11844twfl.ptc Page 34