CN111384000A - Chip package - Google Patents

Abstract

The invention relates to the technical field of component packaging, and in particular to a chip package, which is a square flat leadless package, comprising: a pad, including a heat dissipation pad and electrode contact pads arranged around the heat dissipation pad; a chip, It is attached to the upper surface of the heat dissipation pad and is electrically connected to the electrode contact pad; the package body covers the sealing pad and the chip, and the lower surface of the pad is exposed to the surface of the package body; The thermal deformation is generated, which is arranged on the package body, and the thermal deformation member and the pad are respectively arranged on both sides of the chip. The thermal deformation component has a stress correction effect on the thermal deformation of the device: when heated, the thermal deformation component and the heat dissipation pad are arranged up and down, so that the stress is offset or partially offset, and the deformation is eliminated or reduced. The device can avoid the deformation caused by heat in the SMT assembly process or long-term work, protect the solder joints, and prolong the application life of the device; it does not occupy the layout area on the board, and does not increase the SMT process, which has obvious advantages.

Description

Chip packaging

technical field

The invention relates to the technical field of component packaging, in particular to a chip package.

Background technique

Electronic products have always been evolving toward smaller size, lighter mass, faster speed, higher frequency, lower cost, and higher reliability. QFN devices are widely used in high-speed or microwave designs of 5G products due to their thinner thickness, leadless design, excellent heat dissipation performance, very low impedance and self-inductance.

QFN is a leadless package, which is square or rectangular. There is a large-area exposed pad in the center of the bottom of the package, which has a thermal conductivity. This pad is part of the internal thick copper frame structure, and also has excellent heat dissipation performance of QFN. s reason. However, this kind of thick copper frame structure will undergo dynamic thermal deformation under the influence of ambient temperature or power changes during SMT welding or long-term operation, resulting in large tensile stress on the solder joints, which will seriously deteriorate the life of the solder joints. , affecting the application of high-reliability products, including communication products.

When solving this problem in the industry, there are generally two solutions: one is to increase the four-corner package pads, or NC (non-connect) pads; the other is to dispense glue around the SMT welding. Solution 1 is simple and effective, and does not increase the existing production process, but now QFN is also developing towards high density, and many QFN devices have no space to increase pads or NC pads at the four corners. The second solution is to fix the device and the PCB relatively. Even if stress is generated, it is difficult to act on the solder joints. Therefore, it is very effective to solve the problem of QFN solder joints breaking and breaking. However, the dispensing process increases the PCBA processing process, and the QFN repair is difficult.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, in order to provide a QFN package structure that can correct thermal deformation, so as to reduce the tensile stress generated in the QFN package during welding or operation, and reduce device failure, the present application provides the following technical solutions.

Embodiments of the present application provide a chip package.

The dielectric phase shifter provided according to the embodiments of the present application includes:

a pad, which includes a heat dissipation pad and an electrode contact pad disposed around the heat dissipation pad;

a chip attached to the upper surface of the heat dissipation pad and electrically connected to the electrode contact pad;

a package body, which encapsulates the pad and the chip, and the lower surface of the pad is exposed to the surface of the package body;

The thermal deformation member, which generates thermal deformation when heated, is disposed on the package body, and the thermal deformation member and the pad are respectively disposed on both sides of the chip.

According to the QFN package provided by the embodiment of the present application, the thermal deformation member provided on the package body has a stress correction effect on the thermal deformation of the device: when the device is heated, the chip and the heat dissipation pad generate stress due to the mismatch of CTE, and the thermal deformation member also Stress is generated due to thermal deformation, and the thermal deformation member on the top and the heat dissipation pad on the bottom are arranged up and down, so that the stress can be offset or partially offset, and the deformation can be eliminated or reduced. With this stress-corrected structural design, the device can avoid the deformation caused by heat during the SMT assembly process or long-term operation, protect the solder joints, and prolong the service life of the device; this structural optimization is compared with the existing technical solutions. , does not occupy the layout area on the board, does not increase the SMT process, has obvious advantages.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. In other words, on the premise of no creative labor, other drawings can also be obtained from these drawings.

1 is a schematic structural diagram of a QFN package in the prior art;

2 is a schematic cross-sectional structure diagram of a chip package provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of another chip package provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of still another chip package provided by an embodiment of the present application; and

FIG. 5 is a reference diagram for size calculation of a structure of a chip package provided by an embodiment of the present application.

In the picture:

10, pad; 11, heat dissipation pad; 12, electrode contact pad; 20, chip; 21, connecting wire; 30, package body; 40, thermal deformation member.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only The embodiments are part of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the scope of protection of the present application.

It should be noted that the terms "first", "second", etc. in the description and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the application described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

In this application, the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", etc. is based on the orientation or position shown in the drawings relation. These terms are primarily used to better describe the present application and its embodiments, and are not intended to limit the fact that the indicated device, element, or component must have a particular orientation, or be constructed and operated in a particular orientation.

In addition, some of the above-mentioned terms may be used to express other meanings besides orientation or positional relationship. For example, the term "on" may also be used to express a certain attachment or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present application can be understood according to specific situations.

Furthermore, the terms "arranged", "connected", "fixed" should be construed broadly. For example, "connection" may be a fixed connection, a detachable connection, or a unitary construction; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediary, or two devices, elements or Internal connectivity between components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict.

QFN, whose English full name is Quad Flat No-lead Package, is a square flat no-lead package. QFN devices are thin in thickness, leadless design, have excellent heat dissipation performance, and have very low impedance and self-inductance. In 5G products high-speed or microwave design for numerous applications.

The structure of the QFN package in the prior art is shown in Figure 1, which is generally square or rectangular. There is a large-area exposed heat dissipation pad in the center of the bottom of the QFN package, which has a thermal conductivity. This heat dissipation pad is an internal thick copper frame structure. It is also part of the reason why QFN has excellent thermal performance. Electrode contact pads are arranged around the heat dissipation pads, chips are connected to the upper surfaces of the heat dissipation pads, and the outside of the QFN package is a package body that encapsulates and seals the above structures. This kind of QFN package with thick copper frame structure will undergo dynamic thermal deformation under the influence of environmental temperature or power changes during SMT welding or long-term operation, resulting in large tensile stress on the solder joints, which will seriously deteriorate the solder joints lifespan.

In order to solve the above problems, as shown in FIG. 2 , in addition to the pad 10 , the chip 20 and the package body 30 , a thermal deformation member 40 is also provided in the QFN package structure. The thermal deformation member 40 is thermally deformed when heated, and is disposed on the package body 30 , and the thermal deformation member 40 and the pads 10 are respectively disposed on two sides of the chip 20 . The thermal deformation member 10 provided on the package body 30 has a stress correction effect on the thermal deformation of the device: when the device is heated, the chip 20 and the heat dissipation pad 11 generate stress due to the mismatch of CTE, and the thermal deformation member 40 also generates stress due to thermal deformation. , the thermal deformation member 40 on the top and the heat dissipation pad 11 on the bottom are arranged up and down, so that the stress can be offset or partially offset, and the deformation can be eliminated or reduced.

With this stress-corrected structural design, the device can avoid the deformation caused by heat during the SMT assembly process or long-term work, protect the solder joints, and prolong the service life of the device; this structural optimization does not occupy the layout area on the board, does not Increasing the SMT process has obvious advantages.

In the chip package, there are various options for disposing the thermal deformation member 40 . For example, the thermal deformation member 40 can be completely encapsulated in the package body 30 , can be embedded in the top surface of the package body 30 , or can be connected with the top surface of the package body 30 . Face fit connection.

In the chip package, the material of the thermal deformation member 40 can be selected in various ways, preferably pure metal or alloy, such as red copper or copper alloy. In addition, the material of the thermal deformation member 40 can be the same as the material of the heat dissipation pad 11, for example, the material is selected as red copper, which can ensure that the expansion coefficient of the heat dissipation pad 11 and the thermal deformation member 40 are consistent, and the size of the two is the same or similar. , a substantially equivalent amount of deformation can be generated; the material of the thermal deformation member 40 can also be different from the material of the heat dissipation pad 11 , and the thermal deformation matching that of the heat dissipation pad 11 can be achieved by adjusting the size of the thermal deformation member 40 . The thickness of the thermal deformation member 40 is generally greater than or equal to 0.1 mm, and its size is less than or equal to the size of the top of the device. Specifically, the size and thickness of the thermal deformation member 40 need to be calculated according to the strength, coefficient of thermal expansion (CTE) of the thermal deformation member 40 and the thermal expansion coefficient, thickness and strength of the heat dissipation pad 11 to ensure that the strength of the thermal deformation member 40 can correct the bottom The stress generated by the thermal deformation of the heat dissipation pad 11 .

An optional dimension calculation method of the thermal deformation member 40 is illustrated below with reference to FIG. 5 .

In order to realize the relief of thermal stress, the strength of the thermal deformation member 40 needs to be greater than that of the pad 10 . The size of the thermal deformation member 40 is mainly based on the strength and thermal expansion coefficient of the material, as shown in FIG.

The strength B ₁ of the thermally deformable member 40 is calculated according to its short side section, namely:

B ₁ =W ₁ ×H ₁ ×σ ₁ ;

The strength B2 of the pad ₁₀ is calculated according to the short side section of the QFN package, namely:

B ₂ =(W ₂ -1.4)×H ₂ ×σ ₂ ;

When the strength B ₁ of the thermally deformable member 40 is greater than the strength of the QFN terminal frame, B ₁ ≥B ₂ .

The above σ1 is the thermal expansion coefficient _of the thermally deformable member 40; _σ2 is the thermal expansion coefficient of the pad ₁₀ ; W1 is the short side length _of the thermally deformable member 40; W2 is the short side length of the pad ₁₀ ; -1.4 is to empirically process the effective length of the pad 10. This is because the pad 10 is generally not a strict quadrilateral, but has some gaps and protrusions, thereby forming the pad 10. In order to facilitate the calculation, empirical processing is performed on its effective length. . Of course, the empirical processing value of 1.4 can be adjusted according to the actual situation.

The general pad 10-bit thick copper frame pad is made of copper, that is, σ ₂ is 16.7×10 ^-6 /°C. Assuming that the thickness of the thick copper frame pad is 0.25mm, according to B ₁ ≥B ₂ , there are

W ₁ ×H ₁ ×σ ₁ ≥(W ₂ -1.4)×0.25×16.7×10 ^-6 ,

That is, H ₁ ≧[(W ₂ −1.4)×0.25×16.7×10 ⁻⁶ ]/(W ₁ ×σ ₁ ).

The calculation process enumerated above is only an exemplary illustration of an optional calculation method, in which the shape of the thermal deformation member is equivalent to a quadrilateral structure for calculation. It should be noted that in this application, the thermal deformation member 40 has a The size does not need to be exactly the same as that of the heat dissipation pad 11 , as long as the thermal deformation member 40 exists, the effect of stress relief will be achieved. The size of the thermally deformable member 40 is generally selected through engineering tests, and the thickness and size are selected in consideration of cost and effect.

In the chip package, the chip 20 and the electrode contact pads 12 are electrically connected through connecting wires 21, wherein the connecting wires 21 include but are not limited to gold wires and aluminum wires.

In the chip package, the chip 20 is connected to the heat dissipation pad 11 through a conductive and heat-conductive layer, wherein the material of the conductive and heat-conductive layer includes but is not limited to conductive silver paste.

In the chip package, the material of the package body 30 is plastic or ceramic. The package body 30 encapsulates the pads 10 , the chips 30 , and the connecting wires 21 together, and the package shape is generally square.

In the chip package, the pads 10 include electrode contact pads 12 around the periphery and heat dissipation pads 11 at the bottom. The heat dissipation pads 11 are also called thick copper frame structures inside the package body 30 . The materials of the electrode contact pads 12 and the heat dissipation pads 11 can use the common materials of the existing pads, such as copper; the surface treatment of the electrode contact pads 12 and the bottom heat dissipation pads 11 can use the common surface treatment of the existing pads, Such as silver plated or nickel plated palladium gold.

In chip packaging, the chip 20 includes, but is not limited to, existing silicon wafers.

The present application will be exemplified below with reference to Figures 3-4 and in conjunction with the embodiments.

Example 1

As shown in FIG. 3 , a chip package is provided, including a pad 10 , a chip 20 , a package body 30 and a thermal deformation member 40 , and the pad 10 includes a heat dissipation pad 11 and electrode contacts arranged around the heat dissipation pad 11 . The point pad 12; the chip 20 is attached to the upper surface of the heat dissipation pad 11, and is electrically connected with the electrode contact pad 12; the package body 30 encapsulates the sealing pad 10 and the chip 20, and the lower surface of the pad 10 is exposed to the package The surface of the body 30 ; the thermal deformation member 40 will generate thermal deformation when heated, and is disposed on the package body 30 , and the thermal deformation member 40 and the pad 10 are respectively disposed on both sides of the chip 20 .

In the present embodiment, as shown in FIG. 3 , the thermal deformation member 40 is completely encapsulated inside the package body 30 . The chip 20 is selected as a silicon wafer, which is connected to the heat dissipation pad 11 at the bottom through silver paste to realize grounding heat dissipation. The silicon wafer is connected to the electrode contact pads 12 by means of gold wires to realize electrical connection. The package body 30 is made of epoxy resin plastic material. On the top of the device, a thermal deformation member 40 is encapsulated inside the device. The size of the thermal deformation member 40 is larger than the size of the bottom heat dissipation pad 11, and only slightly smaller than the peripheral size of the device package 30. The thickness is 0.2mm, and the material is welded with the heat dissipation at the bottom. The disk 11 is made of the same material and is made of red copper.

The QFN package of Example 1 was tested, and the QFN package was normally assembled by lead-free soldering process. After the assembly, a temperature cycle test was performed, and the test was conducted according to the IPC 9701 standard. The device passed the 500-cycle test and met the engineering application life requirements.

Example 2

As shown in FIG. 4 , a chip package is shown, including a pad 10 , a chip 20 , a package body 30 and a thermal deformation member 40 , and the pad 10 includes a heat dissipation pad 11 and electrode contacts arranged around the heat dissipation pad 11 . The point pad 12; the chip 20 is attached to the upper surface of the heat dissipation pad 11, and is electrically connected with the electrode contact pad 12; the package body 30 encapsulates the sealing pad 10 and the chip 20, and the lower surface of the pad 10 is exposed to the package The surface of the body 30 ; the thermal deformation member 40 will generate thermal deformation when heated, and is disposed on the package body 30 , and the thermal deformation member 40 and the pad 10 are respectively disposed on both sides of the chip 20 .

In this embodiment, as shown in FIG. 4 , the thermal deformation member 40 of this embodiment is provided outside the package body 30 . The chip 20 is selected as a silicon wafer, which is connected to the heat dissipation pad 11 at the bottom through silver paste to realize grounding heat dissipation. The silicon wafer is connected to the electrode contact pad 12 by means of aluminum wire to realize electrical connection. The package body 30 is made of epoxy resin plastic packaging material. There is a thermal deformation member 40 on the top of the device, the size of the thermal deformation member 40 is the same as the peripheral size of the device, the thickness is 0.25mm, and the material is the same as that of the heat dissipation pad 11 at the bottom, which is made of copper alloy material.

The QFN package of Example 2 was tested, and the QFN package was normally assembled by lead-free soldering process. After the assembly, a temperature cycle test was performed. The temperature cycle condition was -45°C to 125°C. The device passed the 500-cycle test and reached the engineering application life. Require.

Some embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

The above are only specific embodiments of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims (10)

1. A chip package, which is a square flat leadless package, comprising: a pad (10) comprising a heat dissipation pad (11) and an electrode contact pad (12) arranged around the heat dissipation pad (11); a chip (20) attached to the upper surface of the heat dissipation pad (11) and electrically connected to the electrode contact pad (12); a package body (30), encapsulating the bonding pad (10) and the chip (20), the lower surface of the bonding pad (10) being exposed to the surface of the package body (30); It is characterized in that it further comprises: a thermal deformation member (40), which is thermally deformed when heated, is disposed on the package body (30), and the thermal deformation member (40) is connected to the pad (10). ) are respectively arranged on both sides of the chip (20). 2 . The chip package according to claim 1 , wherein the thermal deformation member ( 40 ) is completely encapsulated in the package body ( 30 ). 3 . 3. The chip package according to claim 1, wherein the thermal deformation member (40) is embedded in the top surface of the package body (30). 4 . The chip package according to claim 1 , wherein the thermal deformation member ( 40 ) is attached and connected to the top surface of the package body ( 30 ). 5 . 5. The chip package according to claim 1, wherein the material of the thermal deformation member (40) is the same as the material of the heat dissipation pad (11). 6. The chip package according to claim 1, wherein the material of the thermal deformation member (40) is pure metal or alloy. 7. The chip package according to claim 6, wherein the material of the thermal deformation member (40) is red copper or copper alloy. 8 . The chip package according to claim 1 , wherein the chip ( 20 ) and the electrode contact pad ( 12 ) are electrically connected by connecting wires ( 21 ). 9 . 9 . The chip package according to claim 1 , wherein the chip ( 20 ) is connected to the heat dissipation pad ( 11 ) through a conductive and heat-conducting layer. 10 . 10. The chip package according to claim 1, wherein the material of the package body (30) is plastic or ceramic.

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