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TWI233265B - Phase locked loop circuit - Google Patents

Phase locked loop circuit Download PDF

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Publication number
TWI233265B
TWI233265B TW093117681A TW93117681A TWI233265B TW I233265 B TWI233265 B TW I233265B TW 093117681 A TW093117681 A TW 093117681A TW 93117681 A TW93117681 A TW 93117681A TW I233265 B TWI233265 B TW I233265B
Authority
TW
Taiwan
Prior art keywords
coupled
input terminal
phase
locked loop
loop circuit
Prior art date
Application number
TW093117681A
Other languages
English (en)
Other versions
TW200601703A (en
Inventor
Yi-Bin Hsieh
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW093117681A priority Critical patent/TWI233265B/zh
Priority to US11/086,541 priority patent/US20050280453A1/en
Application granted granted Critical
Publication of TWI233265B publication Critical patent/TWI233265B/zh
Publication of TW200601703A publication Critical patent/TW200601703A/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

1233265
五、發明說明（1) 發明所屬之技術領域·· 本發明係有關於一種鎖 應用於收發器或CD/DVD中的雜^電路，特別有關於一種 先前技術： T的鎖相迴路電路。 第1圖係顯示—傳統的鎖相 10、-相位頻率偵測器i i 电：、：除頻4 13、-壓控震盪器14及一除 5 : :路濾波器 η ΓΟ ^ ^ 牙了貝斋1 5所組成，其中，R 1、门 · ^路濾波态1 3，由於迴路的頻寬（l〇〇p bandndth)需要遠小於參考頻率Fref的頻 迴路穩定，所以Π會非常大，其大小約數百持 相對的其所佔面積亦相當大。其巾’迴路濾波器之轉換函
Vc： SC2(S + CT+C2 SC2(S + 數（1)為 — 為充電幫浦1 2 0之操作電流 為解決上述問題，如第2圖所示之另一傳統鎖相迴路 1’提供雙充電幫浦120、121來減少其電容之面積，其中充 電幫浦1 20之操作電流為11，充電幫浦1 2 1之操作電流為 12 ’其中Ι1 = Β*Ι2，且Β〉1，第2圖之迴路濾波器之^換函 /収+. 1 C2 - — 1 R\C2
，若C2〈〈 Cl ; I - n{S + 'BR\C2/
Vc SC2(S + 1 RIC2 SC2(S + 1 R1C2 數（2)為一 ，若C2、乂 B C 3。由轉換函數（2 )可知’利用此鎖相迴路電路，可使電
五、發明說明（2) C3為ί =積ί小為第1圖之電容C 1的1/B倍，但是由於電容 電衮汙口 Ϊ容，無法使用單位面積電容較大的場效電晶體 ( :、此使用單位面積電容較小的多晶矽對多晶矽
Mm/電容”。固咸::屬對金屬(MetaH〇，tal，· 13〇以&一積減少仍有限，且其需要—個放大器 積，也增加電路增加電路設計的複雜度以及面 發明内容： 有鑑於此，本發明之主要目的 面積以及降2電路雜訊之鎖相迴路電：供-車又小電路 係包’/發n供—種鎖相迴路電路，# 端，包括··一第—；容入端及-第二輪入’、 -端輕接該第—輪入入端上;-電脏， 一屮源，器，具有-輸入端：接二輪入 輸出端耦接於該電阻之另一 一# 、〜一輸入端， 於該第-輸入端，以輸出-第電：弟：充電幫浦，粞接 浦，耦接於該第二輸入端，以輸二，以一及一第二充電幫 一電流係為該第二電流之Β倍，’苴中二電流’·其中該第 為了讓本發明之上述和1他、 。 明顯易懂，下文特舉一較::Α目的、特徵、和優點能 詳細說明如下： ‘佳霄施例，並配合所附圖示 實施方式： 弟3圖係顯示本發明雜 “鎖相迴路電路-較佳實施例之f 1233265 五、發明說明（3) j示意圖’此鎖相迴路電路2包括一迴路濾波器2〇、一第 充電幫浦21、一第二充電幫浦22、一壓控震盪器23、一 除頻器24、一相位頻率偵測器25及一除頻器26。 迴路濾波斋20具有一第一輸入端2〇〇及一第二輸入端 2〇1，包括：一第一電容C2，耦接於該第_輸入端2〇〇上；一 電阻R1，一端耦接該第一輸入端200; 一第二 耦 於該第二輸入端2〇1; —源極隨柄器（source谷 輕接 = ll〇Wer)Ml，例如為一PM〇s電晶體，亦可使用NM〇s電晶 -，其汲極係耦接至一固定電壓源（例如：接地gnd)，具 二閘極當作輸入端連接於該第二輸入端201，一源極當作 端耦接於該電阻。之另一端；一電流源耦接至該源 極k耦器Ml的輸出端。第一充電幫浦浐 以輸出一第—電流IP1;第二充電幫接#2二接輪 輸入端201，以輸出一第二電流其t，該第 一〜lIP1係為該第二電流IP2之β倍，B〉1。壓栌震盪哭 迴路濾波器2〇以接收由迴路濾波器;0輸“ 訊唬並根據其電壓值轉換對應之頻率。 的 端以除頻，並輸出4二:震盈器23的輸出 輸入端分別麵接至之測器25 ’具兩 以接收一頻率為Fref之/ς之輸出端及另一除頻器26上 味 之祝號及頻率為Fvco_f b之迴授訊 二：兩輸出端搞接該第一充電幫浦21以及該第二充電幫浦 藉由本實施例之趣路濾波器2，假設IP1侧P2，B〉
1233265 五、發明說明（4) 1，源極隨耦器Ml之電壓放大倍數為理想值工，則 ·+^χ-
Vc^IPl • · · ·算式（1) …·算式（2 ) .· 丄 Vci ur^vc, 算式（2)代入算式（1) 算式（3) 12 VC1代入算式（3 ) VC: SBCa
Wa) 7λ(^ι+ 1 +现tc2 λ + SR^C^ SBC, \^SRxC2 _In^{S+BR^ _ In{S + lK^ 柳+忐）邮+ 士— …·轉換函數（3 ) 由轉移函數（3 )與轉換函數（1 )比較可知，本韻^ ^ u BC4 = C1 ， C4 = C1/B，使電容C4的面積減少A习习A X明可 的B倍，且電容C4為接地電容，可使用單位而接“ 卞丨见IS?積車父大的揚 效電晶體電容（MOS CAP)，另外，由於只# ^ 從用一源極隨如 器，所以電路雜訊較小，並可降低相位雜訊（pha 思祸 noise)及時間抖動（timing j itter)的影響，另外 電壓VC1由臨界電壓Vth開始充電，所以可加、♦ ’由於 思鎖相迴路到
0608-A40241twf(nl);VIT04-0101;MIKE6277.ptd 第8頁 1233265 五、發明說明（5) 達預定頻率所需要的時間。 雖然本發明已以較佳實施例揭露如上’然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。
0608-A40241twf(nl);VIT04-0101;MIKE6277.ptd 第9頁 1233265 圖式簡單說明 第2 i :::: I統鎖相迴路電路之電路示A 第3圖係顯Γ f 一傳統鎖相迴路電路之雷枚、忍圖； 示意圖、”不本發明鎖相迴路電路路不意圖； 佳實施例之電路 相關符號說明: 相位頻率偵測器1 1 充電幫浦1 2 迴路濾波器丨3 堡控震盪器14 除頻器1 5 充電幫浦120、121 鎖相迴路1， 電容C3 鎖相迴路電路2 迴路瀘波器20 第一充電幫浦21 第二充電幫浦22 壓控震盪器23 除頻器24 才目位頻率偵測器2 5 除頻器2 6 第一輸入端2〇〇 弟一輸入端201 〇6〇8-A40241twf(nl)；viT04-01〇l；MlKE6277.ptd 第10貢 1233265 圖式簡單說明 電阻R1 第二電容C4 源極隨耦器Μ1 1Ι1ΙΗ1 第11頁 0608-A40241twf(nl);VIT04-0101;MIKE6277.ptd

Claims (1)

  1. ^33265
    鎖相迴路電路 、 ^ ^ 5 P ii · ，包 迴路濾波器，且有_ 一· α 括： ’、有—弟一輸入端及一第二輸入知 衲钱於該第 雷：端轉接該第-輸入端； 1極隨ί哭耦i:該第二輪入端;及 ^^^^ ^ /、有一輸入端連接於該第二輸入端， 翰=糕耦接於該電阻之另一端； 電流第以及乞電幫浦，耦接於該第一輸入端，以輸出一第 第 電流； 充電幫浦，耦接於該第二輸入端，以輸出一第 2、中該=一電流係為該第二電流之β倍，其中β〉1。 括一申明專利範圍第1項所述之鎖相迴路電路，更包 “流源輕接至該源極隨耦器的輸出端。 3」如申明專利範圍第1項所述之鎖相迴路電路，更包 一壓控震盪器，耦接至該迴路濾波器之輸出端。 4 · 士申明專利範圍第3項所述之鎖相迴路電路，更包 一第一除頻器，耦接至該壓控震盪器的輪出 一迴授信號。 山％ M f刖出 5.如申請專利範圍第4項所述之鎖相迴路電路， 括一相位偵測器，該相位偵測器之兩輸入端係八匕 一該第二除頻器之輸出端及一第二除頻器上，: 至 分別與該第一充電幫浦及該第二充電幫浦連接。⑴端則
    0608-A40241twf(nl);VIT04-0l0i；MIKE6277.ptd
    第12頁
    1233265 六、申請專利範圍 6.如申請專利範圍第1項所述之鎖相迴路電路，其中 該源極隨耦器具有一汲極連接至一固定電壓源，一閘極作 為該輸入端耦接該第二充電幫浦之輸出端，及一源極連接 至該電阻之另一端。
    0608-A40241twf(nl);VIT04-0101;MIKE6277.ptd 第13頁
TW093117681A 2004-06-18 2004-06-18 Phase locked loop circuit TWI233265B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW093117681A TWI233265B (en) 2004-06-18 2004-06-18 Phase locked loop circuit
US11/086,541 US20050280453A1 (en) 2004-06-18 2005-03-22 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093117681A TWI233265B (en) 2004-06-18 2004-06-18 Phase locked loop circuit

Publications (2)

Publication Number Publication Date
TWI233265B true TWI233265B (en) 2005-05-21
TW200601703A TW200601703A (en) 2006-01-01

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