TWI232591B - Self-aligned Schottky barrier contact structure and its manufacturing methods - Google Patents

Abstract

A self-aligned Schottky barrier contact structure of the present invention comprises a diffusion guard ring being defined by a first sidewall dielectric spacer and a Schottky contact metal layer being formed on an exposed semiconductor surface surrounded by a second sidewall dielectric spacer, in which the first sidewall dielectric spacer being made of silicon dioxide is formed over an inner sidewall formed by a dielectric layer over a patterned field oxide layer and a thermal silicon dioxide layer on a portion of the diffusion guard ring or is formed over an inner sidewall formed by a composite dielectric layer over a patterned field oxide layer and on a portion of the diffusion guard ring. The self-aligned Schottky barrier contact structure of the present invention needs only two masking photoresist steps.

Description

1232591 V. Description of the invention (1) [Technical field to which the invention belongs] A Schottky barrier diode is connected to an auto-aligned Schottky barrier. The present invention relates to a Schottky screen and a manufacturing method thereof, particularly to The structure and its manufacturing method are ^. Before the technique, the gold device touches the current carrying number of the whole base and the multi-frequency special Gao Xiao. One by one is recognized or contains a public body cover and rarely is a two-to-up crossover plate speed. The basic half is a special one for Xiao Yi and Yu Yiyin because of 10% of the physical layer and poles, and the main body} one of them (IR is, the current working electricity is leaked to the pole inverse two, obstacles) B screen (V-base voltage special electricity Xiao Kuai has always been used in the reverse of the collection: extremely uniform (IF second question> ^ (rate question electric FV voltage ^ 6- ^ 9 to 'II and Figure 1 shows the other of the prior art A brief cross-sectional view of a Schottky barrier contact structure, in which a P + diffusion protection ring 05 is formed through a diffusion window (not shown) formed between two forming field oxide layers 102a. Within a designed surface portion of an η- / n + epitaxial semiconductor substrate 101/100; a metal silicide layer 103 is formed on the P + diffusion as a Schottky contact metal layer system. Guard ring 105 and an exposed n — / n + epitaxy surrounded by a shaped step boron glass (BSG) layer 106a On the surface of the semiconductor substrate 101/100; a forming metal layer 10 "is formed on a part of the forming field oxide layer 10a, and the forming step <

1232591 V. Description of the invention (2) 1 0 6 a and the metal silicide layer 10 3; and a back metal layer (not shown) is formed on the η + semiconductor substrate 1 as an ohmic contact metal layer system. 0 0 above. Therefore, a main object of the present invention is to provide a Schottky barrier contact structure and a method of manufacturing the same to improve the disadvantages of the prior art. It can be clearly seen here that the fabrication of the Schottky barrier diode shown in Figure 1 requires three mask photoresist steps, one of which is the first mask photoresist step to define the ρ + diffusion protection ring. A diffusion window; a second mask photoresist step is used to remove the forming field oxide layer 1 0 2 a (not shown) and a part of the step boro glass layer 10 6 a to form the The metal silicide layer 103 and a third mask photoresist step are used to form the shaped metal layer 104a. Obviously, a wet etching solution (such as buffered hydrofluoric acid) is used to remove the forming field oxide layer 10 2 a and the step boron glass layer 106 (not shown) at the same time without serious undercutting. (Undercut) is quite difficult. Similarly, an anisotropic dry etching method is used to remove the forming field oxide layer 1 2 a and the step boro glass layer 1 0 6 a simultaneously without generating the p + guard ring and the exposed semiconductor substrate 1 0 1 The severe groove engraving of / 100 is not easy. Therefore, the width of the diffusion window using the wet etching method must be kept larger (10 micrometers or more) and the junction depth of the P + diffusion guard ring 105 using the non-isotropic dry etching method must be kept deep. (Greater than or equal to 2 microns). Therefore, the size of the Schottky barrier diode cell will become larger and its stray series resistance will increase to 0 for a specified breakdown voltage. Therefore, a main object of the present invention is to provide an automatic alignment Tactical barrier contact structure has a minimized diffusion guard ring area and a

1232591 V. Description of the invention (3) Maximize the cell area. Another object of the present invention is to provide an auto-aligned Schottky barrier contact structure that can be fabricated with a minimum number of mask photoresist steps. A further object of the present invention is to provide an auto-aligned Schottky barrier contact structure with better metal step coverage and a smaller series resistance at a known breakdown voltage. SUMMARY OF THE INVENTION The present invention discloses an automatic alignment Schottky barrier contact structure and a manufacturing method thereof. The self-aligning Schottky barrier contact structure includes at least a semiconductor substrate of a first conductivity type having a lightly doped epitaxial semiconductor layer formed on a highly doped semiconductor substrate; a diffusion protection of a second conductivity type It is formed by an ion implanted window defined by a first side wall dielectric pad, and a Schottky contact metal layer is formed on at least one exposed surrounded by a second side wall dielectric pad. Semiconductor surface. The above-mentioned first side wall dielectric hafnium layer is formed by a dielectric layer formed on a forming field oxide layer and a thermal silicon dioxide layer on a part of the surface of the diffusion protection ring or a composite dielectric. The electric layer is placed on an outer side wall formed on a forming field oxide layer and a part of the surface of the diffusion protection ring. The above-mentioned ion implanted window is formed on a mask dielectric layer surrounded by the dielectric layer or the composite dielectric layer and the first side wall dielectric pad layer. The second side wall dielectric pad is made of silicon nitride or oxygen.

1232591 V. Description of the invention (4) The silicon nitride composition is formed on the inner side wall of the forming field oxide layer and is placed on the thermal silicon dioxide layer or the second side wall. The electrical pad is composed of silicon dioxide and is formed on a part of the surface of the dielectric layer or the composite dielectric layer. The above-mentioned diffusion guard ring includes at least a moderately doped diffusion guard ring or a highly doped diffusion guard ring. The above-mentioned self-aligned Schottky barrier contact structure can be manufactured by two mask photoresist steps, and the width of the diffusion protection ring can be controlled to be small by the first side wall dielectric cushion layer. [Embodiment] Referring now to FIGS. 2A to 2G, the process steps for manufacturing a first type of self-aligning Schottky barrier contact structure of the present invention and a brief cross-sectional view thereof are disclosed. FIG. 2A shows that a field oxide layer 2 0 2 is formed on a semiconductor substrate 201/200 of a first conductivity type, wherein the semiconductor substrate 2 0 0/2 0 1 includes at least one lightly doped epitaxy. The semiconductor layer 201 is placed on a highly doped semiconductor substrate 2000. The field oxide layer 202 is a thermal dioxide layer grown by a water vapor environment or a wet oxygen environment, and a doped silicon dioxide layer is deposited by a chemical vapor deposition (CVD) method. And a CVD dioxide layer is formed on a thermal dioxide layer, and its thickness is between 60 Angstroms and 100 Angstroms. The dopant concentration within the lightly doped epitaxial silicon layer 2 0 1 is between 1 014 / cm 3 and 1 017 / cm 3

Page 10 1232591 V. Description of the invention (5) The thickness of the epitaxial layer is between 3 microns and 35 microns, and it is determined according to the specified breakdown voltage. The doped concentration of the highly doped semiconductor substrate 2000 is between 1019 / cm 3 and 5 × 102. / Cubic centimeter, and its thickness is determined according to the size of the wafer. The epitaxial semiconductor substrate 20 1/2 0 0 can be replaced by other semiconductor materials, such as gallium arsenide (GaAs) or silicon carbide (SiC), and the field oxide layer 202 can be deposited by a CVD method. A layer of silicon dioxide. FIG. 2B shows that a first mask photoresist (PR1) step (not shown) is performed to define an active region (AA), and the field oxide layer 2 0 2 in the active region uses wet etching. Removal is performed by a method or an anisotropic dry etching method; then, the first mask photoresist (PR1) is removed. '' Figure 2C shows that a thermal silicon dioxide layer 203 is formed on an exposed semiconductor substrate 201/200, and then a dielectric layer 204 is formed on the f-shaped field oxide layer 〇2a and the thermal Above the silicon dioxide layer 203; then, 204, the first side stepped on the dielectric hafnium layer (SP a C 6 Γ) 2 〇 $ a is formed on an inner edge side of the dielectric layer A portion of the surface thickness of the dielectric layer 204 above the wall. The thermal silicon dioxide layer 203 is formed by dry oxygen oxidation and the silicon is between 100 angstroms and 500 angstroms. The dielectric layer 204 is a nitrogen layer, and is deposited using a low pressure vapor deposition method (LPCVD) with a thickness of between about 100% and 500 angstroms. The first side wall dielectric pad layer 20 5 a is deposited by two low-pressure chemical vapor phase (LPCVD) deposition methods, and the second one is deposited on the structure: (layer) (not shown) on the formed structure. One of the surface figures I and E emulsifies a thickness of the silicon layer 205. — ,,,, and not a cover dielectric layer 2 0 6 a is filled with the first side wall dielectric

Page 11 1232591 V. Description of the invention (6) A gap surrounded by the electric cushion layer 205a. The mask dielectric layer 206a is a photoresist layer 206 (not shown), and a photoresist layer 206 is coated on the semiconductor substrate 201/200 and then the photoresist layer 206 is left to a The predetermined 'degrees. It is worth noting here that other fluid materials can be used to replace the photoresist layer 206a, such as (polyimide). FIG. 2E shows that the first side stepping dielectric pad layer 2 0 5 a is removed using buffered hydrofluoric acid; then, ion implantation is performed in an automatic alignment manner and a second conductivity type 1 is doped. Impurities are placed across the dielectric layer 204 on the thermal silicon dioxide layer 203 on a surface portion of the semiconductor substrate 201/200 to form an ion implanted layer shape 207.

Fig. 1F shows that the mask dielectric layer 2 06 a is removed, and then an impurity drive-in is performed to form a diffusion protection ring 2 07 a. It is worth noting here = Yes' The diffusion guard ring 207a can be moderately doped or hea vily doped and its junction depth is between 0.3 microns and 3 microns . Less Figure 2 / shows that the dielectric layer 2 is removed using hot phosphoric acid;

The rear side of a second side wall dielectric cushion layer 2 0a is formed on an inner edge side wall of the molding field oxide layer 20 2 a and is placed on a part of the thermal silicon dioxide layer 20. Over the surface; the thermal silicon dioxide layer surrounded by the second side wall dielectric pad layer 2 0 & is removed by wet etching; a Schottky contact metal layer 2 0 9 a Is formed on an exposed semiconductor surface surrounded by the second side wall dielectric pad layer 208a; then, a forming metal layer 210a is formed on the forming field oxide layer 202a, the second side Side wall

Page 12 1232591 V. Description of the invention (7) The electric pad layer 208a and the Schottky contact metal layer 209a are formed through a second mask photoresist (PR3) step (not shown). The second side wall dielectric pad layer 208a is composed of nitride nitride or oxynitride. A silicon nitride or silicon oxynitride (not shown) is first deposited on a structured surface. Then, a thickness of the stacked silicon nitride or silicon oxynitride layer 2 0 8 is etched back. The Schottky contact metal layer 209a includes at least one metal silicide layer formed by a conventional auto-aligned silicide process. A refractroy metal layer (not shown) may be formed on the surface of the formed structure to replace the metal silicide layer 209a and be formed simultaneously with the metal layer 210. The formed metal layer 2 1 0 a is made of silver (A g), sau (A 1) or gold (Au) on a barrier metal. It can be clearly seen from FIGS. 2A to 2G that the first type of self-aligning Schottky barrier contact structure of the present invention can be manufactured by only two mask photoresist steps. The diffusion protection ring 2 0 7 The width of a is defined by the first side wall dielectric pad 2 0 5 a, which can be controlled to be smaller than the minimum line width of a technology used. In addition, the diffusion guard ring 2 0 7 a has a shallow junction and a relatively low and slope impurity distribution to eliminate the impact of the curvature of the junction on the collapse voltage, and a forward voltage under a known forward current can be passed Smaller stray series resistance to reduce. Please refer to FIG. 3A and FIG. 3B, which illustrate the manufacturing steps and a schematic cross-sectional view of FIG. FIG. 3A shows that a second side wall dielectric cushion layer 2 0 8 a is formed on the dielectric layer 204 and is disposed on a part of the surface of the dielectric layer 204;

1232591 V. Description of the invention (8) A dielectric layer 2 0 4 is placed on the forming field oxide layer 2 0 2 a and is located in a region surrounded by the second side wall dielectric pad layer 2 8 a It is removed by non-isotropic dry etching or hot phosphoric acid. Next, the thermal silicon dioxide layer 2 0 3 surrounded by the second side wall dielectric pad 2 0 a is buffered hydrofluoric acid or Hydrofluoric acid was diluted to remove it. The second side wall dielectric hafnium layer 2 0 8 a is composed of silicon dioxide and is deposited by the LPCVD method. FIG. 3B shows that a Schottky barrier contact metal layer 209a is formed on an exposed semiconductor surface surrounded by the second side wall dielectric pad layer 208a; then, a shaped metal layer 210a system is formed. Formed on a portion of the surface of the forming field oxide layer 202a, a portion of the surface of the dielectric layer 204a, the second side wall dielectric pad layer 2 0a, and the Schottky barrier contact metal Layer 2 0 9 a. The Schottky barrier contact metal layer 209a and the formed metal layer 21a are as discussed in FIG. 2G. Comparing Figure 2g and Figure 3B, the second type of self-aligning Schottky barrier contact structure is similar to the first type of self-aligning Schottky barrier contact structure, so its features and advantages are similar to the first type. The auto-alignment Schottky barrier contact structure is as described. It is worth noting here that the thermal silicon dioxide layer shown in FIG. 2C can be formed on the forming field oxide layer 2 0 a with a liner (1 i ne r) silicon dioxide layer (not shown) and Above the exposed semiconductor substrate 201/200 surrounded by the field oxide layer 2 0 2 a. Therefore, the second side wall dielectric layer 2 0 8 a shown in FIG. 2G is placed on the thermal silicon dioxide layer 2 0 3 a to use the second side wall dielectric pad layer 2 8 a The liner (1 i ned) has a silicon dioxide liner; the dielectric layer 204a shown in FIG. 2B is formed on an inner edge side wall of the molding field oxide layer 202a and is placed on the heat Silicon dioxide layer

Page 14 1232591 V. Description of the invention (9) The dielectric oxide layer 204 is lined with a silicon dioxide-lined silicon layer to replace the silicon oxide-lined silicon layer 203. The silicon dioxide-lined layer 203 is formed by a L P C V D or high temperature oxide (Η T 0) deposition method. Based on this, the features and advantages of the self-aligning Schottky barrier contact structure of the present invention can be summarized as follows: (a) The self-aligning Schottky barrier contact structure of the present invention can use two mask photoresist steps to Manufacturing. (b) The self-aligning Schottky barrier contact structure of the present invention provides a diffusion protection ring defined by a first side wall dielectric cushion to reduce the surface area occupied by the diffusion protection ring and thus provides Optimize the effective surface area to form a Schottky barrier metal contact. (c) The self-aligned Schottky barrier contact structure of the present invention provides a second side wall dielectric pad to improve metal step coverage. (d) The self-aligning Schottky barrier contact structure of the present invention provides a diffusion guard ring with a shallow junction depth and a relatively low and sloped dopant distribution to eliminate the impact of the junction curvature effect on the breakdown voltage and A forward voltage below a known forward current. Although the present invention is particularly illustrated and described with reference to the attached examples or connotations, it is only a representative statement and not a limitation. Furthermore, the present invention is not limited to the details listed, and those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention, but also belong to the present invention. Fans of invention.

Page 15 1232591 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a prior art Schottky barrier contact structure with a diffusion guard ring. Figures 2A to 2G disclose the manufacturing steps and a schematic cross-sectional view of the first type of self-aligning Schottky barrier contact structure of the present invention. Fig. 3A and Fig. 3B show the manufacturing steps and a schematic cross-sectional view of Fig. 2F, which are subsequent to Fig. 2F, for manufacturing a second type of self-aligning Schottky barrier contact structure of the present invention. Representative drawing number description: 200 and doped semiconductor substrate 20 1 202 field oxide layer 2 0 2a 203 track silicon dioxide layer 2 0 3a 204 dielectric layer 2 0 4a 2 0 5a 2 0 6a 207 Ion-implanted area 2 0 7a 208 Dielectric layer of the second side wall 2 0 9a 2 10 Metal layer 210a Layer body layer conductive layer Fractured semi-crystalline crystalline oxygen layer Insect oxygen secondary electric field hybrid Folded curtain into a mask

Environmental protection, protection and expansion, P layer, metal contact layer, fund connection, special shape, Xiao Cheng

Page 16

Claims (1)

1232591 VI. Scope of patent application 1. An auto-aligned Schottky barrier contact structure including at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes at least a lightly doped epitaxial semiconductor layer formed on a high Doped on a semiconductor substrate; a diffusion protection ring of a second conductivity type is formed on a designed surface portion of the semiconductor substrate through an ion implantation window defined by a first side wall dielectric pad Within the first side wall dielectric pad layer, a dielectric layer is formed on a molding field oxide layer, and a thermal silicon dioxide layer surrounded by the molding field oxide layer is disposed on the semiconductor. On an inner edge side wall above the substrate; a Schottky contact metal layer is formed on at least the diffusion protection ring and the semiconductor substrate surrounded by a second side wall dielectric cushion layer; and A forming metal layer is formed on at least a part of the surface of the forming field oxide layer, the second side wall dielectric pad layer, and the Schottky contact metal layer. 2. The self-aligning Schottky barrier contact structure described in item 1 of the scope of the patent application, wherein the first side wall dielectric pad is composed of silicon dioxide and uses low pressure chemical vapor deposition (LP CV D) and the dielectric layer is composed of silicon nitride and is deposited using the LPCVD method. 3. The self-aligned Schottky barrier contact structure described in item 1 of the scope of the patent application, wherein the second side wall dielectric pad layer is made of silicon nitride or oxynitride Page 171232591 VI. Scope of Patent Application Silicon is formed by using LPCVD to form a part of the surface of an inner edge side wall of the forming oxide layer and placed on the thermal dioxide layer Above. 4. The self-aligning Schottky barrier contact structure described in item 1 of the scope of the patent application, wherein the second side wall dielectric pad layer is composed of silicon dioxide and is formed by using a LPCVD method. A dielectric layer is placed over the field oxide layer and over a portion of the surface of the thermal silicon dioxide layer. 5. The self-aligned Schottky barrier contact structure described in item 1 of the scope of patent application, wherein a mask dielectric layer includes at least one mask photoresist or one (ρ ο 1 ynide) system formed by The first side wall dielectric pad is surrounded by the dielectric layer as an etching mask to selectively remove the first side wall dielectric pad to form the ion implanted window. 6. The self-aligning Schottky barrier contact structure described in item 1 of the scope of the patent application, wherein the above-mentioned diffusion guard ring includes at least a moderately doped diffusion guard ring or a highly doped diffusion guard ring with a slope impurity distributed. 7. An auto-aligned Schottky barrier contact structure, comprising at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises at least a lightly doped epitaxial semiconductor layer formed on a highly doped semiconductor substrate A diffusion protection ring of a second conductivity type is transmitted through a first measurement Page 181232591 6. Scope of patent application An ion-implanted window defined by a dielectric layer of a side wall is formed within a designed surface of the semiconductor substrate, wherein the first side wall dielectric layer is formed. A Schottky contact metal layer is formed on at least one inner dielectric sidewall formed by a composite dielectric layer on a forming field oxide layer and the semiconductor substrate surrounded by the forming field oxide layer; On the diffusion protection ring and the semiconductor substrate surrounded by a second side wall dielectric pad; and a forming metal layer is formed on a part of the surface of the forming field oxide layer and the composite dielectric layer A portion of the surface, the second side wall dielectric layer, and the Schottky contact metal layer. 8. The self-aligned Schottky barrier contact structure described in item 7 of the scope of the patent application, wherein the composite dielectric layer includes at least one silicon nitride layer deposited by the LPCVD method, and by the LPCVD method or a high temperature oxide ( Η T 0) stacked on a silicon dioxide-lined layer. 9. The self-aligning Schottky barrier contact structure as described in item 7 of the scope of patent application, wherein the first side wall dielectric cushion layer is composed of silicon dioxide and is stacked using the LPC VD method to form a The mask dielectric layer is placed on the composite dielectric layer surrounded by the first side wall dielectric cushion layer and then removed to form the ion implanted window. 10. Automatic alignment of Schottky barrier contacts as described in item 8 of the patent application Page 19, 1232591 6. The scope of the patent application, wherein the above-mentioned mask dielectric layer includes at least one photoresist layer or one (ρ ο 1 yimide) layer after being ion-implanted through the ion-implanted window to be removed. . 1 1. The self-aligning Schottky barrier contact structure as described in item 7 of the scope of the patent application, wherein the second side wall dielectric pad is composed of silicon dioxide and is formed by using LPCVD An inner edge side wall of the composite dielectric layer is placed on a part of the surface of the composite dielectric layer. 1 2. The self-aligning Schottky barrier contact structure described in item 7 of the scope of patent application, wherein the second side wall dielectric pad layer is composed of silicon nitride or silicon oxynitride and is obtained by LPCVD method. A stacking system is formed on a silicon dioxide-lined silicon dioxide-lined layer formed on a portion of the surface of the silicon dioxide-lined layer formed on the molding field oxide layer and on a portion of the surface of the diffusion protection ring. Inside edge side wall. 1 3 · The self-aligning Schottky barrier contact structure described in item 7 of the scope of patent application, wherein the Schottky contact metal layer includes at least one high-temperature-resistant metal layer or a metal silicide layer by an automatic alignment Quasi-silicidation process to form. 1 4 · The self-aligning Schottky barrier contact structure described in item 7 of the scope of the patent application, wherein the above-mentioned field oxide layer includes at least one thermal silicon dioxide layer by thermally oxidizing the semiconductor substrate in a vapor or Wet oxygen down Page 20 1232591 6. The scope of the patent application grows, a doped silicon dioxide layer is deposited by chemical vapor deposition (CVD) or a doped CVD silicon dioxide layer is placed on a thermal silicon dioxide layer. A self-aligning Schottky barrier contact structure, including at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate includes at least a lightly doped epitaxial semiconductor layer formed on a highly doped semiconductor substrate A diffusion protection ring of a second conductivity type is formed in a designed surface portion of the semiconductor substrate through an ion implantation window defined by a first side wall dielectric pad. The dielectric layer on the first side wall is composed of dioxide, formed on a stone dioxide layer or a composite dielectric layer, formed on a forming field oxide layer, and placed on the forming field oxide layer. A surrounding thermal silicon dioxide layer or an inner edge side wall over the semiconductor substrate and a mask dielectric layer are formed surrounded by the first side wall dielectric pad layer. The silicon nitride layer is formed on the composite dielectric layer by removing the first side wall dielectric pad layer to form the ion implanted window; a Schottky contact metal layer is formed at least on a second side edge Above an exposed semiconductor surface surrounded by a wall dielectric pad, wherein the second side wall dielectric pad is composed of silicon nitride or silicon oxynitride and is formed on an inner edge of the forming field oxide layer Above the side wall and placed on a side surface of the thermal silicon dioxide layer or composed of silicon dioxide is formed on an inner edge side wall of the silicon nitride layer or the composite dielectric layer. On the nitrogen Page 211232591 6. Patent application scope: Silicon layer or a part of the surface of the composite dielectric layer; and a forming metal layer is formed on at least a part of the surface of the forming field oxide layer and the second side A dielectric layer on the sidewall and the Schottky contact metal layer. 16. The self-aligning Schottky barrier contact structure described in item 15 of the scope of patent application, wherein the mask dielectric layer includes at least one photoresist layer or one (polyimide) layer and the first layer is removed by removing The ion implantation window formed on the dielectric layer on one side is removed after ion implantation, and the composite dielectric layer includes at least a silicon nitride layer on a silicon dioxide-lined layer. 17. The self-aligning Schottky barrier contact structure described in item 15 of the scope of patent application, wherein the diffusion guard ring includes at least a moderately doped diffusion guard ring or a highly doped diffusion guard ring with a ramp doping Impurity distribution. 18. The self-aligning Schottky barrier contact structure as described in item 15 of the scope of patent application, wherein the Schottky contact metal layer includes at least one high-temperature-resistant metal layer or a metal oxide layer by an automatic alignment It is formed by a quasi-shixi chemical process. 19. The self-aligning Schottky barrier contact structure described in item 15 of the scope of patent application, wherein the formed metal layer comprises at least one silver (Ag), aluminum (A1) or gold (Au) layer formed on an obstacle Over the metal layer with a second cover Page 22 1232591 VI. Scope of Patent Application Curtain photoresist step to shape. 20. The self-aligning Schottky barrier contact structure as described in item 15 of the patent application scope, wherein the molding field nutrient layer includes at least one thermal silicon dioxide layer by thermally oxidizing the semiconductor substrate to a water vapor or To grow in a wet oxygen environment, a doped silicon dioxide layer is deposited by CVD or a doped CVD SiO2 layer is placed on top of a thermal SiO2 layer and is protected by a first mask Steps to shape. Page 23