1229445 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（） 發明領域： 本發明係有關於一種電容器（Capacitor)結構與製造方 法’特別是有關於一種褶層型（F〇ldecUtype)電容結構與製 xe方法’可在積體電路（IC)製程上增加電容面積，同時得 到增加電容值的效果，除可應用於例如晶片型電容、晶片 型電谷陣列等小型化被動元件的電容小型化外，更可應用 於動心 Pic 機存取 δ己憶體（Dynamic Random Access Memory ; DRAM)的記憶單元等需要單位面積電容值提高的ic製程 上。 發明背景： 動態隨機存取記憶體是一種廣泛應用的積體電路元 件’尤其在今日資訊電子產業中更佔有極重要的地位。近 年來由於各類電子元件均朝高積集度及高速率運作及微小 化的方向發展。對於DRAM的記憶單元來說，在積體化後， 因為電容電極接觸面積變小，造成電容量下降，因此目前 有溝槽型（Trench-type)、堆疊型（Stacked_type)以及冠銮 (Crown-type)等三種增加電容電極接觸面積方法，使得電容 量的提昇。隨著製程技術的演進，目前生產線上常見的動 態隨機存取記憶單元（DRAM cell)大多是由一電晶體τ和 一電容器C所構成，如第1圖的電路圖所示者。基本上， (請先閱讀背面之注意事項再填寫本頁)1229445 Printed by A7 B7, Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs 5. Description of the invention () Field of the invention: The present invention relates to a capacitor structure and manufacturing method, especially to a fold type (FolldecUtype) Capacitor structure and manufacturing method x 'can increase the capacitance area in the integrated circuit (IC) process, and at the same time get the effect of increasing the capacitance value, in addition to the capacitors that can be applied to miniaturized passive components such as chip capacitors, chip type valley array In addition to miniaturization, it can also be applied to ic processes that need to increase the capacitance per unit area, such as memory cells of a dynamic random access memory (DRAM). Background of the invention: Dynamic random access memory is a widely used integrated circuit element, and it occupies a very important position, especially in today's information electronics industry. In recent years, various types of electronic components have developed in the direction of high accumulation, high-speed operation, and miniaturization. For the DRAM memory cells, after the integration, the capacitance electrode contact area becomes smaller, which causes the capacitance to decrease. Therefore, there are currently trench-type, stacked-type, and crown-type type) and other three methods to increase the contact area of the capacitor electrode, so that the capacitance is improved. With the evolution of process technology, the dynamic random access memory cells (DRAM cells) commonly used in current production lines are mostly composed of a transistor τ and a capacitor C, as shown in the circuit diagram in Figure 1. Basically, (Please read the notes on the back before filling out this page)
1229445 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 電晶體T的源極（source)係連接到一對應的位元線（bit line)BL，汲極（drain)連接到電容器C的儲存電極（st〇rage electrode)，而閘極（gate)則連接到一對應的字元線（w〇rd line)WL’電谷器C的相對電極（opposed electrode)係連接 到一固定電壓源，而在儲存電極和相對電極之間則設置一 介電質層。如熟習此藝者所知，電容器C是用來储存電 何以&供電子資訊的’其應具有足夠大的電容量，方可避 免資料的流失並減低充電更新（refresh)的頻率。在傳統少 於一百萬位元（1MB)的DRAM元件製程中，一般多利用二 度空間構造的電容器來儲存資料，亦即泛稱的平坦邊 (Planar-type)電容器。然而’平坦型電容器需佔用相當大 的基板面積，方足以提供足夠的電容量，故並不適於目前 曰益而度積集化之DRAM元件的製程。因此，高度積集 化的DRAM元件，例如大於一千六百萬位元（16M)的儲存 容量者，必須利用三度空間結構的電容器來實現，例如所 謂的溝槽型或堆疊型電容器記憶元件。其中，由於蝕刻溝 槽來製作電容時不可避免地會在基板產生晶格缺陷 (Defects)，造成漏電流的增加而影響元件性質，並且隨著 溝槽縱橫比（Aspect Ratio)的增大，其蝕刻速率亦將遞 減，不僅製程難度增加也影響了生產效率，因此實際生產 線上使用此類溝槽型電容器製程的並不普遍。相反地，堆 疊型電容器記憶元件的製程則不會有上述缺點，因此許多 技術研發均係針對此一型式的記憶元件進行改良，用以達 3 本紙張尺度適用中國國家標準（CNS)A^_規格（21〇 χ 297公----- (請先閱讀背面之注意事項再填寫本頁) · n II ϋ ΙΒ1 n n n · n n §1 n n «it an I · 1229445 A7 B7 五、發明說明（） 到在記憶元件尺寸縮小時，仍能確保提供足夠大之電容量 的目的。為了提高電容器C的電容量，可從兩個方向= 手：一是減小介電質層的厚度，一是增加儲存電極的表面 X在減小介電質層的厚度方面，現今製造的記憶元件電 容器/句G使用極薄之介電質層，然而其厚度並非可無限制 地減小，當介電質層的厚度小於50A時，即可能因直接 f子隧穿（Dlrect Carrier TunneUng)而產生過大的漏電 流，影響元件的性質。因此，許多研發都致力於增加错存 電極的表面積，藉以提升電容器的電容量。各種改良製程 2 於儲存電極上形成凹凸不平的粗糙（Rugged)表面構 用以增加儲存電極的表面積，達到提升電容器之電容 量的目的，疋一種簡單而有效的方法。然而，習知製程中 夕係於形成粗糙表面構造後，才進行蝕刻程序來定義出 電容器範圍的，故其所製得的儲存電極的整體表面積增加 有限提升電容量的效果受到限制，影響元件之性質， 此有必要謀求改善之道。 發明目的及概述： 鑒於上述之發明背景中，習知電容器及其製程均有 改進’因此本發明之目的係提供-種在κ：製程上增加電容 面積的結構與方法’相對於一般增大面積的方法，有較簡 易的製程步驟。 本紙張尺度適时關家標準（CNS)A4祕 f請先閱讀背面之>i意事項再填寫本頁) ^--------t-------- 經濟部智慧財產局員工消費合作社印製 12294451229445 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () The source of transistor T is connected to a corresponding bit line BL, and the drain is connected to The storage electrode (capacitor electrode) of the capacitor C, and the gate (gate) is connected to a corresponding word line (WL) line WL 'Opposed device (opposed electrode) is connected to a The voltage source is fixed, and a dielectric layer is provided between the storage electrode and the opposite electrode. As is known to those skilled in the art, the capacitor C is used to store electricity & information of the electron donor. It should have a sufficiently large capacity to avoid the loss of data and reduce the frequency of charge refresh. In the traditional DRAM device manufacturing process with less than one million bits (1MB), two-dimensional capacitors are usually used to store data, which is also known as Planar-type capacitors. However, the 'flat capacitor requires a relatively large substrate area to provide sufficient capacitance, and is not suitable for the current process of accumulating DRAM components. Therefore, highly integrated DRAM devices, such as those with a storage capacity of more than 16 million bits (16M), must be implemented using capacitors with a three-dimensional space structure, such as so-called trench-type or stacked-type capacitor memory elements. . Among them, lattice defects are inevitably generated on the substrate when the trench is etched to make a capacitor, which causes an increase in leakage current and affects the properties of the element. As the aspect ratio of the trench increases, the The etching rate will also decrease, which not only increases the difficulty of the process but also affects the production efficiency. Therefore, it is not common to use such trench capacitor manufacturing processes on actual production lines. In contrast, the manufacturing process of stacked capacitor memory elements does not have the above disadvantages. Therefore, many technological developments are aimed at improving this type of memory elements to achieve 3 paper standards applicable to China National Standard (CNS) A ^ _ Specifications (21〇χ 297 公 ----- (Please read the precautions on the back before filling this page) · n II ϋ ΙΒ1 nnn · nn §1 nn «it an I · 1229445 A7 B7 V. Description of the invention () When the size of the memory element is reduced, the purpose of ensuring a sufficient capacitance is still provided. In order to increase the capacitance of the capacitor C, two directions can be used = hand: one is to reduce the thickness of the dielectric layer, and the other is to increase In terms of reducing the thickness of the dielectric layer, the surface X of the storage electrode uses a very thin dielectric layer for memory element capacitors / sentences manufactured today. However, its thickness cannot be reduced indefinitely. When the thickness is less than 50A, excessive leakage current may be generated due to direct f-tunnel tunneling (Dlrect Carrier TunneUng), which affects the properties of the device. Therefore, many R & D efforts are devoted to increasing the surface area of staggered electrodes to improve Capacitance of the container. Various improved processes2 A rough surface is formed on the storage electrode to increase the surface area of the storage electrode and achieve the purpose of increasing the capacitance of the capacitor. However, a simple and effective method. In the conventional manufacturing process, the etch process is used to define the capacitor range after the rough surface structure is formed. Therefore, the overall surface area of the storage electrode produced is limited, and the effect of increasing the capacitance is limited, which affects the properties of the component. It is necessary to seek ways to improve. Purpose and summary of the invention: In view of the above background of the invention, conventional capacitors and their processes have been improved. Therefore, the purpose of the present invention is to provide a structure and a method for increasing the capacitor area in the κ: process and Method 'Compared to the general method of increasing the area, there are simpler process steps. The paper size timely standard (CNS) A4 secret (please read the > i notice on the back before filling this page) ^- ------ t -------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1229445
五、發明說明（ 本發明之另一目的就是提供一 種電容器，其相鲂於如 上所述的習知電容器，因為本發明 、數於士 落差較小，約小於1 500埃，所LV 士 ”看的冋度 Coverage)的能力。 有利於階梯覆蓋（Step 本發明之再-目的就是提供—種糟層型電容器 電極表面係經過粗輪化處理，因μ '、 U此可進一步增加電容值。 本發明之再一目的就是提供—褶 ^ ^ ^層型電容結構，是 利用電容並聯時，電容值相加的 ^ 疋 J尽理，實際應用於褶層型 電容的結構，可應用於例如晶片型 更各、晶片型電容陣列 等小型化被動元件，也可應用於Α λ/Γ二 的記憶單元等需要 單位面積電容值提高的1C製程上。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 依據本發明之上述目的，因此本 令赞明徒供一種權層型 電容器之結構，至少包括：一下電極；一介電層；以及一 上電極，其中該下電極、該介電層、與該上電極係以一摺 層數目堆疊而成，該下電極與該上電極各自成一梳狀結 構，且該下電極與該上電極之該梳狀結構係以一距離相互 間隔且穿插排列，而該介電層則係位於該下電極與該上電 極之間。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） --------^--------- 1229445 . A7 ___B7 五、發明說明（） 根據本發明之上述目的本發明另外提供一種褶層型電 容器之製造方法，至少包括下列步驟：a.提供一基板；b. 形成一第一導體層於該基板上；c.形成一第一介電層覆蓋 部分之該第一導體層與該基板，且曝露出另一部份之該第 一導體層；以及d.形成一第二導體層覆蓋部分之該第一介 電層與該基板，且曝露出另一部分之該第一介電層。e.形 成一第二介電層覆蓋曝露出之該第一介電層與部分之該第 二導體層，且曝露出另一部分之該第二導體層；f·形成一第 三導體層覆蓋曝露出之該第一導體層與部分之該第二介電 層，曝露出部分之該第二介電層；g·形成一第三介電層覆 蓋曝露出之該第二介電層與部分之該第三導體層，曝露出 另一部分之該第三導體層；以及h·形成一第四導體層覆蓋 曝露出之該第二導體層與部分之該第三介電層，曝露出另 一部分之該第三介電層。 (請先閱讀背面之注意事項再填寫本頁) 明 說 單 簡 式 圖 列 下 以 辅 中 字 文 明 說 之 後 往 於： 將中 例其 施， 實述 佳闡 較的 的細 明詳 發更 本做 形 圖 經濟部智慧財產局員工消費合作社印製 1 2 圖 第第意 示 罩 圖V. Description of the invention (Another object of the present invention is to provide a capacitor which is comparable to the conventional capacitor as described above, because the present invention has a small difference between the number and the value, which is less than about 1 500 Angstroms. The capacity of the Coverage is good. It is beneficial to the step coverage (Step The purpose of the present invention is to provide-the surface of the capacitor of the bad layer type capacitor has undergone rough rounding treatment, because μ 'and U can further increase the capacitance value. Another object of the invention is to provide-a pleated ^ ^ layered capacitor structure, which uses ^ 疋 J to add capacitance values when capacitors are connected in parallel, and is actually applied to the structure of a pleated capacitor, which can be applied to, for example, a chip type In addition, miniaturized passive components such as chip-type capacitor arrays can also be applied to 1C processes that require increased capacitance per unit area, such as memory cells of Aλ / Γ2. (Please read the precautions on the back before filling out this page) The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned purpose in accordance with the present invention. Therefore, this order commends the structure for providing a right-layer capacitor, including at least: the lower electrode; An electrical layer; and an upper electrode, wherein the lower electrode, the dielectric layer, and the upper electrode are stacked in a folded layer number, the lower electrode and the upper electrode each form a comb structure, and the lower electrode and The comb structure of the upper electrode is arranged at a distance from each other and interspersed with each other, and the dielectric layer is located between the lower electrode and the upper electrode. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297) -------- ^ --------- 1229445. A7 ___B7 V. Description of the invention () According to the above purpose of the present invention, the present invention further provides a manufacture of a pleated capacitor The method includes at least the following steps: a. Providing a substrate; b. Forming a first conductor layer on the substrate; c. Forming a first dielectric layer covering portion of the first conductor layer and the substrate, and exposing the substrate Another portion of the first conductor layer; and d. Forming a second conductor layer covering a portion of the first dielectric layer and the substrate, and exposing another portion of the first dielectric layer. E. Forming a The second dielectric layer covers the exposed first dielectric layer and a portion of the second conductive layer. Layer, and exposing another part of the second conductor layer; f. Forming a third conductor layer covering the exposed first conductor layer and part of the second dielectric layer, exposing part of the second dielectric layer G. Forming a third dielectric layer covering the exposed second dielectric layer and a portion of the third conductor layer, exposing another portion of the third conductor layer; and h · forming a fourth conductor layer Cover the exposed second conductor layer and part of the third dielectric layer, and expose another part of the third dielectric layer. (Please read the precautions on the back before filling this page) The following is supplemented by the Chinese character civilization theory: I will apply the examples in the middle, and explain the detailed details of the better explanations and make a copy of this. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure
圖 A ;光 圖之 路例 電施 之實 元佳 單較 憶明 記發 取本 存據 機依 隨示 態緣 動係 知圖 習2B 示第 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1229445 . A7 _^_B7_ 五、發明說明（） 第3 A圖至第3N圖係繪示依據本發明一較佳實施例之 一種電容器之製程剖面圖； 第4圖係依據本發明之層數對電容密度之數據圖； 第5圖係繪示依據本發明一較佳實施例之一種DRAM 之電容器之剖面示意圖； 圖號對照說明： T :電晶體 B L :位元線 WL :字元線 C :電容器 10 、 12 、 14 :光罩 20、104 ：基板 22、28、34、40、44、48、52:光阻層 24 、 30 、 36 、 42 、 46 、 50 、 54 :開口 26a、26b :導體層 32a、32b、32c:介電層 38a、38b :導體層 (請先閱讀背面之注意事項再填寫本頁) --------訂---- 經濟部智慧財產局員工消費合作社印製 器窗體 容觸晶 電接電 0 2 6 ο ο ο 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1229445 ’ Α7Figure A; Road map example of light maps. Shiyuan Jiadan of Electricity Co., Ltd. issued the depository machine according to the dynamics of the situation according to the illustrated situation. Figure 2B shows that the paper size is applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) 1229445. A7 _ ^ _ B7_ V. Description of the invention () Figures 3A to 3N are cross-sectional views of a capacitor manufacturing process according to a preferred embodiment of the present invention; Figure 4 is based on The data graph of the layer number versus the capacitance density of the present invention; FIG. 5 is a schematic cross-sectional view of a DRAM capacitor in accordance with a preferred embodiment of the present invention; the comparison of drawing numbers: T: transistor BL: bit line WL : Word line C: Capacitors 10, 12, 14: Masks 20, 104: Substrates 22, 28, 34, 40, 44, 48, 52: Photoresist layers 24, 30, 36, 42, 46, 50, 54 : Openings 26a, 26b: Conductor layers 32a, 32b, 32c: Dielectric layers 38a, 38b: Conductor layer (Please read the precautions on the back before filling this page) -------- Order ---- Economy Ministry of Intellectual Property Bureau, Employee Consumer Cooperative Printed Device Forms, Touch Chips, Electrical Connections 0 2 6 ο ο ο This paper standard applies to Chinese national standards Standard (CNS) A4 (210 X 297 mm) 1229445 ′ Α7
五、發明說明（） 發明詳細說明： 在256百萬位元組的DRAM元件，基 單元至少需一在積集化：： 電容值可行的方法及方向有三種，分別是使用高介電值（k 值）的介電材料，將介電層儘量降低其厚度，以及改變電容 器結構使« S ®積增加。本發明就是針對電纟器結構的改 變，設計出光罩，然後藉由IC製程的步驟，製作出晶片型 電容元件，並量測其電性，以證明此電容結構的可行。 本發明之權層型晶片電容的製造方法，係為一應用於 以一氧化石夕/石夕為基板的被動元件，利用本發明之三種光 罩’分別為光罩1〇、光罩12與光罩14，如第2A圖至第 2B圖所不，依序進行曝光顯影，然後沉積金屬層與高介電 值之介電層薄膜，材質例如為五氧化二钽（Ta2〇5)，於基板 上，藉以形成褶層型電容晶片。其中，光罩1〇之長寬各約 為180μιη與ΙΟΟμπι，光罩12之長寬各約為ΜΟμιη與 140μιη’而光罩14之長寬各約為“卟瓜與1〇〇μιη。 (請先閱讀背面之注意事項再填寫本頁) n n I I I n an 一OJ· n n ϋ— I an ϋ n I * 經濟部智慧財產局員工消費合作社印製 本發明之褶層型晶片電容的製造流程，係繪示於第3A 圖至第3N圖中。首先請參照第3A圖，提供基板20，其 材質可為二氧化矽/矽。此處必須注意的一點是本發明之電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1229445 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（ >裔可應用於晶片型電容、晶片型電容陣列等小型化被動 兀件t可應用於DRam的記憶單元中，因此此處所提供 之基板僅為舉例，廿非田 J 正非用以限定本發明。若本發明係應用 於D R A Μ中，目丨丨μμ总知；7 只J此暴板可為已形成有組成Dram所必備之 兀件例如電晶體與主動區等（如第5圖所示）。因為，此 基板之 '、且成並非本發明之重點，量可不再冗述。 接著七成一層光卩且層22覆蓋此基板2〇，然後利用第 2Β圖所示之光罩12，斟企 對先阻層22進行曝光顯影的步驟， 而移除不必要之部分，葬 ： 曰乂露出一開口 24，使得光阻層22 具有第3Α圖所示之4士雄 ^ ° Ik後，進行導體層的形成步驟， 例如使用賤鍍法或是化學 ^ ^ a 予虱相7儿積法，在光阻層22上形成 一層導體層並填入開口 24 φ 中。在導體層填入開口 2 4之後， 接者例如使用濕式或兹+ 〆 工）丨除法以去除光阻層22以及位 在光阻層22上之導體層， 僅保留填入開口 24中之導體層 26a,而形成如第3Β圖所V. Description of the invention () Detailed description of the invention: For 256 megabyte DRAM elements, at least one base unit needs to be accumulated: There are three possible methods and directions for the capacitance value, which are using high dielectric value ( k value) of the dielectric material, to reduce the thickness of the dielectric layer as much as possible, and to change the capacitor structure to increase the «S ® product. The present invention is designed to change the structure of the capacitor, design a photomask, and then use the steps of the IC process to make a chip-type capacitor element and measure its electrical properties to prove the feasibility of the capacitor structure. The method for manufacturing a right-layer chip capacitor according to the present invention is a passive element applied to a substrate with monolithic oxide / lithium as a substrate. The three photomasks of the present invention are a photomask 10, a photomask 12 and The photomask 14, as shown in FIGS. 2A to 2B, is sequentially exposed and developed, and then a metal layer and a high-k dielectric layer film are deposited, for example, tantalum pentoxide (Ta205). On the substrate, a pleated capacitor chip is formed. Among them, the length and width of the photomask 10 are about 180 μm and 100 μm, the length and width of the photo mask 12 are about 100 μm and 140 μm ′, and the length and width of the photo mask 14 are about “portrait and 100 μm.” (Please (Please read the notes on the back before filling in this page) nn III n an-OJ · nn ϋ — I an ϋ n I * The manufacturing process for printing the pleated chip capacitor of the present invention by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, is It is shown in Figures 3A to 3N. First, please refer to Figure 3A to provide the substrate 20, which can be made of silicon dioxide / silicon. One thing to note here is that the electrical paper size of the present invention is applicable to China Standard (CNS) A4 specification (210 X 297 mm) 1229445 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 V. Description of the invention (> can be applied to miniaturized passive components such as chip capacitors, chip capacitor arrays, etc. t can be used in the memory unit of DRam, so the substrate provided here is only an example, and Feifei J Zhengfei is used to define the present invention. If the present invention is applied to DRA M, the general purpose is μμ7; 7 Only this storm board can be formed The necessary components such as a transistor and an active area (as shown in FIG. 5) that are necessary to form a Dram. Because the substrate of this substrate is not the focus of the present invention, the amount can be omitted. And the layer 22 covers the substrate 20, and then, using the photomask 12 shown in FIG. 2B, the steps of exposing and developing the first resistive layer 22 are removed, and unnecessary parts are removed, and an opening 24 is exposed: After the photoresist layer 22 has 4 Shixiong ^ ° Ik as shown in FIG. 3A, a step of forming a conductive layer is performed, for example, using a base plating method or a chemical method ^ ^ a lice phase 7 product method, in the photoresist A conductor layer is formed on the layer 22 and filled in the opening 24 φ. After the conductor layer is filled in the opening 2 4, one can use a wet method or a sintering method to remove the photoresist layer 22 and the photoresist. The conductor layer on the layer 22 retains only the conductor layer 26a filled in the opening 24, and is formed as shown in FIG. 3B.
Pf3 e ^ ^ σβ <、、、口構。其中，此導體層26a P疋電谷裔之下電極之一部， ,：1 . θ 其材質可為任何之導體材 料，例如夕日日矽或鋁（Α1)等 -^ ^ 导體層或疋鋁/氮化鈦、多晶矽/ 氮化鈦等複合結構。 7 另外，一種可選擇採用製 田夕曰访性s，丄 表程包括當導體層之材質選 ^ 1^1 Φ ^ ^ ^ 用其日日格與溫度之關係，得 到不冋之電極面積。就多曰 多曰曰矽之形成製程而言，當製程溫 本紙張尺度適用中國國家標準（CNS)A4 (請先閱讀背面之注意事項再填寫本頁) 0 n n i a^i i n ϋ 一口，I In i^i ·_ϋ n ·ϋ n I · 1229445 A7 五、發明說明（ -於攝氏550度時，此結構呈現非晶石夕（Amorphous)狀 ^而具有平滑狀之表面。但是當製程溫度漸昇至攝氏5 60 度時’此結構則呈現非晶矽與多晶矽共存之狀態，此時結 籌表面上會產生半圓形球狀物（Hemispherical Gain ; HS〇) ’隨著溫度的逐漸上升，球狀物的直徑會開始減少， 但是密度卻會增加。直至攝氏565度之後，隆起之球狀物 會從半球狀改變成圓柱狀，此時非晶矽狀態已經完全消 失。當溫度昇至超過攝氏58〇度時，結構就會完全轉變成 為夕曰曰矽狀態，同時維持小幅度的隆起結構（未繪示），而 增加了接觸電極的面積。一般而言，藉由此隆起結構，可 比傳統製程之電容器多出2.5倍之接觸面積。任何熟習此 技藝者，在經過本發明之教示後當知如何應用此隆起結 構’因此本發明不再冗述其製程。 隨後，形成另一層光阻層28覆蓋基板20，同時覆蓋導 體層26a。再利用第2B圖所示之光罩1〇對光阻層28進行 曝光顯影步驟，藉以露出另一開口 3〇,使得光阻層U且 有第3C圖所示之結構。隨後，進行介電層的形成步驟，: 如使用化學氣相沉積法，在光阻層28上形成一層介電層並 填入開口 3"。在介電層填入開口 3〇之後，接著例如使 用濕式或乾式剝除法以去除光阻層28以及位在光阻層Μ 上之介電層，僅保留填入開口 3〇中之介電層…，而形成 如第3D圖所示之結構。其中，介電層仏之材質可為任何 (請先閱讀背面之注意事項再填寫本頁) · I I J I I I I*tr°J— — — — — — — — I. 經濟部智慧財產局員工消費合作社印製 10 1229445 經濟部智慧財產局員工消費合作社印製 A7 _B7___ 五、發明說明（） 具有高介電係數之材質，例如五氧化二钽（丁a205)、二氧化 鈦（Ti02)、氧化矽/氮化矽/氧化矽（ΟΝΟ)、鈦酸緦鋇 (BaSiTi〇3 ; BST)、锆鈦酸鉛（ΡΖΤ)或氮氧化矽等，本發明 不限於此。 當介電層32a完成之後，另一種可選擇採用之步驟就 是在而溫中’例如在攝氏約7 〇 〇度至攝氏約9 5 0度高溫以 及氧化亞氮（N2〇)之氣體環境中對介電層32a進行氮化熱處 理步驟，藉以使得介電層的表面形成一層氮化物（未繪 示），以強化界面間鍵結，並可改善介電層之缺陷。藉此； 元件的低電場漏電流（Leakage Current)與崩潰電壓 (Breakdown Vo It age)便可獲得良好改進，同時可提升介電 層之介電常數至約25左右’故電容值可提昇約2〇%至 2 5%。 請參照第3 E圖，形成另一層光阻層3 4覆蓋第3 D圖所 示之結構。隨後，利用第2 B圖所示之光罩14對光阻層3 4 進行曝光顯影步驟，而移除不必要之部分，藉以形成一開 口 36 ’曝露出介電層32a與基板20，使得光阻層34具有 第3E圖所示之結構。隨後，進行導體層的形成步驟，例如 使用賤鍍法或是化學氣相沉積法，在光阻層34上形成一層 導體層並填入開口 36中。在導體層填入開口 36之後，接 著例如使用濕式或乾式剝除法以去除光阻層34以及位在 π ---1 i I I ------------訂---------· (請先閱讀背面之注意事項再填寫本頁) 1229445 A7 五、發明說明（） 光阻層34上之導體層，僅 ..A # “留真開口 36中之導體層 j8a,而形成如第3F圖 即是電玄考夕卜^ 斤不之結構。其中’此導體層心 即疋電谷态之上電極之一部份，1 ^ 為任何之導體材 枓，例如多晶石夕或铭等導體層或是氣 矽等複合結構。 氣化欽/多曰曰 二#^30圖，例如利用旋轉塗佈法形成—層光阻層 \ 3F所不之結構，接著使用第2B圖所示之光罩 1 〇 ’對光阻層40進行曝光顯影步驟，藉以形成一開口 π 曝露出部分之介電層仏與導體層38a。然後，進行介電層 的形成步驟，例如使用化學氣相沉積法或是其他沉積法， 在光阻層40上形成一層介電層並填入開〇 〇中。在介電 層真入開口 42之後’接著例如使用濕式或乾式剝除法以去 除光阻層40以及位在光阻層4()上之介電層，僅保留填入 開口 42中之介電層32b，而形成如第3h圖所示之結構。 其中；I電層32b之材質如同介電層32a 一般可為任何具 有高介電係數之材質，例如五氧化二钽、二氧化鈦、氧化 矽/氮化石夕/氧化石夕、鈦酸銷銷、錯歎酸勤或氛氧化石夕等，本 發明不限於此。當介電層32b完成之後，另一種可選擇採 用之步驟就疋在高溫中，例如在攝氏約7〇〇度至攝氏約95〇 度向溫以及氧化亞氮之氣體環境中對介電層3几進行氮化 熱處理步驟，藉以使得介電層的表面形成一層氮化物（未繪 示），以強化界面間鍵結，並可改善介電層之缺陷。藉此， 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 (請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 1229445 A7 B7 五、發明說明（ 元件的低電場漏電流與崩潰電壓便可獲得良好改進，同時 可提升介電層之介電常數至約25左右，故電容值可提昇約 2 0% 至 25% 〇 訂 如上所述，可知本發明係利用三種光罩，亦即第2B圖 所示之下電極光罩12、介電層光罩10與上電極光罩14, 依照特定順序交互使用，而形成褶層型電容器結構。其中， 光罩之使用順序分別為下電極光罩1 2 ;介電層光罩1 〇 ;與 上電極光罩14;與介電層光罩1〇,而分別形成了電容器之 下電極（導體層26a)、電容器之介電層（介電層32a與介電 層32b)、以及電容器之上電極（導體層38a)。然而，本發明 並不限於僅完成上述之構造，本發明也可以依據實際需要 而繼續進行後續之製程，如下所述： 接著，請參照第31圖，形成一層光阻層44覆蓋上述 之結構（如第3H圖所示），然後利用第2B圖所示之光罩a， 對光阻層44進行曝光顯影的步驟，而移除不必要之部分， :以形成-開。46’曝露出導體層26a與介電層32b :使 得光阻層4 4具有第31圖所示之结構。^ 經 濟 部 智 慧 財 產 局 < '〇稱隨後，進行導體層 的形成步冑，例如使㈣錢法或是化學氣相沉積法 阻層44上形成-層導體層並填入開口 46中 入開口 4 6之後，接著例如使㈣趙層填 阻層44以及位在光阻層44 ”先 上之導體層，僅保留填入開口 消 費 社 印 製 本紙狀度週用中國國家標準（CNS)A4規格（21〇 13 1229445 . A7 五、發明說明（） 46中之導體層26b，而形成如第3J圖所示之結構。其中’ 此導體層26b即是電容器之下電極之一部份，其材質可為 任何之導體材料，例如多晶石夕或鋁等導體層或是氮化鈦/ 鋁、氮化鈦/多晶矽等複合結構。如上所述，當導體層26b 之材質選用多晶矽時，則本發明亦可利用其晶格與溫度之 關係’而在導體層2 6 b之表面上形成小幅度的隆起結構（未 繪示），而增加了接觸電極的面積。藉由此隆起結構，本發 明可比傳統製程之電容器多出2 · 5倍之接觸面積。 經濟部智慧財產局員工消費合作社印製 請參照第3 K圖，形成另一層光阻層4 8覆蓋第3 J圖所 示之結構。隨後，利用第2B圖所示之光罩14對光阻層48 進行曝光顯影步驟，而移除不必要之部分，藉以形成一開 口 50’曝露出導體層26b與介電層32b，使得光阻層48具 有第3 K圖所示之結構。隨後，進行介電層的形成步驟，例 如使用化學氣相沉積法，在光阻層48上形成一層介電層並 填入開口 50中。在介電層填入開口 5〇之後，接著例如使 用濕式或乾式剝除法以去除光阻層48以及位在光阻層48 上之介電層’僅保留填入開口 5〇中之介電層32c，而形成 如第3L圖所示之結構。其中，介電層32c之材質如同介電 層3 2a —般可為任何具有高介電係數之材質，例如五氧化 二钽、二氧化鈦、氧化矽/氮化矽/氧化矽、鈦酸鳃鋇、鍅鈦 酸鉛或氮氧化矽等，本發明不限於此。當介電層32c完成 之後’另一種可選擇採用之步驟就是在高溫中，例如在攝 14 本紙張尺度適財國國(CNS)A4規格⑽χ挪公餐）---- 1229445 A7 -----—--21___ 五、發明說明（） ----.--111 — — ^--- (請先閱讀背面之注意事項再填寫本頁) 氏約7GG度至攝氏約95〇度高溫以及氧化亞氮之氣體環境 中對；！電層32c進行氮化熱處理步驟，藉以使得介電層的 表面形成層氮化物（未續示），以強化界面間鍵結，並可 改。介電層之缺陷。藉此，元件的低電場漏電流與崩潰電 壓便可獲付良好改進，同時可提升介電層之介電常數至約 25左右，故電容值可提昇約20%至25%。 .贄. 請參照第3M圖，形成另一層光阻層52覆蓋第3l圖 所不之結構。隨後，利用第2B圖所示之光罩14對光阻層 52進行曝光顯影步驟，而移除不必要之部分，#以形成一 開口 54曝露出導體層38a與介電層32〇，使得光阻層η 具有第3M圖所示之結構。隨後，進行導體層的形成步驟， 例如使用濺鍍法或是化學氣相沉積法，在光阻層52上形成 一層導體層並填入開口 54中。在導體層填入開口 54之後， 接著例如使用濕式或乾式剝除法以去除光阻層52以及位 在光阻層52上之導體層，僅保留填入開口 54中之導體層 :>8b而幵/成如第3N圖所示之結構。其中，此導體層38b 即是電容器之上電極之一部份，其材質可為任何之導體材 經濟部智慧財產局員工消費合作社印製 料，例如多晶矽或鋁等導體層或是氮化鈦/鋁、氮化鈦/多晶 矽等複合結構。 如上所述’本發明可依據實際需要而進行後續製程， 因此本發明之結構可持續堆疊，端視實際所需條件而定， 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公餐） 1229445 A7 B7Pf3 e ^ ^ σβ < ,,, mouth structure. Among them, the conductive layer 26a is a part of the lower electrode of the electric valley,: 1. Θ The material can be any conductive material, such as XiRiSi or aluminum (Α1), etc.-^^ / Titanium nitride, polycrystalline silicon / titanium nitride and other composite structures. 7 In addition, an alternative method is to use Tian Xi's viscidity s. 丄 The schedule includes the selection of the material of the conductor layer. ^ 1 ^ 1 Φ ^ ^ ^ Use the relationship between the daily grid and temperature to obtain a large electrode area. As far as the formation process of silicon is concerned, when the process temperature is in accordance with the Chinese National Standard (CNS) A4 (please read the precautions on the back before filling this page) 0 nnia ^ iin ϋ sip, I In i ^ i · _ϋ n · ϋ n I · 1229445 A7 V. Description of the invention (-At 550 degrees Celsius, this structure has an Amorphous shape ^ and has a smooth surface. However, when the process temperature gradually rises to At 5 to 60 degrees Celsius, 'this structure exhibits the state of coexistence of amorphous silicon and polycrystalline silicon. At this time, semi-circular spheres (Hemispherical Gain; HS〇) will be formed on the surface of the chip. The diameter of the object will begin to decrease, but the density will increase. Until 565 degrees Celsius, the raised spheres will change from hemispherical to cylindrical, and the amorphous silicon state has completely disappeared. When the temperature rises above 58 degrees Celsius When the temperature is 0 °, the structure will be completely transformed into a silicon state, while maintaining a small bump structure (not shown), which increases the area of the contact electrode. Generally speaking, with this bump structure, it can be compared with traditional processes. Of The capacitor has 2.5 times more contact area. Anyone skilled in this art should know how to apply this raised structure after the teaching of the present invention, so the present invention will not repeat its process. Then, another photoresist layer 28 is formed to cover The substrate 20 covers the conductor layer 26a at the same time. Then, the photoresist layer 28 is exposed and developed by using the photomask 10 shown in FIG. 2B to expose another opening 30 so that the photoresist layer U has the position shown in FIG. 3C. The structure is shown below. Next, a dielectric layer forming step is performed: if a chemical vapor deposition method is used, a dielectric layer is formed on the photoresist layer 28 and the opening 3 is filled. The dielectric layer is filled with the opening 3. After that, for example, a wet or dry stripping method is used to remove the photoresist layer 28 and the dielectric layer on the photoresist layer M, leaving only the dielectric layer filled in the opening 30, and forming as shown in FIG. 3D The structure shown. Among them, the material of the dielectric layer 仏 can be any (Please read the precautions on the back before filling this page) · IIJIIII * tr ° J— — — — — — — — — I. Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperative 10 1229445 Printed by the Intellectual Property Bureau's Employee Cooperative Cooperative A7 _B7___ V. Description of the Invention () Materials with high dielectric constants, such as tantalum pentoxide (butyl a205), titanium dioxide (Ti02), silicon oxide / silicon nitride / silicon oxide ( 〇ΝΟ), barium hafnium titanate (BaSiTi03; BST), lead zirconate titanate (PZT), or silicon oxynitride, etc., the present invention is not limited thereto. After the dielectric layer 32a is completed, another optional step is In the middle temperature, for example, the dielectric layer 32a is subjected to a nitriding heat treatment step in a gas environment at a high temperature of about 700 to about 950 degrees Celsius and a temperature of nitrous oxide (N20), so that the dielectric layer 32a A layer of nitride (not shown) is formed on the surface to strengthen the bonding between the interfaces and improve the defects of the dielectric layer. With this, the component's low electric field leakage current (Leakage Current) and breakdown voltage (Breakdown Vo It age) can be improved, and the dielectric constant of the dielectric layer can be increased to about 25. Therefore, the capacitance value can be increased by about 2 〇% to 2 5%. Referring to FIG. 3E, another photoresist layer 34 is formed to cover the structure shown in FIG. 3D. Subsequently, the photoresist layer 3 4 is exposed and developed using the photomask 14 shown in FIG. 2B, and unnecessary portions are removed to form an opening 36 ′ to expose the dielectric layer 32 a and the substrate 20 so that light The resist layer 34 has a structure shown in FIG. 3E. Subsequently, a step of forming a conductive layer is performed, for example, a conductive layer is formed on the photoresist layer 34 using a base plating method or a chemical vapor deposition method and filled into the opening 36. After the conductor layer is filled into the opening 36, then, for example, a wet or dry stripping method is used to remove the photoresist layer 34 and the π --- 1 i II ------------ order --- ------ · (Please read the precautions on the back before filling this page) 1229445 A7 V. Description of the invention () The conductor layer on the photoresist layer 34, only .. A # "Remember the conductor in the opening 36" The layer j8a is formed as shown in Figure 3F, which is the structure of the electric metaphysics. Among them, 'this conductor layer core is a part of the electrode above the valley state of electricity, 1 ^ is any conductor material, For example, conductor layers such as polycrystalline stone or Ming, or composite structures such as gas silicon. Gasification Qin / Duo Yue Yue II # ^ 30 Figure, for example, formed by spin coating-a structure that does not include a layer of photoresistance layer 3F, Next, the photoresist layer 40 is exposed and developed using the photomask 10 ′ shown in FIG. 2B to form an opening π exposed portion of the dielectric layer 仏 and the conductor layer 38a. Then, the step of forming the dielectric layer is performed. For example, a chemical vapor deposition method or other deposition method is used to form a dielectric layer on the photoresist layer 40 and fill it in the openings. The dielectric layer is really opened 4 After 2 ', for example, a wet or dry stripping method is used to remove the photoresist layer 40 and the dielectric layer located on the photoresist layer 4 (), leaving only the dielectric layer 32b filled in the opening 42, and forming as The structure shown in Figure 3h. Among them, the material of the I electrical layer 32b is the same as that of the dielectric layer 32a. Generally, it can be any material with a high dielectric constant, such as tantalum pentoxide, titanium dioxide, silicon oxide / nitride oxide / stone oxide The invention is not limited to this. After the dielectric layer 32b is completed, another optional step can be used at high temperature, such as about 70 degrees Celsius. The nitriding step is performed on the dielectric layer 3 in a temperature environment of 0 ° to about 95 ° Celsius to a temperature and a nitrous oxide gas environment, so that a nitride (not shown) is formed on the surface of the dielectric layer to strengthen the interface. Bonding can improve the defects of the dielectric layer. As a result, 12 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210 (Please read the precautions on the back before filling this page). Install the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumer Cooperative 1229445 A7 B7 V. Description of the invention (The low electric field leakage current and breakdown voltage of the device can be improved, and the dielectric constant of the dielectric layer can be increased to about 25, so the capacitance value can be increased by about 20% to 25%. It can be seen that the present invention uses three types of photomasks, that is, the lower electrode photomask 12, the dielectric layer photomask 10, and the upper electrode photomask 14 shown in FIG. 2B, which are used alternately in a specific order to form a pleated type. Capacitor structure. Among them, the order of use of the photomask is the lower electrode photomask 12; the dielectric layer photomask 10; and the upper electrode photomask 14; and the dielectric layer photomask 10, respectively, and the capacitors are respectively formed under the capacitor. The electrode (conductor layer 26a), the capacitor's dielectric layer (dielectric layer 32a and dielectric layer 32b), and the electrode above the capacitor (conductor layer 38a). However, the present invention is not limited to only completing the above-mentioned structure, and the present invention can also continue the subsequent process according to actual needs, as follows: Next, referring to FIG. 31, a photoresist layer 44 is formed to cover the above structure ( (As shown in FIG. 3H), and then using the photomask a shown in FIG. 2B, the photoresist layer 44 is subjected to exposure and development steps, and unnecessary parts are removed to form -open. 46 'exposes the conductor layer 26a and the dielectric layer 32b: so that the photoresist layer 44 has the structure shown in FIG. 31. ^ The Bureau of Intellectual Property of the Ministry of Economic Affairs said that, subsequently, a step of forming a conductor layer is performed, such as forming a layer of a conductor layer on the resist layer 44 using a cash deposit method or a chemical vapor deposition method and filling the opening 46 into the opening. After 46, then, for example, the zhaozhao layer filling layer 44 and the conductive layer located above the photoresist layer 44 ”, and only the filling paper printed by the opening consumer society is kept in accordance with the Chinese National Standard (CNS) A4 specification. (21〇13 1229445. A7 V. Description of the Invention) The conductor layer 26b in (46) forms the structure shown in Figure 3J. Among them, 'This conductor layer 26b is a part of the electrode below the capacitor and its material It can be any conductive material, such as polycrystalline silicon or aluminum, or a composite structure such as titanium nitride / aluminum, titanium nitride / polycrystalline silicon. As mentioned above, when the material of the conductive layer 26b is polycrystalline silicon, The invention can also use the relationship between the lattice and temperature to form a small bump structure (not shown) on the surface of the conductor layer 2 6 b, thereby increasing the area of the contact electrode. With this bump structure, the present invention Capacitors comparable to traditional processes 2 × 5 times the contact area. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 3K to form another photoresist layer 4 8 to cover the structure shown in Figure 3 J. Then, use Figure 2B The photomask 14 shown performs an exposure and development step on the photoresist layer 48, and removes unnecessary portions, thereby forming an opening 50 'to expose the conductive layer 26b and the dielectric layer 32b, so that the photoresist layer 48 has a third K The structure shown in the figure. Subsequently, a dielectric layer formation step is performed, for example, a chemical vapor deposition method is used to form a dielectric layer on the photoresist layer 48 and fill it into the opening 50. Fill the opening 5 with the dielectric layer. 〇 Then, for example, using a wet or dry stripping method to remove the photoresist layer 48 and the dielectric layer 'on the photoresist layer 48', only the dielectric layer 32c filled in the opening 50 is left, and formed as 3L The structure shown in the figure. Among them, the material of the dielectric layer 32c is the same as that of the dielectric layer 3 2a-it can be any material with a high dielectric constant, such as tantalum pentoxide, titanium dioxide, silicon oxide / silicon nitride / silicon oxide , Gill barium titanate, lead gadolinium titanate, or silicon oxynitride, etc., the present invention When the dielectric layer 32c is completed, 'an alternative step is to use it at high temperature, for example, when taking 14 papers (CNS) A4 size ⑽χ Norwegian meal) ---- 1229445 A7 -----—-- 21___ 5. Description of the invention () ----.-- 111 — — ^ --- (Please read the notes on the back before filling out this page) About 7GG degrees to about 95 degrees Celsius 〇 High temperature and nitrous oxide gas environment! Electrical layer 32c is subjected to a nitriding heat treatment step, so that the surface of the dielectric layer is formed with a layer of nitride (not shown) to strengthen the bonding between interfaces, and can be modified . Defects in the dielectric layer. With this, the device's low electric field leakage current and breakdown voltage can be well improved, and the dielectric constant of the dielectric layer can be increased to about 25, so the capacitance value can be increased by about 20% to 25%.贽. Please refer to FIG. 3M to form another photoresist layer 52 to cover the structure not shown in FIG. 31. Subsequently, the photoresist layer 52 is exposed and developed using the photomask 14 shown in FIG. 2B, and unnecessary parts are removed, so as to form an opening 54 to expose the conductive layer 38a and the dielectric layer 32. The resist layer η has a structure shown in FIG. 3M. Subsequently, a step of forming a conductive layer is performed, such as using a sputtering method or a chemical vapor deposition method to form a conductive layer on the photoresist layer 52 and fill the opening 54. After the conductor layer is filled in the opening 54, for example, a wet or dry stripping method is used to remove the photoresist layer 52 and the conductor layer located on the photoresist layer 52, and only the conductor layer filled in the opening 54 remains: > 8b The structure is shown in Fig. 3N. Among them, this conductor layer 38b is a part of the electrode above the capacitor, and the material can be any conductor material printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, such as a polycrystalline silicon or aluminum conductor layer or titanium nitride / Composite structures such as aluminum, titanium nitride / polycrystalline silicon. As described above, 'The present invention can be followed up according to actual needs, so the structure of the present invention can be continuously stacked, depending on the actual required conditions. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇X 297) Meal) 1229445 A7 B7
五、發明說明（） 因為此後續製程實屬上述步驟之應用，因此為避免模糊本 發明之焦點，故不再贅述。 ---------:丨丨裝--------訂· (請先閱讀背面之注意事項再填寫本頁) 請參考第4圖，其繪示褶層數與電容值之關係。第4 圖係採用厚度50nm與l〇〇nm之介電層（Ta2〇5)來作比較， 由第4圖中可清楚發現褶層數與電容值是幾乎成正比線性 的關係，合乎預期之結果。由此可知，本發明確實可實行。 綜上所述，本發明之褶層型電容器是利用電容並聯 時，電容值相加的原理，實際應用而得。本發明之電容器 結構不僅可改善介電常數、介電層品質亦可以增加電極接 觸面積，以增加每一層的電容值。另外，上述製程僅為舉 例本發明之製程更可以應用在DRaMJi，如第5圖所示， 此時本發明之電容n 100則是藉由接觸窗1〇2而電性連接 至位在基板1〇4上之電晶體106。此DRAM之細部結構為 此技藝者所熟知，量可不再冗述。 本發明之一優點在提供一種在1(:製程上增加電容面積 的結構與方法，相對於—般增大面積的方法，冑較簡易的 經濟部智慧財產局員工消費合作社印製 製程步驟。此外’其下電極表面係經過粗糙化處理，因此 可進一步增加電容值。 本發明之另一優點在本發明之電容器可應用於例如晶 16 本紙張尺度ίδ用t國國家標準（CNS)A4規格H 297公爱)----------— 1229445 A7 B7 五、發明說明（） 片型電容、晶片型電容陣列等小型化被動元件，也町應用 於DRAM的記憶單元等需要單位面積電容值提高的ic製糕 上。 本發明之再一優點在提供一種電容器，其相較於如上 所述的習知電容器，因為本發明電容器中層與層的高度落 差較小，約小於1 500埃，所以有利於階梯覆蓋的能力。 如熟悉此技術之人員所瞭解的’以上所述僅為本發明 之較佳實施例而已，並非用以限定本發明之申請專利範 圍；凡其它未脫離本發明所揭示之精神下所完成之等效改 變或修飾，均應包含在下述之申請專利範圍内。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）V. Description of the invention () Because this subsequent process is actually an application of the above steps, in order to avoid obscuring the focus of the present invention, it will not be repeated here. ---------: 丨 丨 Installation -------- Order · (Please read the precautions on the back before filling this page) Please refer to Figure 4, which shows the number of pleats and capacitance Value relationship. Figure 4 uses a dielectric layer (Ta205) with a thickness of 50nm and 100nm for comparison. From Figure 4, it can be clearly found that the number of pleats and the capacitance value are almost linearly proportional, which is expected. result. It can be seen from this that the present invention is indeed feasible. In summary, the pleated capacitor of the present invention is obtained by practical application of the principle of adding capacitance values when capacitors are connected in parallel. The capacitor structure of the present invention can not only improve the dielectric constant and the quality of the dielectric layer, but also increase the contact area of the electrodes to increase the capacitance value of each layer. In addition, the above process is only an example. The process of the present invention can be applied to DRaMJi, as shown in FIG. 5. At this time, the capacitor n 100 of the present invention is electrically connected to the substrate 1 through the contact window 102. 〇4 上 电 晶 106。 On the transistor 106. The detailed structure of this DRAM is well known to those skilled in the art, and the amount can be omitted. One advantage of the present invention is to provide a structure and method for increasing the area of a capacitor in the 1 (:) process. Compared with the general method of increasing the area, the simpler printing process steps of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 'The surface of the lower electrode is roughened, so that the capacitance value can be further increased. Another advantage of the present invention is that the capacitor of the present invention can be applied to, for example, crystal 16 paper size, national standard (CNS) A4 specification H 297 public love) ------------ 1229445 A7 B7 V. Description of the invention () Miniature passive components such as chip capacitors and chip capacitor arrays, and memory cells used in DRAM, etc., require a unit area. The capacitance value is increased on the IC cake. Still another advantage of the present invention is to provide a capacitor, which is compared with the conventional capacitor described above, because the height difference between the middle layer and the layer of the capacitor of the present invention is small, less than about 1,500 angstroms, which is beneficial to the ability of step coverage. As understood by those familiar with this technology, 'The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application for the present invention; all other things that are completed without departing from the spirit disclosed by the present invention, etc. Effective changes or modifications should be included in the scope of patent application described below. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)