TWI228835B - Junction varactor - Google Patents

Abstract

A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor. Second heavily doped regions of the first conductivity type located in the first ion well at one side of the first dummy gate that is opposite to the first heavily doped region and at one side of the second dummy gate that is opposite to the first heavily doped region, the second heavily doped regions being electrically connected to each other and serving as a cathode of the PN junction varactor.

Description

1228835 V. Description of the invention (1) [Technical Field] I-The present invention is a general description of a variable capacitor (varactor), especially a PN that has both high quality factor (Q factor) and wide tuning range characteristics Interface with variable capacitor. When you wait, use the same image number. In this way, the cif pulse system can be used to control the video. Based on the steps of control, the basic information is used. The lack of the same purpose to make all the information and electricity are all pulsed or pulsed. The Telecommunications Association also deals with it.) The tffl from t is not the best, the taste is the best-one in the same ^, in the use of Chinese capital: ^ Road system is not a device, and the industry \ Electricity system I wave signal is It is also reported that the production, transmission, transmission, and transmission of three shocks, and the number of transmissions of the C number must be controlled. The news is that this is not a medium-sized device that can be used as a medium device. The accuracy rate of a certain industry is often controlled by the frequency of the production number. The required number is the j number of the block number of the T bit. The oscillating zizizi was shocked in the number of pulses, technical circuits, and time-adjusted transmission devices. The previous generation used the theory of telephony to transfer electricity surplus. It is now reasonable to produce roads in phase earthquake. t call the lock step in every case

1228835 V. Description of the invention (2) To be adjusted. A variety of variable capacitors have been developed for use in integrated circuit components, such as PN diodes, Schottky diodes and metal oxide semiconductors (me ta 1 ox i de sem i conduc tor, MOS). ) Transistor diodes are commonly used in bipolar transistor (bi po 1 ar juncti on transistor (BJT)) and complementary metal oxide semiconductor (comp 1 emen tary me ta 1 ox i de sem i conduc t or , CMOS) transistors and electronic components such as BiCMOS-BiCMOS

Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional structure diagram of a conventional junction variable capacitor. As shown in FIG. 1, an N-type ion 2 is formed in a p-type substrate “0” and a plurality of isolation structures 14, such as a shallow trench isolation (shal 10 tra i so 1 at i on, ST I) structure. The isolation structure 14 defines a plurality of predetermined regions on the surface of the N-type ion well 12 and is used to fabricate a doped region H ^ P-type doped region 18 to form a diode structure with a pN junction. Ϊ́ ΐ When a reverse bias is applied, the PN junction of the diode can be regarded as a medium ^ μ ^ ^ depletion region (dePleti〇n regi〇n), and the diode can be consulted ^ 2 5 1 6 , P-type doped regions, such as cathodes, and anode two conduction intervals. As the voltage across the anode and the cathode of the diode is adjusted, the width of the anode ^ f will change accordingly, and the purpose of changing the equivalent capacitance value provided between the diode and the cathode is achieved. Please refer to Figure 2, which is a schematic diagram of the surface structure. As shown

The second section of the conventional metal oxide semiconductor (M0S) variable capacitor is shown in Figure 2. The conventional M0S variable capacitor is formed at N

Page 9 1228835 V. Description of the invention (3) Type well 22 includes polysilicon gate structure 2 6. The gate dielectric layer 2 is located between polycrystalline silicon gate electrode structure 2 6 and _well 2 2 8. N + doped regions 24 located in the N-type wells 22 on both sides of the polycrystalline silicon gate structure 26, and in the N-type wells 22 on both sides of the polysilicon gate structure 26 and mixed with N + Region 24 is adjacent to a light & doped drain (LDD) 25. During operation, the crystalline silicon gate structure 26 is used as the anode of the variable capacitor, and the miscellaneous means is known to those skilled in the art. The conventional interface shown in FIG. 1 has a wide frequency modulation. The range (tuning range) is just its value, so the f factor is relatively low. The cJ transformer t shown in Figure 2 has a lower resistance value and a higher quality because of its main advantage, but its disadvantage is that it has a narrower frequency modulation range. As can be seen from the above, such as providing 0 good! Ϊ ί electric capacitor and < quality ^. The electrical performance of skin capacitors has become the direction of the current industry efforts. [Content] The capacity im: that is to provide-a kind of variable capacitor 'to improve the capacity i ΐ Ξ ΐ ί:: = i "M0S process compatible connection '' Enables both high quality factor Q and

1228835 V. Description of the invention (4) Wide frequency modulation range (t u n i n g r a n g e). According to a preferred embodiment of the present invention, a PN junction variable capacitor is provided, which includes a first N-type well disposed in a semiconductor substrate with a first gate electrode disposed on the first N-type well; A first gate dielectric layer is disposed between the first gate electrode and the first N-type well; a second gate electrode is disposed on the first N-type well on the side of the first gate electrode; Two gate dielectric layers are disposed between the second gate and the first N-type well; a Pf doped region is disposed between the first N and the first N Type / in-well, as the anode of the PN junction variable capacitor;-a first N + doped region, the first N type provided on the side of the first gate opposite to the P + doped region A well; and a second N + doped region, which is disposed in the first N-type well on the opposite side of the second gate and the P + doped region and is electrically connected to the first N + doped region , As the cathode (cath ode) of the PN junction variable capacitor. The P + doped region is covered by a second N-type well, and the doping concentration of the second N-type well is greater than that of the first N-type well. In operation, the first gate and the second gate are grounded. In order to make your reviewers understand the features and technical contents of the present invention more closely, please refer to the following detailed description and drawings of the present invention. However, the drawings are only for reference and auxiliary explanation, and are not intended to limit the present invention. 【method of execution】

1228835 V. Description of the invention (5V ^ ^ ^ ^ ^ ^ The following is a detailed description of the features of the present invention from Figures 3 to 7. The skilled artisan should understand the technical features of the present invention and understand the following ^ The element (conduct i V ty type) in the comparative embodiment of the present invention is exemplified and described, and it can be used as an equivalent converter instead of the protection scope of the invention. ^ First, please refer to FIG. 3 and FIG. Among them, FIG. 3 is a schematic top view of the layout of a preferred variable capacitor 80 interface according to the present invention, and FIG. 4 is a schematic diagram of a variable capacitor 80 interface along the tangent line AA in FIG. As shown, the junction variable capacitor 80 of the preferred embodiment of the present invention is formed on an N-type well 100, and the N-type well 100 can be formed on a P-type hair substrate or a silicon-based insulation (silicon- on-insul at or (SO I) on the surface of the substrate (not shown), and the N-type well 100 is isolated from the shallow trench isolation (ST I) region 2 0 0. If The N-type well 100 is formed in the SOI substrate, and a silicon oxide insulating layer (not shown) is formed below the SOI substrate. The domain 2 0 collectively electrically isolates the N-type well 100 into a floating (floating :) state. In the preferred embodiment of the present invention, the interface variable capacitor 80 includes a dummy polycrystalline silicon gate 101, which is located across Above the N-type well 100, and a dummy polysilicon gate 102, which is located above the N-type well 1 0 0 on the side of the dummy polysilicon gate 10 1. The dummy polysilicon gate 1 0 and the dummy polysilicon gate 1 0 2 Each has two vertical sidewalls, and spacers 101a and 102a are formed on the sidewalls, and a dummy polysilicon gate 101 and a dummy polysilicon gate are formed thereon.

1228835 V. Description of the invention (6h ^ ^ ^ ^ ^ — ~ The pole 102 is isolated from the warship _. A P + doped region is formed in the _ well 1 0 0 between the dummy polycrystalline sand gate W ^^ It is a gambling well. ”It is used as the anode of the junction variable capacitor 80, in which the doping concentration of N-type parallel 113 must be greater than that of N-type well 100. Doping 113 can use an additional Mask opening angle) ion implantation process is completed. One of the main features of the present invention is to cover the P + doped region 'η with an additional N-type well 113, which has the advantage that it can improve the figure of merit Q of the variable capacitor 80 and increase the tuning range. ). As shown in FIG. 4, an nv-doped region 114 and a τ N-type lightly doped drain electrode are formed in the N-type well 100 on the opposite side of the dummy polysilicon gate 丨 〇 丨 and the p + doped region 1 丨 2 ( The lightly doped drain (LDD) 121 is adjacent to the NV doped region 1 1 4 and extends laterally to the bottom of the dummy polycrystalline silicon gate electrode 1 〇1 sidewall 1 〇1 & In other embodiments, the N-type lightly doped drain electrode (NLDDM21 extends below the dummy polysilicon gate 101). On the opposite side of the dummy polycrystalline silicon gate 10 and the p + doped region 11 2 A v + doped region 1 16 and an N-type lightly doped drain (1 i gh 11 y doped dr ai η, LDD) 1 2 are formed in the gambling well 100 adjacent to the N + doped region 1 16 and laterally extend below the dummy polysilicon gate 102. In other embodiments, the lightly doped drain (NLDD) 122 extends below the dummy polysilicon gate 102. N + doped Regions 1 1 4 and N + doped regions 1 1 6 are electrically connected using interconnects to connect the cathode of the variable capacitor 80 to the junction. In addition, to reduce the chip current,

Page 13 l228835 V. Description of the invention (7) ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ '~~~ jtg ^ It is more difficult to form self-aligned metal stones in the P + doped region m. Evening compound (sa H cide) layer 103. From the cathode in Figure 4, it is found that compared with the conventional junction variable capacitor, there is no shallow trench insulation area barrier between the anode and the transformer, so the resistance value of the junction can be reduced. This improves the figure of merit. And after the operation. Set the polycrystalline shatter gates 10 1 and 10 2 to ground 1 to change the electrical system of the variable capacitor 80 by changing the anode 112 and the cathode 114/1 [6 ^ Brother integral surface ^ 'Please refer to Figure 5 to FIG. 7 and FIG. 5 to FIG. 7 show the main steps of preparing the junction variable capacitor 80 according to the preferred embodiment of the present invention as shown in the cross-sectional structure. The method of manufacturing the junction variable capacitor 80 of the present invention is CMOS up-range. As shown in Fig. 5, a substrate (not shown) is provided, the surface of which is connected to an N-shaped well 100, which is isolated by a shallow trench insulation area (not shown). An insulating layer (not shown) is formed on the N-type well 100, for example, gate silicon ^: and then a polycrystalline silicon layer (not shown) is deposited on the gate silicon oxide layer. The yellow light and rice carving process define the polycrystalline silicon layer and the insulating layer as two-pole structures 101 and 丨 02, and the insulating layers are shown below 10 lb and 6 respectively, and then NLDD ion implantation is performed, using an appropriate mask, ^ implant (photo) The region f between the gate structure 101 and 102 is masked ', and then arsenic ion implantation is performed to form a erbium-doped region 121 on one side of the gate structure 101 and 102. 122.

$ 14 pages 1228835 V. Description of the invention (8) As shown in Fig. 7, side walls (s ρ a c e r) 1 0 1 a and 1 0 2 a are formed on the side walls of the gate structures 101 and 102. Then, an appropriate mask (N + implant pho t 〇) is used to mask the area between the P4 pole structure 101 and 102, and then N + ion implantation is performed to apply the gate structure 101 and 102. N + doped regions 11 4 and 116 are formed on one side. Finally, a ^ f and two ion implantation processes are applied to the gate structure 丨 〇 丨 and 丨 〇2 ^ + doped region 1 1 2 and coating? The structure in the + doped region 112] continues the self-aligned silicide process, which is shown in FIG. 4 as the variable capacitor 80 of the present invention.

Any changes and modifications made to the scope of application of the present invention that are specifically covered by the patent of the present invention are merely equivalent to the scope of the present invention's better actual benefits.

1228835 Brief description of the diagram Brief description of the diagram Figure 1 is a schematic cross-sectional view of a conventional junction variable capacitor. FIG. 2 is a schematic cross-sectional structure diagram of a conventional metal-oxide semiconductor variable capacitor. FIG. 3 is a schematic top view of a layout of a variable capacitor at a junction according to a preferred embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of the variable capacitor along the tangent line AA in FIG. 3. Figures 5 to 7 show cross-sectional structures of the main process steps for manufacturing the planar variable capacitor of the preferred embodiment of the present invention as shown in Figure 4. Symbols of the drawings: 12 ion wells 16 doped regions 2 2 N-type wells 25 lightly doped; and pole 28 gate dielectric layer 100 N-type well 101a, side wall 102 dummy polycrystalline sand 102t 1 gate dielectric Layer 10 substrate 14 isolation structure 18 doped region 24 N + doped region 26 polycrystalline silicon gate structure 80 junction variable capacitor 101 dummy polycrystalline silicon gate 101b gate dielectric layer 1 0 2 a side wall 103 self-aligned metal silicide Object layer 112 P + doped region 113 N-type well 114 N + doped region 1 17 N + doped region

1228835 Schematic description

2 0 0 STI 3 0 0 P + / N + ion implantation mask open

BlB Page 17

Claims (1)

1228835 Six 'patent application scope 1. A PN junction variable capacitor includes: a first N-type well disposed in a semiconductor substrate; a first gate electrode disposed on the first N-type well; a first A gate dielectric layer disposed between the first gate electrode and the first N-type well; a second gate electrode disposed on the first N-type well on the side of the first gate electrode; a second A gate dielectric layer is provided between the second gate and the first N-well: :: a P + doped region provided on the first gate between the first gate and the second gate An N-type well serves as the anode of the PN junction variable capacitor; a first N + doped region is provided in the first N-type well on the side of the first gate opposite to the P + doped region And a second N + doped region is provided in the first N-type well on the opposite side of the second gate and the P + doped region, and is electrically connected to the first N + doped region as the Cathode of PN interface variable capacitor. 2. The PN junction variable capacitor according to item 1 of the scope of patent application, wherein the P + doped region is covered by a second N-type well, and the doping concentration of the second N-type well is greater than the Doping concentration of the first N-type well. 3. The PN junction variable capacitor according to item 1 of the patent application scope, wherein the PN junction variable capacitor further includes a first N-type lightly doped drain (NLDD), which is disposed on the first N-type In the well, it is adjacent to the first N + doped region and extends laterally below the first gate. 1228835 on page 18 Six 'patent application scope 4. The PN junction variable capacitor described in item 1 of the patent scope, wherein the PN junction variable capacitor further includes a second N-type lightly doped drain (NLDD) ), Located in the first N-shaped well adjacent to the i-laterally extending below the second gate 5. The PN junction variable capacitor as described in the first item of the patent application scope ^ its ^ the first gate and the first gate There is a spacer on each side wall of the two gates. 6. The PN junction variable capacitor as described in the first paragraph of the patent application park, wherein the first gate, the second gate, the The first N + doped region, the second N + doped region, and the P + doped region further have a self-aligned metal silicide (sa 1 ici de) layer. 7. The PN junction variable capacitor as described in item 1 of the scope of the patent application, wherein the first gate and the second gate are grounded during operation. 8. A variety of PN junctions are variable. The capacitor includes a first ion well, which is of a first conductivity type, and is provided in a second conductivity type semiconductor substrate; a first dummy gate is provided on the first ion well; A first gate dielectric layer disposed on the first dummy gate and the first ion Page 19, 1228835 VI. Scope of patent application ^ —— Together; a second dummy gate, a second-cavity dielectric layer on the side of the first dummy gate, located in Tandong ^ ^ ^ A first heavily doped region, which is an anode of the first separation plane variable capacitor between a closed electrode and a second dummy gate; and a second heavily doped region, which is The first conductivity type r is provided with a gate electrode, and the second dummy gate electrode and the first ion well on one side of the second conductivity type are used as cathodes of a variable capacitor at the mPN interface. The PN junction variable capacitor according to item 8, wherein the first conductive type is referred to as N-type, and the second conductive type is referred to as P-type. 1 〇 The PN junction variable capacitor as described in item 8 of the scope of patent application, wherein the first dummy gate and the second dummy gate are grounded during operation. Page 20 1228835 6. Scope of patent application 12. As described in item 8 of the scope of patent application? 1 ^ junction variable capacitor, wherein the PN junction variable capacitor further includes a lightly doped drain (LDD), which is disposed in the first ion well, adjacent to the second heavily doped region, and extends laterally to the Below the first dummy gate / the second dummy gate. 13. The PN junction variable capacitor according to item 8 of the scope of the patent application, wherein each side wall of the first dummy gate and the second dummy gate has a spacer. Page 21