TWI224363B - Manufacturing method for semiconductor pitch - Google Patents

Abstract

The present invention provides a manufacturing method for semiconductor pitch, which includes the following steps: first, providing a substrate; sequentially forming a gate oxide layer, a polysilicon layer, and patternized SiN layer on the substrate, wherein the patternized SiN layer has a first pitch and several first openings, and the size for each first opening is one fourth of the first pitch; forming a patternized oxide layer to fill up the first opening and cover part of the patternized SiN layer, wherein the patternized oxide layer has a first pitch and several second openings, and the second openings are alternately arranged with the first openings below, and the size of the second opening is one fourth of the first pitch; removing the exposed patternized SiN layer to form another patternized SiN layer, and the patternized SiN layer has a second pitch, several third openings and first openings, and the second pitch is one half of the first pitch, and the first openings are alternately arranged with the third openings, and the size for each third opening is a half of the second pitch; and, removing the patternized oxide layer and the exposed first polysilicon layer to form a first patternized polysilicon layer with the second pitch.

Description

1224363 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a kind of semiconductor pitch (pitch); it is ancient, i ^ 1 ^ 4-and especially it relates to a Manufacturing method of semiconductor pitch smaller than the step-sweep specification of the machine. [Previous technology] 7In the era of rapid technological development, electronic devices have become a reality: an integral part of human life. Among them The electronic device can be operated. In that, 'because it is equipped with an integrated circuit (integrated c 1 r = U 1 7' 1C) 'such as logic 1C and memory 1 c. These ICs must be manufactured by U It ’s privately done, and in the semiconductor process, has lithography technology been the most challenging and difficult part of the process? With the continuous improvement of the scanner, the exposure wavelength is continuously improved. In order to make 0.25-018 micron ("m) process technology, the wavelength of the stepping scanner is 248 nanometers (nm), and the pitch of 248 nanometers can be made. Nowadays, the semiconductor industry is regarded as the latest competitive target of the 0.13 micron process technology. The wavelength of the step scanner equipment required has been increased to 193 nanometers (nm), but it can only make a pitch of 193 nanometers. . Qing Fen according to Figures 1 A to 1 C, which is a cross-sectional view showing the flow of a traditional semiconductor pitch manufacturing method. First, in FIG. A, a substrate 102, such as a silicon substrate, is provided, and a gate oxide layer 104 is formed on the substrate 102. Next, a polycrystalline silicon layer 106 is formed on the gate oxide layer 104, and a patterned photoresist layer 112 is formed on the polycrystalline silicon layer 106, as shown in FIG. 1B. The patterned photoresist layer 11 2 has a pitch p 1 and several openings 1 11. The size s j of the openings 丨 丨 1

TW1108F (Wanghong) .ptd Page 5 1224363

V. Description of the invention (2) It is a half of the pitch P1, and the vertical pitch P1 is the sum of the line width (1 ine width) W1 and the size S1 of the opening 211. For example, when using a stepping scanner with a wavelength of 193 nanometers for lithography, the pitch pi will be 200 nanometers, and the line width W1 and the size S1 of the opening 211 will both be 〇〇〇 奈. Meter. Then, the exposed polycrystalline silicon layer 106 is removed at a later time, and the patterned photoresist layer 丨 2 is removed to form a patterned polycrystalline silicon layer 106a, as shown in FIG. 1C. The knot \ ρι is still V 200 nm, and the line width W1 and the size Sl of the opening 211 are 100 nm. ~ 'Under the current trend of electronic devices pursuing light and short and high-speed signal transmission, the semiconductor pitch will be smaller than 200 nanometers, and even reach 100 nanometers, resulting in the current lithography technology will be insufficient. ❶But if: step = scanner function, the conductor industry will also pay a huge amount of money: "So, how to use the existing lithography technology to obtain semiconductors with even smaller pitch specifications" will be urgently needed to be solved ΐ [Invention [Contents] In view of this, the purpose of the manufacturing method of the present invention can obtain a step semiconductor pitch, which can increase the upgrade cost of the semiconductor scanner. What is needed is to provide a semiconductor pitch design standard with a smaller pitch specification for the scanner and a body pitch, and save steps according to the purpose of the present invention. First, a substrate is provided. on. Then, a first polycrystalline-patterned silicon nitride layer is formed on the first substrate, which is a semiconductor pitch manufacturing method. Next, a gate oxide layer is formed on the substrate and a gate oxide layer is formed on the substrate. Next, a polycrystalline stone layer is formed, and a patterned silicon nitride layer is formed.

1224363 V. Description of the invention (3) There is a first pitch and several first openings, and the size of each first opening is a quarter of the first pitch. Then, a patterned oxide layer is formed to fill the first opening and cover a portion of the patterned silicon nitride layer. The patterned oxide layer has a first pitch and several second openings. The first openings are staggered, and the size of the second openings is a quarter of the first pitch. Then, the exposed patterned silicon nitride layer is removed to form another patterned silicon nitride layer, and the patterned silicon nitride layer has a second pitch, a plurality of third openings, and a first opening. The distance is half of the first pitch, the first openings are staggered with the third openings, and the size of each third opening is half of the second pitch. Then, the patterned oxide layer is removed. Then, the exposed first polycrystalline silicon layer is removed to form a first patterned polycrystalline silicon layer, and the first patterned polycrystalline silicon layer has a second pitch. According to still another object of the present invention, a method for manufacturing a semiconductor pitch is proposed. First, a substrate is provided. Then, a gate oxide layer is formed on the substrate. Next, a patterned polycrystalline silicon layer is formed on the gate oxide layer. The patterned polycrystalline silicon layer has a first pitch and a plurality of first openings, and the size of each opening is a quarter of the first pitch. Then, a first patterned polymer layer is formed to fill the first opening and cover a portion of the patterned polycrystalline silicon layer. The first patterned polymer layer has a first pitch and a plurality of second openings. The first openings below are staggered, and the size of the second openings is a quarter of the first pitch. Then, the exposed patterned polycrystalline silicon layer is removed to form another patterned polycrystalline silicon layer, and the patterned polycrystalline silicon layer has a second pitch, a plurality of third openings, and a first opening, and the second pitch is the first pitch. Half, the first opening is staggered with the third opening, and the size of the third opening is the second

TW1108F (Wang Hong) .ptd Page 7 1224363 V. Description of the invention (4) Half of the pitch. According to another object of the present invention, a method for manufacturing a semiconductor pitch is proposed. First, a substrate is provided. Then, a gate oxide layer is formed on the substrate. Next, a polycrystalline silicon layer is formed on the gate oxide layer. Then, a first patterned silicon nitride layer is formed on the polycrystalline silicon layer. The first patterned silicon nitride layer has a first pitch and a plurality of first openings. The size of the first opening is one quarter of the first pitch. One. Then, a patterned oxide layer and a second patterned silicon nitride layer are formed. The patterned oxide layer fills these first openings and covers a portion of the first patterned silicon nitride layer to pattern the oxide layer. It has a first pitch and several second openings. The second openings are staggered with the first openings below. The size of the second opening is a quarter of the first pitch, and a second patterned silicon nitride layer is formed in the second opening. Then, the second patterned silicon nitride layer and a part of the first patterned silicon nitride layer are removed to form a third patterned silicon nitride layer. The third patterned silicon nitride layer has a second pitch, a number Third openings and first openings. The second pitch is a half of the first pitch, the first opening is staggered with the third opening, and the size of the third opening is half of the second pitch. Then, the patterned oxide layer is removed. Then, the exposed polycrystalline silicon layer is removed to form a patterned polycrystalline silicon layer, and the patterned polycrystalline silicon layer has a second pitch. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: [Embodiment]

TW1108F (Wang Hong) .ptd Page 8 1224363 V. Description of the invention (5) Embodiment 1 Please refer to Figures 2A to 2L, which shows the semiconductor device pitch according to the first embodiment of the present invention. ) Of the manufacturing method. First, in FIG. 2A, a substrate 202 such as a silicon substrate is provided, and a gate oxide layer 204, a first poly silicon layer 206, and the like are sequentially formed on the substrate 202. A silicon nitride (Si 1 icon nitride) layer 208, a second polycrystalline silicon layer 210, and a patterned photo resist layer 212. The patterned photoresist layer 2 1 2 has a pitch P1 and several openings 2 11. The size S1 of the opening 2 11 is one-half of the pitch P1, and pi is the size of the line width (Hne width) W1 and the opening 211. The sum of S1. For example, when a lithographic operation is performed by a stepping scanner (sca η ner) with a wavelength of 193 nanometers (nm), the pitch p 1 is 200 nanometers (nm), and the line width W1 and the opening 211 The sizes S1 are all 100 nanometers (nm). In addition, in this embodiment, an anti-reflection dielectric coating (DARC) can be formed between the nitride nitride layer 208 and the second polycrystalline silicon layer 210 or the silicon nitride layer 208 and the first polycrystalline silicon. The Shixi layer 206 is used to increase the integrity of the patterned photoresist layer 212 when it is formed. &

Next, 'trimming' the patterned photoresist layer 212 to form a trimmed photoresist layer 212a, as shown in FIG. 2B. In FIG. 2B / the trimmed photoresist layer 21 2a has a pitch pi and a plurality of openings 213, and the size S2 of the openings 213 is about the pitch? Three quarters, such as 150 nanometers. The line width W2 is a quarter of the pitch Pj, such as 50 nm. Then, the silicon nitride layer 208 is used as an etch stop layer for the second polycrystalline silicon layer 210, and the rainstorm is removed.

1224363 V. Description of Invention (6) The second polycrystalline silicon layer 2 1 0 and the second patterned polycrystalline silicon layer 2 1 Oa will be formed, which is completed by dry etching, as shown in FIG. 2C. In FIG. 2C, the second patterned polycrystalline silicon layer 21a has a pitch P1 and a plurality of openings 215. The size S3 of the openings 215 is equal to three-quarters of the pitch P1, such as 150 nm. After the second patterned polycrystalline silicon layer 21a is formed, the trimmed patterned photoresist layer 212a may be subsequently removed. Next, a polymer layer 2 1 4 is formed by a polymer chemical vapor deposition (CVD) method. The polymer layer 2 1 4 is covered with a trimmed photoresist layer 2 1 2 a and nitrogen. The chemical layer 208 is shown in FIG. 2D. In FIG. 2D, the polymer layer 214 has a pitch P1 and a plurality of notches 217. The notches 217 are located in the center of the opening 21 5 in FIG. 2C. The size S4 of each notch 217 is the fourth of the pitch P1. One-half, such as 50 nanometers. The reason why the polymer chemical vapor deposition method is adopted in the present invention is that the polymer chemical vapor deposition method has a wider process window (plasmr enhanced chemical vapor deposition (PECVD)) than the traditional plasma enhanced chemical vapor deposition (PECVD) method. window), can provide a polymer layer in the form of anisotropic deposition. That is to say, the thickness of the polymer layer 214 on the trimmed photoresist layer 2a-2a is greater than the thickness of the polymer layer 214 under the notch 215, which is not possible with PECVD. In addition, because the polymer chemistry = phase and the product process temperature are room temperature, it can protect the integrity of the photoresist layer 2 h after trimming, which is also a difficult factor for PECVD for high temperature processes. Then, the first polycrystalline silicon layer 206 is used as the silicon nitride layer 208 during the etching.

1224363 V. Description of the invention (7) Stop layer, and remove part of the polymer layer 214 and part of the silicon nitride layer 208 under the notch 217, the patterned silicon nitride layer 208a and the patterned polymer layer 21 4a It will be completed by an anisotropic last name, as shown in Figure 2E. . The patterned silicon nitride layer 208a has a pitch P1 and a plurality of openings 21 9. The size S 5 of the openings 21 9 is one quarter of the pitch P1, such as 50 nm. Next, the patterned polymer layer 214a and the trimmed photoresist layer 212a are removed, and a plurality of trenches 221 are formed on the first polycrystalline silicon layer 206. An oxide layer 2 1 6 is then formed by a high density plasma (HDP) deposition method, as shown in FIG. 2F. In FIG. 2F, the oxide layer 21 6 fills the trench 2 2 1 and covers the second patterned polycrystalline silicon layer 2 1 a. Then, the oxide layer 2 1 6 is planarized to form a patterned oxide layer 2 1 6a, and the second patterned polycrystalline silicon layer 2 1 0a is exposed, which is chemical mechanical polishing (CMP) or back. The etch-back is completed, as shown in Figure 2G. In FIG. 2G, the patterned halide layer 21 6a just fills the trench 221, and the top surface of the patterned oxide layer 21 6a is coplanar with the top surface of the second patterned polycrystalline silicon layer 21a. Next, the second patterned polycrystalline silicon layer 210a is removed, so that the patterned oxide layer 21 6a has a pitch P1 and a plurality of openings 223, as shown in FIG. 2H. In FIG. 2H, the openings 223 of the patterned oxide layer 216a are staggered with the openings 2 1 9 of the patterned nitride layer 2 0 8 a below. The size S 6 of the openings 2 2 3 is the fourth of the pitch P1. One-half, such as 50 nm. Then, the exposed patterned silicon nitride layer 208a is removed to form another patterned silicon nitride layer 208b, as shown in FIG. In FIG. 21, the patterned nitride stone layer 2 0 8 b has a pitch P 2, a plurality of openings 2 2 5 and 2 1 9,

TW1108F (Wang Hong) .ptd Page 11 1224363 V. Description of the invention (8) The pitch P2 is one half of the pitch pi, such as 100 nm. The opening 225 is staggered with the opening 219, and the size of the opening 225 is equal to one-half of the pitch P2, such as 50 nm. Next, the patterned oxide layer 2 1 6a is removed, as shown in FIG. 2J. Then, the exposed first polycrystalline silicon layer 206 is removed to form a first patterned polycrystalline silicon layer 206a, as shown in FIG. 2K. In Fig. 2K, the first patterned polycrystalline silicon layer 206a has a pitch P2, such as 100 nm. Next, the patterned silicon nitride layer 208b is removed, as shown in FIG. 2L. In FIG. 2L, the line width W1 0 of the first patterned polycrystalline silicon layer 2 06 a and the size S1 0 of the opening are both half of the pitch P2, such as 50 nm. Therefore, the present invention can obtain a semiconductor pitch smaller than the pitch specification of the existing step scanner, and can save the upgrade cost of the step scanner. Second Embodiment Reference is made to Figs. 3A to 3, and the margins are cross-sectional views showing the flow of a method for manufacturing a semiconductor pitch according to the second embodiment of the present invention. First, in FIG. 3A, a substrate 302, such as a silicon substrate, is provided, and a gate oxide layer 304, a polycrystalline silicon layer 306, and a nitrogen are sequentially formed on the substrate 302. Fossil evening layer 308 and patterned photoresist layer 312. The patterned photoresist layer 312 has a pitch of π and several openings = 311, the size S1 of the opening 3n is one half of the pitch ρ, and η is the sum of the size s 1 of the line W1 and the opening 2 11. For example, when using a wavelength of 9 nm to a scanner to perform lithography, the pitch? 1 is 200 nm, and the line width W1 and the size S1 of the opening 211 are both 100 nm. Then, the patterned photoresist layer 312 is cut to form a trimmed photoresist 312a, as shown in FIG. 3B. Trimmed photoresist layer 312 & has pitch "and

TW1108F (Wang Hong) .ptd Page 12 5. Description of the invention (9) Several openings 313, the size S2 of the opening 313 is three quarters of the pitch P1, such as 150 nm. However, the line width W2 is a quarter of the pitch P1, such as 50 nm. Then, the exposed nitride layer 308 is removed to form a patterned nitride layer 308a, as shown in FIG. 3C. In FIG. 3C, the patterned nitrided stone layer 308a has a pitch P1 and a plurality of openings 315. The size S3 of the openings 315 is three-quarters of the pitch P1, such as 150 nm. Next, a polymer chemical vapor deposition method is used to form a polymer layer 314, as shown in FIG. 3D. In FIG. 3D, the polymer layer 314 is a polycrystalline silicon layer 306 covering the portion and the trimmed photoresist layer 312a. The polymer layer 314 has a pitch P1 and a plurality of notches 317. The notch 317 is located at the center of the opening 31 5 in Fig. 3C. The size S4 of the notch 317 is a quarter of the pitch P1, such as 50 nm. Then, a part of the polymer layer 3 丨 4 and a part of the polycrystalline stone layer 306 ′ under the notch 3 1 7 are removed to form a patterned polymer layer 314 a and a patterned polycrystalline silicon layer 306 a, as shown in FIG. 3E. . In FIG. 3E, the patterned polycrystalline silicon layer 30 6a has a pitch P1 and a plurality of openings 319, and the size S5 of the openings 319 is a quarter of the pitch P1, such as 50 nm. Next, the patterned polymer layer 3 1 4 a and the trimmed photoresist layer 3 1 2 a are removed to form a plurality of trenches 3 2 1 on the gate oxide layer 3 0 4. A polymer layer 3 1 6 is formed to fill the trench 3 2 1 and cover the patterned nitrided layer 308a, as shown in FIG. 3F. In FIG. 3F, the polymer layer 316 is, for example, a bottom anti-reflective coating (BARC) °. Then, the polymer layer 3 1 6 is planarized to form a patterned polymer. The layer 3 1 6 a, and the patterned nitrided stone layer 3 0 8 a is exposed, which is completed by a cash back method, as shown in FIG. 3G. Next, the patterned silicon nitride layer 308 is removed, so that

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Does the patterned polymer layer 316a have a pitch? 1 and several openings 323, as shown in FIG. 3H. The openings 323 of the patterned silicon nitride layer 308a are staggered with the openings 319 of the patterned polycrystalline silicon layer 306a below. The size% of the openings 323 is a quarter of the pitch P1, such as 50 nm. Next, the exposed patterned polycrystalline silicon layer 306a is removed to form another patterned polycrystalline silicon layer 30p, as shown in FIG. 31. The patterned polycrystalline silicon layer 306b has a pitch ", several openings 325 and 319, and the pitch P2 is a half of the pitch P1, such as 100 nm. The opening 325 is staggered with the opening 319, and the opening 325 The size S7 is a half of the pitch p2, such as 50 nm. Then, the patterned polymer layer is removed, as shown in FIG. 3J. Among them, the line width wi of the patterned polycrystalline silicon layer 306b and the opening The size S1 0 is half of the pitch P 2, such as 50 nm. Therefore, the present invention can obtain a semiconductor pitch smaller than the pitch specification of the existing step scanner, and can save the step scanner. The upgrade cost. The sum of S1 in the third embodiment. For example, when using a stepping scanner with a wavelength of 193 nanometers to perform lithographic operations, the pitch P1 is 200 nanometers, and the line width "and the opening 411 are large. Referring to FIGS. 4A to 4K, a flow cross-sectional view of a method for manufacturing a semiconductor pitch according to a third embodiment of the present invention is shown. First, in FIG. 4a, a substrate 402, such as a silicon substrate, is provided, and a gate oxide layer 404, a polycrystalline silicon layer 406, a first nitride layer 408, and The second silicon nitride layer 409 and a patterned photoresist layer 412. The patterned photoresist layer 412 has a pitch P1 and several openings 4U. The small si of the opening 4U is half of the pitch pi, and P1 is the size of the line width W1 and the opening 411.

TW1108F (Wang Hong) .ptd Page 14 1224363 V. Description of the invention (11) The small S1 are all 1 ο 0 nm. Next, the patterned photoresist layer 412 is trimmed to form a trimmed photoresist layer 412a 'as shown in FIG. 4B. In FIG. 4B, the trimmed photoresist layer 412a has a pitch P1 and a plurality of openings 413. The size S2 of the openings 413 is about three-quarters of the pitch pi, such as 150 nm. However, the line width W2 is one quarter of the pitch P1, such as 50 nm. Then, the exposed portion of the second silicon nitride layer 409 'is removed to form a second patterned silicon nitride layer 409 & as shown in the first generation diagram. The first patterned 1 fossil evening layer 409a has a pitch P1 and a plurality of openings 415 '. The size S3 of the openings 415 is equal to three quarters of the pitch pi, such as HQ nanometer. ^ Next, a polymer chemical vapor deposition method is used to form a polymer layer 414 ′. The polymer layer 414 covers the trimmed photoresist layer 412a and a portion of the first silicon nitride layer 408, as shown in FIG. 4D. The polymer layer 414 has a pitch ρ and a plurality of notches 417. The notches 417 are located at the center of the opening 415 in FIG. 4C. The size of the notch 417 is S4 which is a quarter of the pitch P1, such as 50 nm. level. Then, the polymer layer 414 under the notch 417 and the first silicon nitride layer 408 are removed to form a first patterned silicon nitride layer 408a and a patterned polymer layer 414a. Figure 4E. The first patterned nitrided layer 408a has a pitch ^ and a plurality of openings 419 ', and the size S5 of the opening 419 is a quarter of the pitch P1, such as 50 nm. Next, the patterned polymer layer 414a and the modified photoresist layer 412a are removed to form a plurality of trenches 421 on the polycrystalline silicon layer 406. Then, an oxide layer 416 is formed by a high-density electrodeposition method. The oxide layer 416 fills the trench 421 and covers the second patterned fossil layer 409a, as shown in FIG. 4F. Say

1224363 V. Description of the invention (12) Then, the oxide layer 416 is planarized to form a patterned halide layer 416a, and a second patterned silicon nitride layer 409a is exposed, which is completed by chemical mechanical polishing or etch-back. , As shown in Figure 4G. Next, the second patterned silicon nitride layer 409a and the first patterned stone nitride layer 408a below it are removed to form a third patterned silicon nitride layer 408b, as shown in FIG. 4H. The third patterned silicon nitride layer 408b has a pitch P2, several openings 423, and openings 419, and the pitch P2 is a half of the pitch P1, such as 100 nm. The opening 4 2 3 is staggered with the opening 4 1 9. The size S 6 of the opening 4 2 3 is equal to one-half of the pitch P2, such as 50 nm. Then, the patterned oxide layer 41 6 a is removed, as shown in FIG. 4I. Then, the exposed polycrystalline silicon layer 406 is removed to form a patterned polycrystalline silicon layer 406a, as shown in FIG. 4J. The patterned polycrystalline stone layer 406a has a pitch P2, such as 100 nm. Next, the third patterned silicon nitride layer 408b is removed, as shown in FIG. 4K. The line of the patterned polycrystalline silicon layer 406a sees W10 and the size of the opening S10 are both half of the pitch P2, such as 50 nm. The method for manufacturing a semiconductor pitch disclosed in the above embodiments of the present invention can obtain a semiconductor pitch that is smaller than, or even half the semiconductor pitch specification of a stepping scanner. In this way, the design pitch of the semiconductor pitch can be increased, and many upgrade costs used as a stepping scanner can be saved, which is quite economical. In summary, 'Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention should be regarded as defined by the scope of the attached patent application as im

1224363

TW1108F (Wang Hong) .ptd Page 17 1224363 Brief Description of Drawings [Simplified Description of Drawings] Figures 1 A to 1 C are cross-sectional views showing the flow of the traditional manufacturing method of semiconductor pitch. Figures 2A to 2L are cross-sectional views showing the flow of a method for manufacturing a semiconductor pitch according to the first embodiment of the present invention. Figures 3A to 3J are cross-sectional views showing the flow of a method for manufacturing a semiconductor pitch according to the second embodiment of the present invention. Figures 4A to 4K are cross-sectional views showing the flow of a method for manufacturing a semiconductor pitch according to the third embodiment of the present invention. Description of reference numerals 102, 202 > 302, 402: substrates 104, 204, 304, 404: gate oxide layers 106, 30 6, 406: polycrystalline silicon layers 106a, 306a, 306b, 406a: patterned polycrystalline silicon layer 111 ^ 211 > 213 > 215 ^ 219 ^ 223 ^ 225 ^ 311 > 313, 315, 319, 323, 325, 411, 413, 415, 419, 423: Open σ 112, 212, 312, 412: Patterned photoresist layer 2 06: first polycrystalline silicon layer 2 06a: first patterned polycrystalline silicon layer 208, 308: silicon nitride layer 208a, 208b, 308a: patterned silicon nitride layer 2 1 0: second polycrystalline silicon layer 2 1 0 a: second patterned polycrystalline silicon layer

TW1108F (Wang Hong) .ptd Page 18 1224363 Brief description of the drawings 212a, 312a, 412a: Trimmed photoresist layer 214, 314, 316, 414: Polymer layer 214a, 314a, 316a, 414a: Patterned polymer layer 216, 416: oxide layers 216a, 416a ... patterned oxide layers 217, 317, 417: notches 221, 321, 421: trenches 408: first silicon nitride layer 408a: first patterned silicon nitride layer 408b · Third patterned silicon nitride layer 409: Second silicon nitride layer 409a: Second patterned silicon nitride layer

TW1108F (Wanghong) .ptd Page 19

Claims (1)

1224363 VI. Application for Patent Scope 1. A method for manufacturing a semiconductor pitch at least includes: providing a substrate; forming a gate oxide layer on the substrate; forming a first polycrystalline silicon layer on the gate oxide layer Forming a patterned silicon nitride layer on the first polycrystalline silicon layer, the patterned silicon nitride layer having a first pitch and a plurality of first openings, and the size of each of the first openings is the first A quarter of the pitch; forming a patterned oxide layer to fill the first openings and cover a portion of the patterned silicon nitride layer, the patterned oxide layer having the first pitch and a plurality of Second openings, each of which is equal to a quarter of the first pitch, and the second openings are staggered with the first openings below; removing the exposed patterned nitrogen Silicon layer to form another patterned silicon nitride layer, and the patterned silicon nitride layer has a second pitch, a plurality of third openings, and the first openings, and the second pitch is the first Half the pitch, the size of each third opening is Half of the second pitch, the first openings are staggered with the third openings; removing the patterned oxide layer; and removing the exposed first polycrystalline layer to form a first patterning A polycrystalline silicon layer, the first patterned polycrystalline silicon layer having the second pitch. 2. The method according to item 1 of the scope of patent application, wherein the method comprises the step of forming a patterned silicon nitride layer on the first polycrystalline silicon layer and further comprising: TW1108F (Wanghong) .ptd Page 20 1224363 6. Application scope: forming a silicon nitride layer on the first polycrystalline silicon layer; forming a second polycrystalline silicon layer on the silicon nitride layer; forming a A patterned photoresist layer is on the second polycrystalline silicon layer, the patterned photoresist layer has the first pitch and a plurality of fourth openings, and each of the fourth openings has a size equal to half of the first pitch. One; trimming the patterned photoresist layer to form a trimmed photoresist layer, the trimmed photoresist layer having the first pitch and a plurality of fifth openings, and the size of each of the fifth openings is the first Three quarters of the pitch; removing the exposed second polycrystalline silicon layer to form a second patterned polycrystalline silicon layer, the second patterned polycrystalline silicon layer having the first pitch and a plurality of sixths Openings, the size of each of the sixth openings is three-quarters of the first pitch; a polymer layer is formed by a polymer chemical vapor deposition (polymer CVD) method, and the polymer layer covers a portion of the nitrogen Silicon layer and the trimmed photoresist layer 'The polymer layer has the first pitch and a plurality of Notches, each of which is located in the center of each of the sixth openings, the size of each of the notches is a quarter of the first pitch; and the polymer layer from which a portion under the notches is removed And part of the nitrided oxide layer to form a patterned polymer layer and the patterned nitrided stone layer. The method described in Shi Shenqing's patent scope item 2, wherein the method is in the step of forming a patterned oxide layer further comprising: ', removing the patterned polymer layer and the trimmed photoresist layer, and This ditch is aligned with Xi 隹 a ^ / Zaimu on the 4th polycrystalline silicon layer; Hi Nan Density Plasma (hi gh dens i ty p 1 asma, hop) deposition 1224363 6. The scope of the patent application method is to form an oxide layer. The oxide layer fills the trenches and covers the second patterned polycrystalline stone layer. The oxide layer is planarized to form the patterned oxide. Layering and exposing the second patterned polycrystalline silicon layer; and removing the second patterned polycrystalline silicon layer, so that the patterned oxide layer has the first pitch and the second openings. 4. The method according to item 3 of the scope of patent application, wherein the method further comprises: planarizing the oxide layer by a chemical mechanical polishing (CMP) method Floor. 5. The method according to item 3 of the scope of patent application, wherein the method further comprises: flattening the oxide layer by an etch-back method. 6. The method according to item 1 of the scope of patent application, wherein the method is after the step of forming a first patterned polycrystalline stone layer further comprising: removing the other patterned nitrided stone layer. 7. The method as described in item 1 of the scope of patent application, wherein the substrate is a chopped substrate. 8. The method according to item 1 of the scope of patent application, wherein an anti-reflection coating (DARC) can be formed on or over the patterned silicon nitride layer. 9 A semiconductor A method for manufacturing a pitch includes at least: providing a substrate; forming a gate oxide layer on the substrate; TW1108F (Wang Hong) .ptd Page 22 1224363 6. The scope of the patent application forms a patterned polycrystalline silicon layer on the gate oxide layer. The patterned polycrystalline silicon layer has a first pitch and a plurality of first openings. The size of an opening is a quarter of the first pitch; a first patterned polymer layer is formed to fill the first openings and cover a portion of the patterned polycrystalline silicon layer, and the first patterned polymer The object layer has the first pitch and a plurality of second openings, each of the second openings is a quarter of the first pitch, and the second openings are staggered with the first openings below And removing the exposed patterned polycrystalline silicon layer to form another patterned polycrystalline silicon layer, and the patterned polycrystalline silicon layer has a second pitch, a plurality of third openings, and the first openings, the second pitch It is half of the first pitch, and the size of each of the third openings is half of the second pitch. The first openings are staggered with the third openings. 10. The method according to item 9 of the scope of patent application, wherein the method comprises the step of forming a patterned polycrystalline silicon layer on the gate oxide layer, further comprising: forming a polycrystalline silicon layer on the gate oxide layer; forming A silicon nitride layer on the polycrystalline silicon layer; forming a patterned photoresist layer on the silicon nitride layer, the patterned photoresist layer having the first pitch and a plurality of fourth openings, each of the fourth openings The size is one-half of the first pitch; trimming the patterned photoresist layer to form a trimmed photoresist layer, the trimmed photoresist layer having the first pitch and a plurality of fifth openings, The size of each of the fifth openings is three-quarters of the first pitch; TW1108F (Wang Hong) .ptd Page 23 1224363 6. The scope of the patent application removes the exposed silicon nitride layer to form a patterned silicon nitride layer, and the patterned nitride layer has the first pitch and a complex number Six sixth openings, each of which has a size equal to four of the first pitch, forms a second polymer layer by a polymer chemical vapor deposition method, and the polymer layer covers part of the A polycrystalline silicon layer and the trimmed photoresist layer, the second polymer layer has the first pitch and a plurality of notches, each notch is located in the center of each sixth opening, and the size of each notch is A quarter of the first pitch; and removing the second polymer layer under the notches and the multi-layered layer of the portion to form a second patterned polymer layer and the pattern Huayue said ^ Riri > 5 Xi layer. 11. The method as described in item 10 of the scope of patent application, wherein the method further comprises the step of forming a first patterned polymer layer: removing the second patterned polymer layer and the trimmed light A barrier layer to form a plurality of trenches on the gate oxide layer; forming a first polymer layer, the first polymer layer filling the trench and covering the patterned nitride layer; planarizing the first layer A polymer layer to form the first patterned layer and expose the patterned silicon nitride layer; and remove the patterned silicon nitride layer from the material. Wherein the method engravs the first polymer layer. The method described in item 9 of the patent scope, wherein the method 1224363 6. The scope of patent application is after the step of removing the exposed patterned polycrystalline silicon layer, further comprising: removing the first patterned polymer layer. 14. The method described in item q of the scope of patent application, wherein the far substrate is one; the 6th substrate. 15. The method as described in item 9 of the scope of patent application, wherein the first patterned polymer layer is a bottom anti-reflection coating (BARC) 〇16 · A method for manufacturing a semiconductor pitch At least includes: providing a substrate; forming a forming a forming a patterned nitrided first opening to form a patterned oxide and a patterned nitrogen; a plurality of second staggered arrangements; one, the second removing the cased silicon nitride The siliconized silicon nitride is 'an opening', and the gate oxide layer is gate-oxidized on the substrate on the polycrystalline silicon layer. The first patterned nitride layer has a first pitch. The layer has a size of patterned layer 4 The openings of the dagger layers, each of the second patterned second layers, each layer has an oxide layer with the second pitch of the first pitch and one fills the first, the patterned oxygen, and the second openings have the size of the two openings. The silicon nitride layer is formed into a third nitride layer and a second pitch layer, and the distance is on the first layer layer. Opening in the second and second figures, the compound layer and the The brother was born in In the following scheme, the first first openings are formed on a plurality of two-layer silicon silicon layers with nitrogen, and each case covers nitrogen and covers the silicon silicon layer. The first opening is one quarter of the third opening of the third part of the siliconized silicon layer; the first drawing, the third drawing, and the third openings are each ! 224363 The size of the six-patent application range is half of the second pitch, the first openings are staggered with the second openings; removing the patterned oxide layer; and removing the exposed polycrystalline stone Layer to form a patterned polycrystalline stone layer, and the patterned polycrystalline silicon layer has the second pitch. v 1 7 · The method described in item 16 of the scope of patent application, wherein the method further comprises the step of forming a first patterned nitrided stone layer on the polycrystalline stone layer. Forming a Forming a first silicon nitride layer on the polycrystalline silicon layer; forming a second silicon nitride layer on the first silicon nitride layer; > forming a patterned photoresist layer on the second silicon nitride layer, The patterned photoresist layer has the first pitch and a plurality of fourth openings, and the size of each of the fourth openings is one-half of the first pitch; ^ repairing the patterned photoresist layer to form A trimmed photoresist layer, the photoresist layer after the repair has the first pitch and a plurality of fifth openings, and the size of each of the fifth openings is three-quarters of the first pitch; A second silicon nitride layer to form a second patterned nitrogen layer> the second patterned nitride layer has the first pitch and a plurality of first and / or openings; each of the sixth openings is Three quarters of the first pitch; a polymer chemical vapor deposition method (po 1 ymer CVD) is used to form a t-layer layer; the polymerization Layer covering part of the first silicon nitride layer and the f $ rear photoresist layer 'the polymer layer has the first pitch and a plurality of notches', each of the notches is located at the positive of each of the sixth openings In the center, the size of each notch is a quarter of the first pitch; and page 26 TW1108F (Wang Hong) .ptd 1224363 Sixth, the scope of the patent application removes the polymer layer under the notches And a portion of the first silicon nitride layer to form a patterned polymer layer and the first patterned silicon nitride layer. 18. The method as described in item 17 of the scope of patent application, wherein the method further comprises: removing the patterned polymer in the step of forming a patterned oxide layer and a second patterned silicon nitride layer Layer and the trimmed photoresist layer to form a plurality of trenches on the polycrystalline silicon layer; an oxide layer is formed by a high density plasma (HDP) deposition method, and the oxide layer is filled Fill the trenches and cover the second patterned nitrided layer; and planarize the oxide layer to form the patterned oxide layer and expose the first patterned ratified layer. 19. The method as described in item 18 of the scope of patent application, wherein the method further includes, in the step of planarizing the oxide layer, planarizing the chemical mechanical polishing (CMP) method. Oxide layer. 2 0. The method as described in item 18 of the scope of patent application, wherein the method further includes the step of planarizing the oxide layer: planarizing the oxide by a etch-back method Floor. 21. The method according to item 16 of the scope of patent application, wherein the method is after the step of forming a patterned polycrystalline stone layer further comprising: removing the second patterned nitrided stone layer. 2 2 · The method according to item 16 of the scope of patent application, wherein the substrate TW1108F (Wang Hong) .ptd Page 27 1224363 6. Scope of patent application It is to cut the substrate. Page 28 TW1108F (Wang Hong) .ptd