TWI223081B - Peak voltage detector with output stage - Google Patents

Abstract

A peak voltage detector having a novel framework is proposed in the present invention. The invention is composed of a differential amplifier 1, a charging transistor 2, a capacitor C and an output stage 3. The differential amplifier 1 is designed to have an asymmetric structure where only single side load transistor is used. In addition, the load transistor together with the charging-transistor 2 forms a current mirror. The differential amplifier 1 is used as a comparator. The charging transistor 2 is used as a charger to provide the required charging current for the capacitor. The output stage 3 is used to adjust the voltage signal V(C) of the capacitor C so as to accurately output the peak voltage of the inputted signal. In addition to accurately detecting the peak voltage of the inputted signal, the proposed peak voltage detector of the invention has multiple functions such as simple circuit structure, small chip-occupation area and advantage for device miniaturization. Additionally, an output stage is disposed so as to effectively prevent the held peak input voltage from being destroyed due to the access action of the external circuit.

Description

1223081 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a voltage peak detector, especially using a differential amplifier, a charging transistor, a capacitor, and A complementary metal-oxide-semiconductor (CM0s) electronic circuit composed of an output stage to obtain precise voltage peaks. [Prior art] The voltage peak detector is an electronic circuit that can measure the maximum value of a voltage waveform. The quality of the circuit is “input-variable voltage signal of this circuit” and its output is the voltage waveform of the human.

In fiber evening applications, the peak value of the input voltage signal must be measured, and then it should be kept in the DC type for subsequent analysis and use. The peak value of a burst is often more useful than its average value. For example, when performing a destructive test, it is necessary to track down and maintain the peak measurement. The amount of attenuation of the pressure signal on the transmission medium, analog to digital converter ⑽c 〇; jte likeiih 〇d dec〇ding Prior art towels, relying on peaks and seldom do tricks = diodes, and charge the capacitor in order to obtain the peak value of the input voltage waveform.

As shown in the second figure, when the input voltage v⑽ is greater than the voltage of the capacitor c, the second shop ^ ^, D charging action 'until the input cake v (_ reaches its maximum value, the output voltage when the electric H 聊 T) means the output. The peak of human sugar. ° " As shown in the second picture, the picture has unpredictable consequences. There are differences, but this can cause adverse effects or to determine the peak value of the lost person. In addition, the previous technique used 5 1223081. Two operational amplifiers 0P1 and 0P2, two diodes D1 and The two resistors ri and R2 and one capacitor c constitute a voltage peak detector, as shown in the third figure; the simulation results of the transient analysis of PSp1Ce are shown in the fourth figure. Among them, 〇ρι is a precise wave rectifier. When the input voltage is larger than the capacitor voltage V (C), the diode_transmission capacitor C1 is charged, and finally the capacitor voltage v (c) will be equal to the input voltage. The peak voltage of () = When approached, the detected output electric game (T) will also be quite close to the peak dragon of the input office. 'There will no longer exist between the output terminal and the input terminal as shown in the second figure. -Error of diode on voltage Vd. When the input voltage ^ ⑽ is smaller than the capacitor voltage, the diode will be turned on, and the diode D1 will be turned off and the capacitor c will no longer be charged. This makes the detected output voltage V (0UT) It is equal to the peak voltage of the input voltage. Although the electric peak detector of the third figure can accurately detect the peak voltage, its circuit structure is complicated and the occupied area of the chip is large, which is not conducive to the requirements of the integrated circuit. So far, many voltage peak detector technologies have been proposed, such as those disclosed in U.S. Patent Cases Nos. 304939, 5502746, 5560027, 5969545, 6051998, 6064238, and 6462861, and the Republic of China Patent Case No. 88219066 All of them, these technologies can accurately detect the peak voltage of the incoming signal, but because these voltage peak detectors use more than one operational amplifier, there are complex circuit structures and large chip area. Is missing. Recently, a variety of inaccurate precision dust detectors using op amps have been listed as disclosed in the Republic of China Patent Case No. 90119722 and No. 1188. The 4th class technology is -differential amplifier and- The circuit composed of the current mirror replaces the operational amplifier. Since the operational amplifier is not used, it has multiple functions such as a simple circuit structure, an occupied chip area it, and a favorable miniaturization of the device. However, because the differential amplifiers used in these technologies are called two load transistors and use independent galvanometers, there is still room for improvement in reducing the number of transistors required for power and value. In addition, these technologies set up an output stage in the value detector. The output stage can effectively maintain the input peak voltage when the detected input peak voltage is captured by an external pan, so as not to reduce the damage caused by the desired action. . · This is the main purpose of the present invention is to propose a novel voltage peak detector with a novel architecture, which not only accurately detects the peak value of the input signal, but also has a simple transfer structure and a small chip area of 6 1223081. And it is conducive to multiple functions such as miniaturization of the device. At the same time, a wheel-out stage is also provided to effectively prevent the operation of the external circuit of the S from causing damage to the voltage value of the listening field. [Summary of the invention] The voltage peak detector provided by the present invention is composed of a differential amplifier i, a charging transistor 2, a capacitor C, and an output, and a stage 3. The differential amplifier is asymmetric The structure is based on the material, that is, only one-sided zenith crystal is used, and the zener-carrying transistor and the charging transistor together form a current mirror, so it can be two less than the traditional precision voltage peak detector. Crystal. In addition, the voltage peak detector provided by the present invention is provided with an output stage, so it can not only prevent the held input peak voltage from being damaged due to the capture of external circuits, but also accurately adjust and output all The function of keeping the input peak voltage. [Embodiment] According to the above object, the present invention provides a novel voltage peak detector, as shown in the fifth figure, which is composed of a differential amplifier 1, a charging transistor 2, a capacitor ^; and an output It is composed of stage 3. The differential amplifier 1 is designed using an asymmetric circuit configuration. It is composed of a blue transistor leg, MN2 and MN3, and a PM0S transistor MP1. Among them, the _s transistor MN1 and MN2 are used as drivers, the PMOS transistor MΠ is used as a load transistor, and the NMOS transistor M just provides a reference current to the differential amplifier. The gates of the _s transistors MN1 and MN2 respectively receive the input voltage signal V (IN) and the voltage signal V (C) on the capacitor. The sources are connected together and connected to NM〇s. The drain of the transistor MN3 is connected to the load transistor Μρι and the power supply voltage vdd respectively; the gate of the NMOS transistor MN3 is connected to the power supply voltage Vdd, and the source is grounded. Please refer to the fifth figure again, the load transistor MP1 and the charging transistor MP2 together form a current mirror, and the source of the PM0S transistor MP1 and MP2 are connected to the power supply voltage vdd, and the gate is connected together, and Connected to the drain of NM0S transistor MN1, and the gate and drain of the PM0S transistor MP1 are connected together to form a current mirror; furthermore, the drain of pM0s transistor Mp2 and the capacitor One terminal of C is connected, and the other terminal of the capacitor C is grounded. In addition, the output stage 3 is composed of an NMOS transistor MN4 and a resistor R, and is connected between the power supply voltage Vdd and the ground. When the input voltage V (IN) is greater than the voltage ν (〇) on the capacitor, the current id (MN1) will be greater than 7 1223081

Id (MN2), and (1)

Id (MN1) + Id (MN2) = id (MN3) and

Id (MN1) = -Id (MP1) ⑵ Because the PMOS transistor MP1 and MP2 are constituted by a current mirror, -Id (MP1) = -Id (MP2) (3) ′, the capacitor C can be charged. When the voltage V (C) on the capacitor is equal to the peak voltage of the input voltage V (IN), the current Id (MN1) = Id (MN2) = y Id (MN3) (4) 'At this time, the capacitor C will still be charged action. According to the transfer characteristic curve of the differential amplifier, it is known that the voltage v (c) on the capacitor must be greater than the input peak voltage vp—over-overvoltage (〇verSh (X) tVc) itage_v〇s) in order to convert ^ jM〇s The crystal MN1 forces the stop g, f should be on the crystal surface. When the wire is stopped, the charging transistor stops charging the capacitor c. At this time, the voltage v (c) on the capacitor is V (C) = Vpeak + V〇S ⑸ Because the NM0S transistor MN2 works in the saturation region, and the NM0S transistor MN1 enters the cut-off region from the saturation region, VGS2 & VGS1 can be obtained from the following equation: ⑹ ⑺

Id (MN2) = Id (MN3)

Id (MN1) = 0 so the excess voltage Vos is equal to

Vos = VGS2-VGS1 (8), when the input voltage V (IN) drops from the peak voltage Vpeak, because the NM0S transistor MN1 has entered the cut-off state, the current -Id (MP1) = -Id (MP2) = 0 ⑼ Therefore, the charging transistor will no longer charge capacitor C, so the voltage% on the capacitor will remain fixed at the voltage of equation (5). Please refer to the fifth figure again. After the voltage V (C) on the capacitor deducts the gate-source voltage VGS4 of a NM0S transistor mm, it becomes the output voltage of the voltage peak detector ν (〇υτ), which is V ( OUT)-V (C)-VGS4 (10) 8 1223081 Next, we know from equations (5) and (10) that if the output voltage V (0UT) is to be equal to the input peak voltage Vpeak, we must VGS4 = Vos ( 11) Finally, since the drain current Id (MN4) of the NM0S transistor MN4 is a function of the gate-source voltage VGS4 and the drain-source voltage VDS4, the channel width-to-length ratio of the NM0S transistor Li 4 in the output stage 3 (W / L) and the resistance value of the resistor R must satisfy the following equations: (Vdd-VDS4) / r = Id (MN4) (⑵ With this, the voltage peak detector can be easily designed. The present invention The OrCADPSpice transient analysis simulation results of the proposed voltage peak detector are shown in Figures 6 and 7, which can accurately and effectively detect the peak voltage of the input voltage waveform. Figures 6 and 7 use 0 · 35 microns The CMOS process parameters are simulated, and the PM0S transistors MP1, MP2, and NM0S transistors are dirty, and the channel width-to-length ratio of Li 2 is (W / LM0 · 3 5μιη / 0.35), the channel width-length ratio of the NM0S transistor MN3 is (W / LH0 · 35μπι / 0_ 35μπι * 30), and the channel width-length ratio of the NM0S transistor Li4 is (¥ / 1 > (25 * 0.35_ / 0.35), and the resistance value of the resistor 1? Is between 0.7_um and 1.25M ohm. The voltage peak detector of the present invention can be connected in parallel with a switch at both ends of the capacitor c when in use This open relationship is used to provide a discharge path to discharge the charge stored on the capacitor, which is beneficial to the peak detection of the next input voltage signal. [Effect of the invention] The voltage peak detector proposed by the present invention only uses 2 pM0s transistors and ^ @ NM〇s transistors, and 1 capacitor H and 丨 resistors, which not only have a small number of relays, are fresh, use a small number of transistors, occupy a small area of the chip, and can Accurately detect the peak value of the input voltage waveform. At the same time, because the voltage peak detector of the present invention does not use an operational amplifier, it is also conducive to the miniaturization of the device. In addition, the voltage peak detection proposed by the present invention The device is equipped with an output stage, so it can also avoid the The input peak voltage will not be damaged due to the capture action of the external circuit, and at the same time, it will also adjust and input the peak input voltage function of Linlin. Although the present invention discloses and describes the selected preferred embodiment, However, anyone skilled in the art can understand that any form or detail of possible changes does not depart from the spirit and scope of the present invention. Therefore, all changes in the related technical scope are included in the scope of patent application of the present invention. 9 1223081 [Brief description of the diagram] = The diagram shows the circuit diagram of the voltage miscellaneous detector of the prior art towel; the third diagram of the signal is the circuit diagram of the voltage peak detector of the second prior technique;: signal The fourth figure is the timing chart of the input voltage signal analysis of the third peak voltage detector. The sixth circuit of the circuit = :; the peak voltage detector of the electric sequence pressure graph peak detector-the input voltage signal and the wheel of the peak pressure detector of the seventh graph [component symbol description] 2 charging transistor V (IN) input voltage signal V (〇 UT) output voltage signal D pole body D2-pole body R2 resistor 0P1 operational amplifier MP1 first PM0S transistor MN1 first NM0S transistor MN3 third NM0S transistor Vdd power supply voltage 1 differential amplifier 3 output stage V ( C) Voltage signal on the capacitor c Capacitor D1 Diode R1 Resistor R Resistor 0P2 Operational amplifier MP2 Second PM0S transistor MN2 Second NM0S transistor MN4 Fourth NM0S transistor 10

Claims (1)

1223081 Patent application scope: 1. A voltage peak detector for detecting the peak value of an input voltage signal, comprising: an input terminal for providing an input voltage signal; an output terminal for outputting the input voltage The peak voltage of the signal; a power supply voltage to provide the power supply voltage and reference ground required by the voltage peak detector; a differential amplifier 1 with a unilateral load transistor to accept and compare the input voltage signal and the capacitor And a charging current signal to the charging transistor; a charging transistor 2 for providing a current amount and the like according to the amount of current flowing through the unilateral load transistor of the differential amplifier 1; A capacitor C; one end of the capacitor is connected to the charging transistor 2 so as to receive the charging current supplied by the charging transistor 2 and the other end is connected to a reference ground; and an output stage 3, Connected between one end of the capacitor c and the output of the voltage peak detector to adjust the voltage signal on the capacitor C so as to accurately Peak output voltage of the input voltage signals. 2. The voltage peak detector according to item 1 of the scope of patent application, further comprising: a switch connected in parallel with the capacitor in a far-open relationship to provide a discharge path for discharging the charge stored on the capacitor It is good for the peak detection of the next input voltage signal. 3. The voltage peak detector according to item 2 of the scope of patent application, wherein the open relationship is composed of a gold-oxygen semiconductor. 4. The voltage peak detector according to item 1 of the scope of the patent application, wherein the differential amplifier 1 with a single-sided load transistor p includes: a single-sided load transistor, which is a first PM0S transistor MP1 The source of the first PM0S transistor MP1 is connected to the power supply voltage, the gate and drain are connected together and connected to the gate of the charging transistor 2; a first NMOS transistor Li 1 and its source It is connected to the source of the second transistor 08 and the drain of the third NMOS transistor MN3. The gate is used to receive the input voltage signal, and the drain is connected to the gate of the charging transistor 2 and the first A drain of the PM0S transistor MP1 is connected; a source of the second NMOS transistor Li 2 is connected to the source of the first NMOS transistor Li 1 and the third electrode of the third NMOS transistor Li 3, The gate is used to receive the voltage signal from the capacitor, and the 121223081 pole is connected to the power supply voltage; and a third NMOS transistor is connected to the reference ground, the gate is connected to the power supply voltage, and the pole Connected to the first and second NMOS transistor legs and the source of Li 2; The gate of body 2 is connected; and the output stage 3 includes: The charging transistor 2 is composed of a second PM0S transistor MP2, and the source of the second PM0S transistor MP2 is connected to the power supply voltage. —The p-cell electrical brain is connected to the drain of the first transistor MN1, and the drain is connected to one end of the capacitor and the second transistor A resistor R 'is connected to the output of the voltage peak detector. The gate is connected to one of the capacitors and the drain is connected to the power supply voltage. A resistor R is connected between them. Output terminal and reference ground 12