TWI222725B - Flip-chip package bonding structure and the manufacturing method thereof - Google Patents
Flip-chip package bonding structure and the manufacturing method thereof Download PDFInfo
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- TWI222725B TWI222725B TW092115073A TW92115073A TWI222725B TW I222725 B TWI222725 B TW I222725B TW 092115073 A TW092115073 A TW 092115073A TW 92115073 A TW92115073 A TW 92115073A TW I222725 B TWI222725 B TW I222725B
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Description
1222725 五、發明說明(1) 【發明所屬之技術領域】 本發明是關於一種·覆晶構裝接合結構及其製造方法, 特別是關於一種使用異方性導電接著劑之覆晶構裝接合結 構及其製造方法。 " 【先前技術】1222725 5. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip-chip bonding structure and a method for manufacturing the same, and particularly to a flip-chip bonding structure using an anisotropic conductive adhesive. And its manufacturing method. " [Previous Technology]
伴隨著電子產品朝向輕、薄、短、小、高速化與高機 能化之發展趨勢,而使得半導體元件構裝技術對於增加元 件可罪度、接合送、度以及減少元件尺寸方面的要求不斷提 高,因此傳統打線接合(wire bonding)逐漸被覆晶構裝 (f Π p - c h i p)技術所取代。 覆晶構裝技術係以晶片與基板的接合面形成銲球陣列 (array 〇f s〇ider ball)或是導電凸塊(bump)以取代習知 構裝技術所使用的導線架(leaci frame)。透過直接壓合晶 片與基板的接合面之間的銲球陣列(array 〇f s〇lder α曰曰With the development trend of electronic products toward lighter, thinner, shorter, smaller, higher speed and higher performance, the requirements of semiconductor component mounting technology for increasing component guilt, joining, reducing, and reducing component size continue to increase. Therefore, traditional wire bonding is gradually being replaced by f Π p-chip technology. The flip-chip mounting technology is to form a solder ball array (array oc soeder ball) or a conductive bump at the joint surface of the wafer and the substrate to replace the lead frame used in the conventional mounting technology. The array of solder balls (array 〇f s〇lder α) is directly bonded between the bonding surface of the wafer and the substrate.
ball)或導電凸塊來達成電路導通,可降低晶片與基板間 的電子訊號傳輸距離,適用於高速元件的封裝。習知的覆 =構裝方法,係於晶片及基板的表面形成導電凸塊(bump) 荨接合結構,然後在基板表面塗佈接著劑;再將晶片及基 $表面的導電凸塊經過對位壓合以完成覆晶構裝結構。在 曰曰片與基板間使用接著劑加以接合時,由於兩者具有嚴重 2膨脹係數差異,當溫度產生變化肖,熱應力的影響容 易使晶片及基板的導電凸塊接點產生變形。 為了減少接著劑、基板和晶片間:熱膨脹係數差異以 及增加接點的強度,可在膠材中混入適當的粒子以調整接ball) or conductive bumps to achieve circuit conduction, which can reduce the electronic signal transmission distance between the chip and the substrate, and is suitable for packaging high-speed components. The conventional covering = construction method is to form a conductive bump structure on the surface of the wafer and the substrate, and then apply an adhesive on the surface of the substrate; then, the conductive bumps on the surface of the wafer and the substrate are aligned. Press to complete the flip-chip structure. When an adhesive is used to bond the wafer and the substrate, the two have a severe difference in expansion coefficient. When the temperature changes, the effect of thermal stress can easily deform the conductive bump contacts of the wafer and the substrate. In order to reduce the difference between the adhesive, the substrate and the wafer: the difference in thermal expansion coefficient and increase the strength of the contact, appropriate particles can be mixed in the adhesive to adjust the contact
1222725 五、發明說明(2) 著劑之熱膨脹係數差異,並可在接著劑中添加適當濃声 導電粒子,以形成異方性導電揍著劑(Anis〇tr〇pic -之1222725 V. Description of the invention (2) Difference in thermal expansion coefficient of the adhesive, and appropriate concentrated conductive particles can be added to the adhesive to form an anisotropic conductive adhesive (Anis〇tr〇pic-of
Conductive Film,ACF)。但是在極細間距的情況下, 方性導電接著劑之導電粒子容易聚集於接點之側面而產、 相鄰接點短路的情形,因此其所能應用之線寬和間生 限。 又 【發明内容】 為解決先前技術的問題,本發明提供一種 合結構及其製造方法,在晶片盥 冓衣接 胲,以阻絕接點之間因導電接著劑之 =:緣 ,路”,罐構裝接合結構能應用= 距之元件覆晶構裝。 深見兴細間 本發明揭露一種使用異方性導電接覆曰 合結構及其製造方法,係利用元件盥美=J復日日構1接 緣膜以隔、絕其側“電性導 ^ ς ^妾點側面之絕 覆於接點側面直接阻隔導電性接著 結構係由基板、元件及異方 其覆晶構裝接合 板表面形成複數個接合墊以作為基板 =乂、:二 面形成複數個導電凸塊,導雷 '電、、泉路,兀件表 其導電凸塊壓合於基板之a則面係形成一絕緣膜, 性導通;&包含有複數個導;粒子二:成基板與元件之1 充於基板和元件之接合區域以電性連:if接著劑’係’、 此外.,本發明更包含覆 ^妾基板與元件。、, 衣接合結構的製造方法’Conductive Film, ACF). However, in the case of extremely fine pitch, the conductive particles of the square conductive adhesive are easily gathered on the side of the contact, and the adjacent contact is short-circuited. Therefore, the applicable line width and interval are applicable. [Summary of the Invention] In order to solve the problems of the prior art, the present invention provides a composite structure and a method for manufacturing the same. The wafer is connected to the bathroom to prevent contact between the contacts due to the conductive adhesive. The structure of the bonding structure can be applied = the element flip-chip structure of the distance. The present invention discloses a composite structure using anisotropic conductive bonding and its manufacturing method, which utilizes the beauty of the component = J 日 日 日 架 1 border membrane compartment in contact, which side must "guide ^ ς ^ electrically insulating flanking concubine side contacts directly overlying the conductive adhesive barrier structure is formed by a plurality of substrate, and the anisotropic element which flip chip package board engaging surface The bonding pads are used as the substrate = 基板,: a plurality of conductive bumps are formed on the two sides, and the conductors are electrically conductive, and the springs are formed. The conductive bumps are pressed against the a of the substrate to form an insulating film. Continuity; & Contains a plurality of conductors; Particle 2: Forms the substrate and the component 1 and fills the joint area between the substrate and the component to electrically connect: if the adhesive 'system', In addition, the present invention further includes a substrate With components. 、, Manufacture method of clothing joint structure ’
第6頁 1222725 五、發明說明(3) 係在上述之元件和基. 接合墊;於每一導雷几么表面分別形成複數個導電凸塊與 面塗佈異方性導電接著:側成膜;同時於基板表 方性導電個接合塾後壓合,並且固化異 墊之間而導致短路,故子也可能堆積於基板的接合 膜。 文於基板之接合墊侧面形成一絕緣 了解^ s: ί ^ H目的、構造特徵及其功能有進-步的 鉍配口圖不砰細說明如下: 【實施方式】 根據本發明所揭霖> @ s 法’係為解決使用異^桃=阳構t接合結構及其製造方 其間距縮小時所容易產^,接者劑以接合元件與基板’ 接合。 牛¥體封衣及組裝結構,特別是晶片與基板的 接著=較; 結構示意,其包含ί 為本發明第—實施例之 電凸塊11 〇,苴莫帝 日日片10 〇,其表面具有複數個導 A^ 2私凸塊110之侧面係具有絕緣膜in ; — 0,其表面具有複數(個接 1 接著劑120,係為含有導電粒子121之高分子材料方5 Μ基板20 0係以面對面的方式接合使複數個導電凸塊Page 6 1222725 V. Description of the invention (3) It is based on the above components and bases. Bonding pads; a plurality of conductive bumps are formed on the surface of each lightning guide and anisotropic conductive is coated on the surface. ; At the same time, the substrate is bonded to the surface of the conductive conductive bonding pads, and the short-circuit is caused by curing the different pads, so the child may also be deposited on the bonding film of the substrate. The following describes an insulating layer on the side of the bonding pads of the substrate. S: ί ^ The purpose, structural features, and functions of the bismuth profile are described in detail below: [Embodiment] According to the present invention >; @ s method 'is to solve the problem of using a different bonding structure and its manufacturing side, which are easy to produce when the pitch is reduced. The connection agent is used to bond the component to the substrate. The structure and assembly structure, especially the bonding between the wafer and the substrate, is a schematic structure, which includes the electric bumps 11 of the first embodiment of the present invention, and the sun-dried film 100, the surface of which The side with a plurality of conductive A ^ 2 private bumps 110 has an insulating film in; — 0, and the surface has a plurality of (a 1 followed by an adhesive 120, which is a polymer material containing conductive particles 121 5 μm substrate 20 0). Are connected in a face-to-face manner to make a plurality of conductive bumps
第7頁 1222725 五、發明說明(4) 1 二個別:二合=复數個接合塾21 °之上而形成電性導通。 如導電凸塊或接合墊,带士 P i板之接點的侧面, 昱,豆妒绦腊、 形成、、、巴 '、、彖膜。依製程或應用的差 圍= :刀佈形式可配合調整,如僅塗佈於接點周 片表面僅露出接合處,即填充於各: 合塾之間的間隙。請參考第2圖和第3 圖/、為本枭明之絕緣膜分佈示意圖。 如第2圖所示,絕緣膜丨丨形 導電凸塊110周圍。 于值开/成於曰曰片100表面之 人第3ΛΛ示’絕緣膜⑴係形成於晶片100之整個接 泛表面,即填充於各·導雷 丧 S # Λ撿Ί Ί Π+ 電塊1 1 〇之間的間隙,僅露出 ¥電凸塊110導電接合面。 ^ 請參ϊίΓΛ接^構的料膜可由多種方法加以製作, 丙〆又伞叫/弟圖,其為絕緣膜之製作流程示意圖。係 配合先被影技術以製作絕緣膜。 係 如弟4圖所示,提供^一 Byinn ... 導電凸塊11。,並於晶片、10〇V面:‘在其表面形成複數個 ln 、,n h 日日片100表面塗佈光阻材料作為絕緣膜 111,亚且完全覆蓋導電凸塊11()。 絮暝 凸示’使用光罩130曝光晶片100表面之導電 凸塊11 0 ‘電接合面的區域。 如第6圖所* ’顯影光阻材料之圖案使其於 no側面形成絕緣膜⑴,並露出導電凸塊11G的導 f 面〇 ° 此外亦可使用鍍膜後機械研磨方式形成絕緣膜,請Page 7 1222725 V. Description of the invention (4) 1 Two individual: Two-in- plurality of joints 塾 21 ° above to form electrical conduction. Such as conductive bumps or bonding pads, the side of the contacts of the Pi board, Yu, bean jealousy wax, forming ,,,,,,,,,,,, and 彖 film. Depending on the process or application, the range =: knife cloth can be adjusted according to the application. For example, if it is only applied to the surface of the contact surface and only the joint is exposed, it is filled in the gap between each joint. Please refer to Fig. 2 and Fig. 3 /, the schematic diagram of the distribution of the insulation film for this example. As shown in FIG. 2, the insulating film is formed around the conductive bump 110. The person on the surface of the film 100 / the third person ΛΛ shows that the insulating film ⑴ is formed on the entire surface of the wafer 100, that is, filled in each of the guides S # Λ Pick Ί Π + electric block 1 The gap between 10 and 10 only exposes the conductive joint surface of the electric bump 110. ^ Please refer to the structure of the film of ΓΓΛ can be produced in a variety of ways, and it is also called / brother diagram, which is a schematic diagram of the manufacturing process of the insulation film. It is used in conjunction with the first film technology to make an insulating film. As shown in Fig. 4, a Byinn ... conductive bump 11 is provided. And, on the wafer and the 100V surface: ‘a plurality of ln, nh, and nh wafers 100 are coated on the surface with a photoresist material as the insulating film 111, and the conductive bumps 11 () are completely and completely covered. The bulge highlights the area of the electrical bonding surface where the conductive bump 11 0 on the surface of the wafer 100 is exposed using the mask 130. Develop the pattern of the photoresist material as shown in Figure 6 to form an insulating film ⑴ on the side of no, and expose the conductive f surface of the conductive bump 11G. ° In addition, the insulating film can also be formed by mechanical polishing after plating, please
第8頁 1222725 五、發明說明(5) 考fI圖5 T圖’其為絕緣膜之製作流程示音圖。 如第7圖所示,提供一曰y 1ηπ 不丁心圖 導電凸塊110,並於晶片$曰^片 在/、表面形成複數個 絕緣膜鑛半導體絕緣材料以作為 凡王復盍導電凸塊110。 如第8圖所示’以研磨輪而 化學機械研磨,直至露出導電凸^0電的凸5=2以 心t第9圖所示’去除導電凸塊110的導電接合口面之丰莫 之::層後’晶片1 00表面即形成覆蓋於面 之系巴緣膜m並露出導電凸塊11〇的導電接合電凸鬼H0側面 配合絕緣膜製程的差里i 緣膜的材質與其塗佈區域可做 κ v電凸塊側面之絕 構裝接合結構及其製造方法可用:揭露的覆晶 上,且特別適合用於液晶顯示哭(^ °蛉-組裴應用 基板或軟質基板的接合。’、/、Dn 之驅動晶片與玻璃 石月參考第10圖,其為本發 篦一奋 圖,首先,提供一日片,/t f弟一 κ細例之製作流程 (步驟310) . 片在其表面形成複數個導電凸塊 I v驟3 1 〇 ),其次,提供一基板,於苴 〒电凸塊 合墊(步驟320 );於晶片表面形成絕緣膜开數個接 膜係包覆導電凸塊側面並且露出導電凸堍二=33〇),絕緣 再將含有導電粒子的異方性導電接 ^ 妾合面; 墊,然後對位壓合晶片與基板並固化塊對準接合 成覆晶構裝接合結構(步驟3 5 0 )。 — f接者劑,以形 述之基板可選擇有機Page 8 1222725 V. Description of the invention (5) Figure fI Figure 5 T figure ′ This is a sound chart of the manufacturing process of the insulating film. As shown in FIG. 7, a y 1ηπ non-grid conductive bump 110 is provided, and a plurality of insulating film ore semiconductor insulating materials are formed on the surface of the wafer as the Wang Fufu conductive bump 110. As shown in FIG. 8 'the mechanical and mechanical grinding is performed with a grinding wheel until the conductive bumps are exposed, and the electrical bumps are 5 = 2. As shown in FIG. 9', the richness of the conductive joint surface of the conductive bump 110 is removed. :: Behind the layer 100, the surface of the wafer 100 is formed to cover the surface of the edge film m and the conductive bumps 10 are exposed. The side of the conductive junction electric convex ghost H0 is matched with the insulating film process and the material of the edge film is coated. The region can be used as a junction mounting structure on the side of a κ v electrical bump and its manufacturing method is available: on the exposed flip-chip, and it is particularly suitable for the bonding of liquid crystal display substrates or flexible substrates. ', /, Dn's driver chip and glass stone moon refer to Figure 10, which is an endeavor for this development. First, provide a one-day film, a detailed process of the / tf brother κ (step 310). A plurality of conductive bumps are formed on the surface (Iv step 3 1 0). Secondly, a substrate is provided and the pads are bonded to the piezoelectric bumps (step 320); an insulating film is formed on the surface of the wafer, and a plurality of film systems are used to cover the conductive layer. The sides of the bumps and the conductive bumps are exposed (33 °), the anisotropy containing conductive particles is then insulated Conductive bonding ^ bonding surface; pad, and then align the wafer and the substrate and align the solidified block to form a flip-chip bonding structure (step 350). — F-connector, the substrate described in the form can choose organic
第9頁 1222725 五、發明說明(6) 基板、陶瓷基板 '玻璃基板、矽基板或砷化鎵基板等等。. 其異方性導電接著劑亦可選擇熱固化之高分子基接著劑、 光固化高分子基接著劑或其他接著材料,並配合材料以加 熱、曝光或微波等方式固化。 由於導電粒子也可能堆積於基板的接合墊之間而導致 短路,基板之接合墊側面亦可形成一絕緣膜,於本發明之 製作流程步驟中更包含於基板形成絕緣膜的步驟,絕緣膜 係包覆接合墊侧面並且露出接合墊的導電接合面。請參考 〒11圖,其,本發明第二實施例之結構示意圖。晶片丄⑽ 2 0 0係以面對面的方式接合使複數個導電凸塊11 〇個 I i壓合於複數個接合墊2 i 〇而形成電性導通。於晶片盥 接點側面,包括導電凸塊11〇和接合墊21〇,皆形成 ^ 11、211來防止因異方性導電接著劑120之導電粒 產生聚集而產生的短路現象。 以卩ρ ΐ然本發明之較佳實施例揭露如上所述,然.其並非用 样、士,本毛明’任何熟習相關技藝者,在不脫離本發明之 ίΐ Γ?5 , 為準呆4乾圍須視本說明書所附之申請專利範圍所界定者Page 9 1222725 V. Description of the invention (6) Substrate, ceramic substrate 'Glass substrate, silicon substrate or gallium arsenide substrate, etc. The anisotropic conductive adhesive can also be selected from heat-curable polymer-based adhesives, light-curable polymer-based adhesives or other adhesive materials, and the materials can be cured by heating, exposure or microwave. Since conductive particles may also be deposited between the bonding pads of the substrate and cause a short circuit, an insulating film may also be formed on the side of the bonding pads of the substrate. In the manufacturing process of the present invention, the step of forming an insulating film on the substrate is further included. Cover the sides of the bonding pad and expose the conductive bonding surface of the bonding pad. Please refer to FIG. 11, which is a schematic structural diagram of a second embodiment of the present invention. The wafer 丄 ⑽ 2 0 is bonded in a face-to-face manner so that a plurality of conductive bumps 110 i I are pressed onto a plurality of bonding pads 2 i 0 to form electrical conduction. On the side of the wafer contact, including the conductive bump 11 and the bonding pad 21, ^ 11 and 211 are formed to prevent the short circuit caused by the aggregation of the conductive particles of the anisotropic conductive adhesive 120.卩 ρ ΐ The preferred embodiment of the present invention is disclosed as described above, however. It is not a sample, a scholar, Ben Maoming 'Any person skilled in the relevant arts will not depart from the Γΐ 5 of the present invention. 4 Qianwei must be defined by the scope of the patent application attached to this specification
第10頁 1222725 圖式簡單說明 第1圖為本發明第一實施例之結構示意圖; 第2圖和第3圖為本發明之絕緣膜分佈示意圖; 第4圖至第6圖為絕緣膜之製作流程示意圖; 第7圖至第9圖為絕緣膜之製作流程示意圖; 第1 0圖為本發明第一實施例之製作流程圖;及 第11圖為本發明第二實施例之結構示意圖。 【圖式符號說明】 100 晶片 110 導電凸塊 111 絕緣膜 . 120 導電性接著劑 130 光罩 140 研磨輪 121 導電粒子 200 基板 210 接合墊 211 絕緣膜 步驟3 10 提供一晶片,在其表面形成複數個導電凸 塊 步驟3 2 0 提供一基板,於其表面形成複數個接合墊 步驟3 3 0 於晶片表面形成絕緣膜 步驟3 4 0 將含有導電粒子的異方性導電接著劑覆蓋 於基板上 步驟3 5 0 對位壓合晶片與基板以並固化異方性導電Page 10 1222725 Brief description of the drawings. Figure 1 is a schematic diagram of the structure of the first embodiment of the present invention; Figures 2 and 3 are schematic diagrams of the distribution of the insulating film of the present invention; Figures 4 to 6 are the production of the insulating film Schematic diagrams; Figures 7 to 9 are schematic diagrams of the manufacturing process of the insulating film; Figure 10 is a manufacturing flowchart of the first embodiment of the present invention; and Figure 11 is a structural schematic diagram of the second embodiment of the present invention. [Illustration of Symbols] 100 wafers 110 conductive bumps 111 insulating film. 120 conductive adhesive 130 photomask 140 grinding wheel 121 conductive particles 200 substrate 210 bonding pad 211 insulating film step 3 10 Provide a wafer to form a plurality on its surface Step 3 2 0 providing a substrate, forming a plurality of bonding pads on the surface thereof step 3 3 0 forming an insulating film on the surface of the wafer step 3 4 0 covering the substrate with an anisotropic conductive adhesive containing conductive particles 3 5 0 Alignment bonding wafer and substrate to cure anisotropic conductivity
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