1221001 玖、發明說明： (一） 發明所屬之技術領域 本發明係關於在矽鍺磊晶片上成長高品質砷化鎵磊晶之 方法，該方法結合各相關技術及觀念之改良，其運用了超 高真空化學氣相磊晶（UHVCVD)以成長鍺磊晶薄膜，然後再 以金屬有機物化學氣相磊晶法（M0CVD)於該鍺薄膜ί:成長一 砷化鎵磊晶層。 本發明亦關於一種能在矽鍺磊晶片上成長高品質砷化鎵 薄膜之方法，其藉由在矽鍺磊晶層將差排侷限化並利用應 β 變界面阻擋該線差排之傳遞，而使該方法具有大幅降低總 磊晶層之厚度、減少缺陷密度，及解決了表面粗糙度問題 等優點。由於這些優點使本發明之技術具有成本低廉、方 法簡單及產能高等特性，故本發明對於製作I V族高速元 件、光學元件以及整合I V族與I I I - I V族積體電路之技術 而言，非常具有競爭力及產業上之利用價値與潛力。 (二） 先前技術 對於較先進之半導體元件之製造而言，於矽晶片上成長 ® 高品質的砷化鎵或其他I I I - V族化合物半導體係爲此一領 域長久期待及努力的目標。此種材料構造上的優點包括， 在應用方面，砷化鎵具有高的電子遷移率及光學特性，而 矽晶片具有較優的機械強度及良好的熱傳導性質；此外對 其他先進之電子元件而言，由於I I I - V族化合物與砂晶片 之結合，其亦提供了整合砷化鎵之可能性。 惟在矽晶片上異質磊晶砷化鎵，該元件構造上的主要限 -6 - 1221001 制爲在兩種材料間，其具有晶格常數（ut tlce constant )4 . 1 %之差距及本質的熱膨脹係數差異，此種在異質界面 上之晶格失配（m i s m a t c h )形成了失配差排網絡和所謂之 反相區域（anti-phase domain)。在典型之磊晶成長條件 下，這些缺陷之存在將嚴重地限制在砍上砷化鎵元件之應 用。 目前用以克服在矽上成長砷化鎵所產生缺陷之方法包括 :改變直接在矽上成長砷化鎵之成長條件、利用應變超晶 格緩衝層以過濾線差排（t h r e a d i n g d i s 1 〇 c a t i ο η )、及利 春 用鍺含量漸變矽鍺緩衝層之技術。類似方法仍分別存在著 線差排密度過高、或磊晶過程之間或之後，在磊晶層內之 龜裂、或磊晶層過厚等問題。 例如，在矽上直接成長砷化鎵層之技術，其爲了降低由 於砷化鎵/矽晶格失配所引起的大量線差排，習知技藝者係 採退火技術或應變界面超晶格緩衝層過濾技術來解決，相 關之揭示包括由美國專利US 5 9 5 9 3 0 8、5 87 9 9 6 2、5 47 3 1 7 4 、5308444、5438951、523886 9、5183776 及 5141893 所揭 Φ 示，及A.C.Gossard等人所發表文獻” Subpicosecond carrier dynamics in low-temperature grown G a A s on Si substrates”（Applied Physics Letters，Vol .75，Νο·17，2 5 Oct_1999)、以及 p.J.Goodhew 等人所發表文獻”Growth of high quality gallium arsenide on HF-etched silicon by chemical beam epitaxy”（Applied Physics Letters， Vol.62,No.l4, 5 April 1993)及 T.F.Carruthers 等人所 -7- 1221001 發表文獻”Integration of low-temperature GaAs on Si substrates "(Applied Physics Letters，Vol.62,No.3，18 Jan. 1 99 3 )。這些習知技術對於克服直接在矽上成長砷化鎵 磊晶層，其所產生之線差排密度之降低幅度其實相當有限 ，一般約在108/cm 2，即令再經高溫退火處理也僅降至1〇7/ cm 2而已；且還由於砷化鎵與矽之間的熱膨脹係數差異較 大，因此熱處理過程所誘發之額外差排亦難以消除，故在 高性能元件之製作方面，上述習知的成長技術難以符合要 求。 鲁 此外，利用緩衝層於矽上成長砷化鎵，亦即構造爲砷化 鎵/緩衝層/矽，其中該緩衝層目前已知包括SeS2、ZnSe或 ST0膜等。例如，M. Umeno等人所發表之文獻”High-quality GaAs on Si substrate by the epitaxial lift-off technique using SeS2 ”（Applied Physics Letters，1221001 (1) Description of the invention: (1) The technical field to which the invention belongs The present invention relates to a method for growing high-quality gallium arsenide epitaxial wafers on silicon germanium epitaxial wafers. This method combines the improvement of various related technologies and concepts. High vacuum chemical vapor phase epitaxy (UHVCVD) is used to grow germanium epitaxial films, and then metal organic chemical vapor phase epitaxy (MOCVD) is used to grow germanium thin films: a gallium arsenide epitaxial layer is grown. The present invention also relates to a method capable of growing a high-quality gallium arsenide film on a silicon germanium epitaxial wafer. By limiting the differential row in the silicon germanium epitaxial layer and blocking the transmission of the differential row by using a beta-change interface, This method has the advantages of greatly reducing the thickness of the total epitaxial layer, reducing the defect density, and solving the problem of surface roughness. Due to these advantages, the technology of the present invention has the characteristics of low cost, simple method, and high productivity. Therefore, the present invention is very useful for the technology of manufacturing Group IV high-speed components, optical components, and integrating Group IV and III-IV integrated circuits Competitiveness and industrial utilization price and potential. (II) Prior Technology For the manufacture of more advanced semiconductor devices, growing on silicon wafers ® high-quality gallium arsenide or other I I I-V compound semiconductors has been a long-awaited and hard-working goal in this field. The structural advantages of this material include, in terms of application, gallium arsenide has high electron mobility and optical characteristics, and silicon wafers have superior mechanical strength and good thermal conductivity; in addition, for other advanced electronic components Due to the combination of III-V compounds and sand wafers, it also provides the possibility of integrating gallium arsenide. However, the main limitation on the structure of the heteroepitaxial gallium arsenide on a silicon wafer is -6-1221001. It is made between two materials, which has a gap of ut tlce constant of 4.1% and an essential Differences in thermal expansion coefficients, such lattice mismatches on heterogeneous interfaces form mismatched misalignment networks and so-called anti-phase domains. Under typical epitaxial growth conditions, the existence of these defects will be severely limited to the application of cutting GaAs components. The current methods to overcome the defects caused by the growth of gallium arsenide on silicon include: changing the growth conditions of growing gallium arsenide directly on silicon, using a strained superlattice buffer layer to filter the line difference (threadingdis 1 〇cati ο η ), And Lichun's technology of using a germanium buffer layer with graded silicon germanium. Similar methods still have problems such as excessively high linear differential row density, or cracks in the epitaxial layer, or too thick an epitaxial layer between or after the epitaxial process. For example, in the technique of directly growing a gallium arsenide layer on silicon, in order to reduce a large number of line differences caused by a gallium arsenide / silicon lattice mismatch, a skilled artist adopts an annealing technique or a strain interface superlattice buffer. Layer filtering technology to solve the problem. Related disclosures include those disclosed in US patents US 5 9 5 9 3 0 8, 5 87 9 9 6 2, 5 47 3 1 7 4, 5308444, 5438951, 5236886 9, 5183776, and 5141893. , And literature published by ACGossard et al. “Subpicosecond carrier dynamics in low-temperature grown G a As s on Si substrates” (Applied Physics Letters, Vol. 75, No. 17, 25 Oct_1999), and pJGoodhew et al. Publications "Growth of high quality gallium arsenide on HF-etched silicon by chemical beam epitaxy" (Applied Physics Letters, Vol. 62, No. 14, 5 April 1993) and TF Carruthers et al. 7- 1221001 Publications "Integration of low-temperature GaAs on Si substrates " (Applied Physics Letters, Vol. 62, No. 3, 18 Jan. 1 99 3). These conventional techniques are useful for overcoming the growth of gallium arsenide epitaxial layers directly on silicon, The reduction of the linear differential row density produced by it is actually quite limited, usually about 108 / cm 2, even if it is subjected to high-temperature annealing treatment, it is only reduced to 107 / cm 2; and because of the gallium arsenide and silicon There is a large difference in thermal expansion coefficients between them, so it is difficult to eliminate the extra differential induced by the heat treatment process. Therefore, in the production of high-performance components, the above-mentioned conventional growth technology is difficult to meet the requirements. In addition, using a buffer layer to grow on silicon Gallium arsenide, that is, structured as gallium arsenide / buffer layer / silicon, where the buffer layer is currently known to include SeS2, ZnSe, or ST0 film, etc. For example, the document "High-quality GaAs on" published by M. Umeno et al. Si substrate by the epitaxial lift-off technique using SeS2 ”(Applied Physics Letters,
Vo 1·75，Νο. 24，13 Dec· 1 9 9 9 )，曾揭示一種接合（bonding) 技術，即利用S e S 2作爲夾層把砷化鎵晶圓接合在矽晶片上 ’再用剝離（Π f t - 〇 f f )技術獲得所需要之砷化鎵層。然而 φ 很明顯地，此項技術成本很高，而且無法獲得大尺寸之矽 晶片上砷化鎵。 而 J .C.Tramontana 等人所發表之文獻” Use of ZnSe as an interlayer for GaAs growth on Si55 (Applied Physics Letters，Vo 1 · 6 1，No . 2，1 3 Ju1y 1 9 9 2 )，則揭示利用 ZnSe 作爲緩衝層於矽晶片上成長砷化鎵，即砷化鎵/ z n s e /矽。 但在矽晶片上成長高品質之ZnSe十分困難，而且ZnSe的 1221001 熱導係數小並不利於元件之製作，故此種技術並不具備實 用性。 再者’ K.Esenbeiser等人所發表之文獻” New research yield epitaxially grown GaAs on Si，，（Solid State Techno 1 ogy，45 , 6 1 2002 )，曾揭示利用STO膜作爲緩衝層 於砂晶片上成長砷化鎵，即砷化鎵/ S T 0 /政。但S T 0膜必須 利用分子束磊晶技術（ΜΒΕ )成長而成長技術困難、成本昂 貴且產量低，另外，STO膜本身的熱導矽數也很小（〇 . 〇 2 6 W / c m K )而不利於元件之散熱，故此種技術之實用性亦不被 · 看好。 至於採取矽鍺含量漸變緩衝層之技術者，例如 A.C.Gossard 等人所發表” Subpicosecond carrier dynamics in low-temperature grown GaAs on Si subs t rat es”該篇文獻中其利用Si 作爲中間之緩衝層 於矽晶片上成長砷化鎵，由於鍺與砷化鎵具有十分接近的 晶格常數和熱膨脹係數，因此這項技術相對地最具有應用 前景，但仍然存在著一些明顯的缺失。其爲獲得低的差排 · 密度之鍺磊晶層，於成長過程中，Si i_xGex中的鍺含量需要 由零漸增至百分之百，如此之鍺含量漸變緩衝層其厚度往 往達到1 0微米以上。過大的厚度將會增加元件製造的困難 度及磊晶製作的成本。另外，此種技術成長的鍺其表面會 出現井狀的圖案，而使得表面粗糙度增加而變差，爲解決 這種問題，彼等採用化學機械硏磨（CMP )技術進行消除，但 其運用同樣帶來技術上的難度及成本上的問題。 -9- 1221001 (三）發明內容 本發明之目的在於解決先前技術中應用緩衝層 上成長砷化鎵之缺失，特別是利用作爲 矽晶片上成長砷化鎵的技術，本發明提供了包括 總磊晶之厚度、解決過大之高鍺含量磊晶層之表 、及降低因爲晶格失配所形成缺陷密度過高等問 技術。 有關利用Si nGe,作爲緩衝層於矽晶片上成長 技術，E.A.Fitzgerald等人曾發表於” Impact buffer thickness on electronic quality of G a on graded Ge/GeSi/Si substrate”（Applied Letters，Vol.76,No.14,3 April 2000) ’ 彼等係] 上成長鍺含量漸變之矽鍺磊晶，再以分子束磊晶S 於該最頂層之鍺薄膜上進行一砷化鎵層磊曰气 E. A.Fi tzge raid等人已於美國專利案US 6 29 1 3 2 1、 中揭露了於矽晶片上成長Si 之技術，而有 進行碑化錄嘉晶’例如採分子束嘉晶法（MBE / Jeng-Ming Kuo等人之美國專利案 US 53 0 8444所 E.A.Fitzgerald 等人在 US 6 29 1 3 2 3 專利中所 導體構造，係爲一鍺含量梯度從零漸變之矽鍺磊 有低差排密度，然而總磊晶層厚度卻達十微米以 示之製造方法爲於矽晶片上，以MBE或超高真空 磊晶成長其含有矽鍺含量漸變之第一層’通常以_ %鍺含量之漸變速率，漸增至5 0%鍺含量後’接著 在矽晶片 緩衝層於 如何降低 面粗糙度 題之解決 砷化鎵的 of G aA s As grown Physic 於砂晶片 ^ ( MBE ) “；其中 6107653 關鍺表面 )則見於 揭示的。 揭示之半 晶層，具 上。其揭 化學氣相 ί微米10 利用C Μ Ρ 1221001 技術平坦化該層表面，此時第一層之厚度約爲5微米 後再成長弟一層’鍺含量由50%增至 75% ，接著再用 技術平坦化該第二層表面，此時第二層之厚度約爲2. 米；第三層後之高鍺含量磊晶層，改變其磊晶條件， g周降成長溫度及成長氣體分壓，此時成長之厚度約爲 微米以上。根據上述方法最佳實施例所製得之樣品爲 面無龜裂、線差排密度約1 〇6 / cm 2、表面粒狀物密度約 cm 2、粗糙度24奈米及總磊晶厚度至少i 〇微米以上之 層。 然後再根據其於”Impact of GaAs buffer thicknes electronic quality of G a A s grown on graded Ge/GeS subs t rate”文獻中所揭，使用分子束磊晶法於該鍺薄 ，再磊晶一層約2 . 5微米之砷化鎵。 然而’本發明方法特點之一爲，首先在砂晶片上成 層高鍺含量之矽鍺磊晶層（如0.5至0.8微米之Si。」 )’利用本層容納大量因晶格失配所產生之線差排於 底部與界面處。接著成長第二或第三層更高鍺含量之 磊晶層（如 0.5 至 0.8 微米之 SiG.osGem、Sio.wGeu 利用各層之間所形成的應變界面，以進一步阻擋在第 未湮滅掉而傳遞上去之線差排，最後成長爲總磊晶厚 數微米之鍺薄膜磊晶層，例如3微米以下。接著再以 有機化學氣相磊晶法，於該鍺薄膜表面磊晶一層特定 之砷化鎵磊晶。該砷化鎵磊晶厚度可視所製作元件之 需求而定，例如1至3微米厚。 ;妖 CMP 5微 包括 2.5 :表 150/ 嘉晶 s on i /Si 膜上 長一 G e 0 9 該層 矽鍺 8 ) ’ 一層 度僅 金屬 厚度 特性 1221001 在上述成長過程中，對每一單層作即時之高溫退火處理 ，即於6 5 0至80(TC下進行1 5至60分鐘，以進一步提高鍺 薄膜及砷化鎵之磊晶品質。 與E . A · F 1 t z g e r a 1 d等人之硏究及專利相較，本發明係採 取高含量鍺，例如Sin GeQ.9爲起始第一層之矽鍺磊晶，然 後以階梯式地提供其更高鍺含量，例如S^.^Ge^.M、或視 需要增加之Sio.^Geo.^^晶成長，其目的係利用成長具有 特定厚度之第一層，使大量因晶格失配產生之線差排發生 在此磊晶層內，然後再成長第二或視需要第三層，利用其鲁 所形成應變界面阻擋第一層線差排之向上傳遞，故本發明 顯然相對於採每微米漸增5 %或1 〇%鍺含量的成長方式係爲 截然不同之技術觀念，若依前者之漸變梯度至I 〇 〇 % ，則其 石夕鍺磊晶層厚度無法降至1 0微米以下，而本發明之總磊晶 層厚度可控制在約3微米以下（如果不計最後成長之砷化 鎵磊晶厚度）。 其次，本發明之另一特點爲，本發明在矽上成長矽鍺磊 晶之方法係採用超高真空化學氣相磊晶技術，在磊晶溫度馨 3 5 0至6 5 0°C範圍，以高純度之SiH4、GeH4爲成長氣體、成 長氣體壓力20至100毫托下，進行矽鍺磊晶之成長，其不 論第一磊晶層、第二層或視需要之第三層之高鍺含量成長 均維持特定之操作條件’僅改變成長氣體中總矽鍺之比例 。然而，習知之鍺含蓮:漸變技術爲達到特定之鍺含量漸變 卻必須小心地控制其鍺含量漸變梯度，例如爲了降低線差 排密度’則選擇較低之鍺含量漸變梯度，但卻造成磊晶層 -12- 1221001 厚度過高，及一旦成長溫度下降後在磊晶層與矽之間的熱 失配所產生之拉伸應變界面；但是如果選擇較高之鍺含量 漸變梯度，例如每微米漸增1 〇%鍺含量以上，則其線差排 密度變大。低鍺含量之漸變梯度磊晶層中上述現象尙不明 顯，但是達到高鍺含量區域，例如Sio.uGem以上時，以 超高真空化學氣相磊晶技術於初期如7 5 0°C下成長，進入高 鍺含量後需降低成長溫度，例如5 50°C，及更低分壓，例如 3毫托來緩和。 然而，本發明所採用之超高真空化學氣相磊晶技術中， 並不需改變其溫度條件及明顯之壓力變化，故可維持高品 質之鍺薄膜表面及利於砷化鎵磊晶之成長。 習知技術中更包括於每一層磊晶層成長階段之平坦化步 驟’例如以化學機械硏磨（CMP)方式消除其表面粗糙度並續 行其後一層之漸變梯度成長；然而本發明可省卻CMP複雜 之工序，特別係從提供具有平整表面之矽晶片，及在每一 磊晶層成長階段間之即時高溫退火著手，以達到同樣甚或 更佳之平坦化效果。本發明中具有平整表面之矽晶片之提 供’係先以標準淸洗步驟潔淨，再於1 0 %氨氟酸溶液中浸 濕，然後去離子水淸洗，最後再於8 0 0 °C下進行去除倶生氧 化層之處理，至於每一嘉晶層成長階段間之即時高溫退火 處理’係在7 5 0 °C下進行〇 . 2 5至1小時，進一步降低差排 密度提高單晶品質。 本發明之再一特點爲，透過本發明之方法可製作I v族 高速元件、光學元件以及整合IV族與III-IV族積體電路 -13- ^1001 t 術。I V族高速元件/光學元件，例如爲鍺金氧半場效電 曰曰曰體（Ge M0SFET)、鍺光感測器（Ge photodetector )之IV 方矢材料*高頻元件/光學元件；I I I - I V族之應用包括，例如利 $ @與砷化鎵晶格匹配，在鍺爲緩衝層下以成長高品質之 石申鎵材料，其可作爲I I I - I V族材料之晶片以及作爲整合 I Π - I V族與I v族之整合晶片。上述之π丨_丨v族材料其應 用包括作爲異質接面雙極電晶體（ΗΒΤ)、金半電晶體（MESFET) 、局電子遷移電晶體（HEMET)、發光二極體（LED)、雷射 (L a s e 1.)等結構之磊晶晶片。 φ (四）實施方式 本發明揭示如下列之實施例，但不受該實施例所侷限。 實施例 首先，利用標準淸洗步驟潔淨矽晶片，該潔淨處理包括 將矽晶片浸置於H202 : H2S04比例爲1 : 4之溶液中約10分 鐘’然後取出以去離子水（D . I . w a t e r )淸洗1 0分鐘後， 再以10% HF溶液浸濕約30秒並隨之以去離子水淸洗之。 隨後馬上送進UHVCVD系中，進行成長以前先於800°C下作鲁 預烘（pre bak mg)約10分鐘以去除表面氧化層，再緩降 溫度至400 °C，待溫度穩定後立即成長磊晶層。該超高真空 化學氣相磊晶系統爲具有加熱裝置之石英爐管，背景真空 可用分子幫浦抽至5x 10·8托（torr )以下。成長使用氣體 爲SiH4、GeH4，由質流控制器（MFC)控制成長流量，其中‘ SiH4 之流量保持固定，每次僅調整GeH4之供應流量，在特定之 操作條件下，包括： - 14- 1221001 (1 )磊晶溫度範圍·· 3 5 0至6 5 0°C，較佳爲400°C ; (2 )成長氣體壓力範圍：20至1〇〇毫托’較佳爲20毫 托； (3 )成長氣體種類：高純度之SiH4、GeH4氣體； 其次，更進一步地成長第二或第三層之更高鍺含量之石夕 鍺磊晶層（每層厚度至少〇 · 1微米以上’較佳爲0 . 5至0 . 8 微米，特佳爲〇·8微米之SiQ.Q5GeG.95、SiG.Q2GeQ.98)以利 用所形成之應變界面更能阻擋在第一層未湮滅掉而傳遞上 去之線差排，接著成長爲一定厚度之鍺薄膜’例如1微米 H 厚。最後再以金屬有機化學氣相磊晶法’於6 5 0 °C下成長厚 度約1至3微米之砷化鎵磊晶層。 上述該成長過程中，每一單層應作即時（i η - s i t u )高溫 退火，即於6 5 0至800°C，較佳爲7 5 0°C下，進行0 . 25至1 小時、退火之氛圍爲氫氣、壓力範圍爲5至20毫托，以進 一步提高鍺薄膜及砷化鎵磊晶之品質。 有關在矽晶片上進行鍺磊晶成長過程中，第一層之鍺含 量至少大於70% ，較佳爲70%至90%之間，特佳爲90% ; · 其次第二層之鍺含量爲80%至98%之間，較佳爲95% ;可 視需要地進行第三層磊晶之成長，選擇之鍺含量介於第二 層與純鍺之間；最後一層之鍺含量爲100% ，又由於鍺與砷 化鎵之晶格常數相同，故再直接於鍺薄膜表面成長砷化鎵 〇 有關本發明最佳之矽鍺磊晶上成長砷化鎵之結果，其中 係以鍺含量爲90%之Si 作爲起始第一層之矽鍺磊晶Vo 1.75, No. 24, 13 Dec. 1 9 9 9), has revealed a bonding technology, that is, using S e S 2 as an interlayer to bond a gallium arsenide wafer to a silicon wafer, and then peel (Π ft-0ff) technology to obtain the required gallium arsenide layer. However, it is clear that this technology is very expensive and it is not possible to obtain large-sized gallium arsenide on silicon wafers. The literature published by J.C.Tramontana et al. "Use of ZnSe as an interlayer for GaAs growth on Si55 (Applied Physics Letters, Vo 1 · 6 1, No. 2, 1 3 Ju1y 1 9 9 2), reveals Using ZnSe as a buffer layer to grow gallium arsenide on silicon wafers, that is, gallium arsenide / znse / silicon. However, it is very difficult to grow high-quality ZnSe on silicon wafers, and the small thermal conductivity of ZnSe 1221001 is not conducive to the production of components. Therefore, this technology is not practical. Furthermore, the document “New research yield epitaxially grown GaAs on Si,” published by K. Esenbeiser et al. (Solid State Techno 1 ogy, 45, 6 1 2002), has revealed the use of The STO film acts as a buffer layer to grow gallium arsenide on the sand wafer, that is, gallium arsenide / ST 0 / political. However, the ST 0 film must be grown using molecular beam epitaxy (MBE) technology, which is difficult, expensive, and low-yield. In addition, the STO film itself has a small thermal conductivity silicon (0.026 W / cmK). It is not conducive to the heat dissipation of the components, so the practicality of this technology is also not optimistic. As for those who adopt silicon-germanium-graded buffer layers, such as “Subpicosecond carrier dynamics in low-temperature grown GaAs on Si subs t rat es” published by ACGossard et al., It uses Si as an intermediate buffer layer on silicon. The growth of gallium arsenide on the wafer, because germanium and gallium arsenide have very close lattice constants and thermal expansion coefficients, so this technology is relatively the most promising, but there are still some obvious shortcomings. In order to obtain a low-emission-density germanium epitaxial layer, during the growth process, the germanium content in Si ixGex needs to be gradually increased from zero to 100%, so the thickness of the germanium-graded buffer layer tends to be more than 10 microns. Excessive thickness will increase the difficulty of component manufacturing and the cost of epitaxial fabrication. In addition, the germanium grown by this technology will have a well-like pattern on the surface, which will increase the surface roughness and worsen. In order to solve this problem, they use chemical mechanical honing (CMP) technology to eliminate, but its application It also brings technical difficulties and cost problems. -9-1221001 (III) Summary of the invention The purpose of the present invention is to solve the lack of growth of gallium arsenide on the buffer layer in the prior art, and in particular to utilize the technology of growing gallium arsenide on silicon wafers, the present invention provides The thickness of the crystal, the solution of excessively high germanium-content epitaxial layers, and reducing the density of defects due to lattice mismatch are too high. Regarding the use of Si nGe as a buffer layer to grow on a silicon wafer, EAFitzgerald et al. Have published "Impact buffer thickness on electronic quality of G on graded Ge / GeSi / Si substrate" (Applied Letters, Vol. 76, No. .14,3 April 2000) 'These systems] On the top of the germanium thin film, a silicon germanium epitaxy with a gradually changing germanium content is grown on the topmost germanium film EAFi tzge Raid et al. have disclosed the technique of growing Si on silicon wafers in the US patent case US 6 29 1 3 2 1. There are inscriptions on Jiajing, such as the molecular beam Jiajing method (MBE / Jeng-Ming Kuo et al. ’S US patent US 53 0 8444 EAFitzgerald et al. ’S US 6 29 1 3 2 3 patented conductor structure is a silicon germanium with a low germanium content gradient from zero to zero gradient density, but The thickness of the total epitaxial layer is ten micrometers. The manufacturing method is shown on a silicon wafer. The first layer containing silicon and germanium content is grown by MBE or ultra-high vacuum epitaxial growth. After gradually increasing to 50% germanium content, it was then buffered on the silicon wafer. The problem of how to reduce the surface roughness is to solve the problem of gallium arsenide of G aAs as grown Physic on sand wafer ^ (MBE) "; of which 6107653 is about the surface of germanium) is found in the revealed. The semi-crystalline layer revealed, with. Its Reveal the chemical vapor phase 10 μm using C MP 1221001 technology to flatten the surface of the layer. At this time, the thickness of the first layer is about 5 μm and then grow. The germanium content is increased from 50% to 75%, and then the technology is used. The surface of the second layer is flattened. At this time, the thickness of the second layer is about 2. m; the epitaxial layer with a high germanium content after the third layer changes its epitaxial conditions, and reduces the growth temperature and partial pressure of the growth gas. At this time, the grown thickness is about micron or more. The sample prepared according to the preferred embodiment of the above method has no cracks on the surface, a linear differential row density of about 1.06 / cm 2, a surface granular density of about cm 2, and a rough surface. Layer with a thickness of 24 nanometers and a total epitaxial thickness of at least 10 micrometers. Then according to its disclosure in the "Impact of GaAs buffer thicknes electronic quality of G a As grown on graded Ge / GeS subs t rate" document, Molecular beam epitaxy is used to thin the germanium and then epitaxial GaAs layer about 2.5 microns. However, one of the features of the method of the present invention is that a silicon germanium epitaxial layer with a high germanium content (such as 0.5 to 0.8 micron Si) is first formed on a sand wafer. This layer is used to contain a large amount of crystals due to lattice mismatch. The line difference is arranged at the bottom and the interface. The second or third epitaxial layer with a higher germanium content (such as SiG.osGem, Sio.wGeu of 0.5 to 0.8 micron) is used to grow the strain interface formed between the layers to further block the transmission before the first annihilation. The upper line difference row finally grows into a germanium thin film epitaxial layer with a total epitaxial thickness of several microns, for example, less than 3 microns. Then, a specific arsenic layer is epitaxially formed on the surface of the germanium thin film by organic chemical vapor phase epitaxy. Gallium epitaxial. The thickness of the gallium arsenide epitaxial can be determined according to the requirements of the device being manufactured, for example, 1 to 3 microns thick .; CMP 5 micro includes 2.5: Table 150 / Jiajing s on i / Si film grows a G e 0 9 This layer of silicon germanium 8) 'One layer only has metal thickness characteristics 1221001 During the above growth process, each single layer is subjected to an immediate high temperature annealing treatment, that is, from 6 5 0 to 80 (TC 1 to 60) In order to further improve the epitaxial quality of germanium film and gallium arsenide. Compared with the research and patents of E. A. F 1 tzgera 1 d and others, the present invention adopts a high content of germanium, for example, Sin GeQ.9 is Start the first layer of silicon germanium epitaxy, and then provide the Germanium content, such as S ^. ^ Ge ^ .M, or Sio. ^ Geo. ^^ crystal growth as needed, the purpose is to grow a first layer with a specific thickness to make a large number of The line difference occurs in this epitaxial layer, and then the second or third layer is grown as needed. The strain interface formed by it is used to block the upward transfer of the line difference in the first layer. Therefore, the present invention is obviously The growth method of gradually increasing the 5% or 10% germanium content is a completely different technical concept. If the former's gradual gradient reaches 100%, the thickness of the germanium epitaxial layer cannot be reduced below 10 microns. The total epitaxial layer thickness of the present invention can be controlled below about 3 micrometers (if the thickness of the gallium arsenide epitaxial layer that grows last is not counted). Secondly, another feature of the present invention is that the present invention grows silicon germanium epitaxial silicon on silicon The method is to adopt ultra-high vacuum chemical vapor phase epitaxy technology, in the epitaxial temperature range of 350 to 650 ° C, with high purity SiH4 and GeH4 as the growth gas, and the pressure of the growth gas is 20 to 100 millitorr. For the growth of silicon germanium epitaxy, regardless of the first epitaxial layer and the second layer As required, the third layer of high germanium content growth maintains specific operating conditions' only changes the proportion of total silicon germanium in the growing gas. However, the conventional germanium-containing lotus: gradient technology must be careful to achieve a specific germanium content gradient Control the gradual gradient of germanium content. For example, in order to reduce the row density, a lower gradual gradient of germanium content is selected, but the epitaxial layer -12-1221001 is too thick, and once the growth temperature decreases, the epitaxial layer and The tensile strain interface caused by thermal mismatch between silicon; however, if a higher gradual gradient of germanium content is selected, for example, increasing the germanium content by more than 10% per micron, the linear difference row density becomes larger. The above phenomenon is not obvious in the graded gradient epitaxial layer with low germanium content, but when it reaches a high germanium content region, for example, above Sio.uGem, it is grown at an initial stage such as 7 50 ° C by ultra-high vacuum chemical vapor phase epitaxy technology. After entering the high germanium content, it is necessary to reduce the growth temperature, such as 5 50 ° C, and lower partial pressure, such as 3 millitorr to ease. However, in the ultra-high vacuum chemical vapor phase epitaxy technology used in the present invention, it is not necessary to change its temperature conditions and obvious pressure changes, so it can maintain a high-quality germanium film surface and facilitate the growth of gallium arsenide epitaxy. The conventional technique further includes a planarization step at the growth stage of each epitaxial layer, such as removing its surface roughness by a chemical mechanical honing (CMP) method and continuing the gradual gradient growth of the subsequent layer; however, the present invention can be omitted. The complicated process of CMP is particularly to provide a silicon wafer with a flat surface and instant high-temperature annealing between the growth stages of each epitaxial layer to achieve the same or even better planarization effect. The provision of the silicon wafer with a flat surface in the present invention is first cleaned by a standard washing step, then soaked in a 10% ammonia solution, then washed with deionized water, and finally at 80 ° C. The process of removing the oxidized oxide layer is performed. As for the instant high-temperature annealing process between the growth stages of each crystallite layer, it is performed at 750 ° C for 0.2 to 1 hour, further reducing the differential density and improving the quality of the single crystal. . Another feature of the present invention is that, through the method of the present invention, a Group I v high-speed element, an optical element, and an integrated Group IV and III-IV integrated circuit can be fabricated. Group IV high-speed components / optical components, such as germanium-gold-oxygen half-field-effect-electric body (Ge M0SFET), germanium photodetector (Ge photodetector) IV Fangya materials * high-frequency components / optical components; III-IV The applications of the family include, for example, matching the lattice with gallium arsenide, and growing high-quality lithium gallium materials under the germanium buffer layer, which can be used as wafers of III-IV materials and as integrated I Π-IV And I v family integrated chip. The applications of the above-mentioned π 丨 _ 丨 v materials include as heterojunction bipolar transistors (ΗΒΤ), gold semi-transistors (MESFETs), local electron transfer transistors (HEMET), light-emitting diodes (LEDs), lightning Epitaxial wafers with structures such as Lase 1. (4) Embodiments The present invention discloses the following examples, but is not limited by the examples. Example First, the silicon wafer is cleaned using a standard decontamination step. The cleaning process includes immersing the silicon wafer in a solution of H202: H2S04 ratio of 1: 4 for about 10 minutes, and then removing it to deionized water (D. I. water ) Rinse for 10 minutes, then soak in 10% HF solution for about 30 seconds and then rinse with deionized water. Immediately afterwards, it was sent to the UHVCVD system. Before the growth, pre bak mg was pre-baked at 800 ° C for about 10 minutes to remove the surface oxide layer, and then the temperature was slowly lowered to 400 ° C. After the temperature stabilized, it was grown immediately. Epitaxial layer. The ultra-high vacuum chemical vapor phase epitaxy system is a quartz furnace tube with a heating device. The background vacuum can be pumped to below 5x 10 · 8 Torr by molecular pumps. The gas used for growth is SiH4, GeH4, and the growth flow is controlled by a mass flow controller (MFC). The flow of SiH4 is kept constant. Only the supply flow of GeH4 is adjusted at each time. Under specific operating conditions, including:-14- 1221001 (1) Epitaxial temperature range: 350 to 650 ° C, preferably 400 ° C; (2) Growth gas pressure range: 20 to 100 mTorr ', preferably 20 mTorr; ( 3) Types of growth gas: high-purity SiH4, GeH4 gas; Secondly, the second or third layer of higher germanium content Shi Xi germanium epitaxial layer (each layer thickness is at least 0.1 micrometer or more) It is preferably 0.5 to 0.8 μm, and particularly preferably 0.8 μm (SiQ.Q5GeG.95, SiG.Q2GeQ.98) to make use of the formed strain interface to better prevent the first layer from passing without being annihilated. The upward linear difference is followed by the germanium film grown to a certain thickness, for example, 1 micron H thick. Finally, a metal organic chemical vapor phase epitaxy method was used to grow a gallium arsenide epitaxial layer with a thickness of about 1 to 3 microns at 650 ° C. During the above growth process, each single layer should be subjected to instant (i η-situ) high temperature annealing, that is, 0.25 to 1 hour at 650 to 800 ° C, preferably 750 ° C. The annealing atmosphere is hydrogen and the pressure is in the range of 5 to 20 mTorr to further improve the quality of the germanium film and gallium arsenide epitaxy. In the process of germanium epitaxial growth on a silicon wafer, the germanium content of the first layer is at least greater than 70%, preferably between 70% and 90%, particularly preferably 90%; · the second layer of germanium content is 80% to 98%, preferably 95%; the third layer of epitaxial growth can be performed as required, and the selected germanium content is between the second layer and pure germanium; the last layer has a germanium content of 100%, Because the lattice constants of germanium and gallium arsenide are the same, gallium arsenide is grown directly on the surface of the germanium film. The result of growing gallium arsenide on the best silicon germanium epitaxy of the present invention is based on a germanium content of 90 % Si as the first layer of SiGe epitaxy