TWI220566B - Flip chip package and method for producing the same - Google Patents

Abstract

A flip chip package includes a substrate, a semiconductor chip with a plurality of bumps formed thereon and electrically and mechanically connected to the substrate, and an underfill. The semiconductor chip has two opposing edges. The present invention is characterized by that the bumps are arranged in a trapezoid pattern. Specifically, the trapezoid pattern has one pair of parallel sides that are substantially parallel to the two opposing edges of the semiconductor chip. The bumps are arranged symmetrically with respect to a line through the middle points of the two opposing edges of the semiconductor chip. The present invention further provides a method for producing the flip chip package.

Description

1220566 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip-chip package structure and a manufacturing method thereof. [Previous technology] With the increasing demand for lighter and more complex electronic devices, the speed and complexity of the chip are relatively higher and higher, so higher packaging efficiency is required ° Miniaturization is the use of advanced The main driving force of packaging technologies (such as chipscae package and flip chip). Compared with the ball grid array package or thin outline package (thinsma 11 〇u 11 ine package, TSOP), the two technologies of "wafer-scale package and flip chip" significantly increase the packaging efficiency, thereby reducing the required substrate space. In general, a wafer-scale package is approximately 20% larger than the wafer itself, but flip chip is described as the ultimate packaging technology because it is approximately as large as the wafer itself. The wafer itself is directly bonded to a substrate using a tin-lead bump fixed on the wafer. Because the difference between the thermal expansion coefficient of the wafer and the substrate is quite large (the coefficient of thermal expansion (CTE) of the semiconductor wafer is about 2-5 ppm tr1, and the coefficient of thermal expansion (CTE) of the substrate is about 18-SOppniC1) 'So the wafer and the substrate Underfill 1 1 is usually used to seal the gap between the tin-lead connection. This glue can reduce the stress caused by the inconsistent thermal expansion coefficient on the tin-lead connection. Figures 1 and 2 illustrate a conventional glue filling step. Generally speaking, an automated dispensing system (a u t〇m a t e d u n d e r f i 1 1 d i s p e n s e s s s t e m) (not shown) places the filler material at 102 points on the crystal.

00707.ptd Page 6 1220566 V. Description of the invention (2) One of the side edges of the piece 1 0 4 1 0 4 a. The glue filling material 102 is then sucked under the wafer 104 through the capillary action to complete the glue filling process. However, in the conventional flip-chip package structure, most of the tin-lead bumps are evenly distributed on the entire lower surface of the semiconductor wafer or around the lower surface of the semiconductor wafer. As shown in FIG. 1, when the filling material 1 2 is filled between the wafer and the substrate via capillary action, the flow ratio of the filling material 1 0 2 near the edge of the wafer 104 is close to the wafer 1 0 4 The central filling material 1 2 flows quickly. Therefore, as shown in Figure 2, when the surrounding filler material 102 reaches the other side edge 1 0 4 b of the wafer, it will start to move to the center, resulting in a "backpacking" phenomenon, forming a void (v 〇 〇 id) 1 0 6. These pores 106 will cause the reliability of the mechanical and electrical connection (ie, the tin-lead connection) between the wafer 104 and the substrate to decrease. SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a flip-chip package structure and a manufacturing method thereof, which can overcome or at least improve the problems of the foregoing prior art. The flip-chip package structure according to the present invention includes a substrate, a semiconductor wafer having a plurality of bumps (bump) electrically and mechanically connected to the substrate and a filler. The semiconductor wafer has two opposite edges (ο ρ ρ s yn g e d g e s). The invention is characterized in that the bumps are arranged in a trapezoidal pattern. In other words, the bumps define a wafer contact area on the semiconductor wafer, and the wafer contact area has a trapezoidal pattern. More specifically, the trapezoidal pattern has a pair of sides that are substantially parallel to and parallel to two opposite edges of the semiconductor wafer. The plurality of bumps are symmetrically arranged with respect to each other based on a line passing through individual midpoints of two opposite edges of the semiconductor wafer. The invention further provides a method for manufacturing the flip-chip package structure. first

00707.ptd Page 7 1220566 V. Description of the Invention (3) First, the aforementioned semiconductor wafer is placed on a substrate. Specifically, the semiconductor wafer has opposite first and second edges and a plurality of bumps arranged in a trapezoidal pattern (that is, the bumps define a trapezoidal wafer contact area on the semiconductor wafer). The trapezoidal pattern The first and second sides are parallel, and the first and second sides are substantially parallel to the first and second edges of the semiconductor wafer. The first edge of the trapezoidal pattern is close to the first edge of the semiconductor wafer but far from the second edge of the semiconductor wafer. The first side of the trapezoidal pattern is longer than the second side, and the plurality of bumps are symmetrically arranged with respect to each other based on a line passing through individual midpoints of the first and second edges of the semiconductor wafer. Preferably, the plurality of bumps have substantially the same pitch 'and the trapezoidal pattern has more bumps on the first side than on the second side. Next, the bumps of the semiconductor wafer are re-soldered to thereby electrically and mechanically connect the semiconductor wafer to the substrate. Dispense a filler material along the first edge of the semiconductor wafer after the re-soldering step so that the filler material is introduced from the first edge of the semiconductor wafer and fills the semiconductor wafer with a capillary phenomenon and the Gap between substrates. The bumps on the semiconductor wafer according to the present invention are arranged in a trapezoidal pattern (that is, the bumps define a trapezoidal wafer contact area on the semiconductor wafer). When the filler is injected, the filler is first spotted. Glue to the larger bottom edge of the trapezoidal pattern (that is, two mutually parallel edges), and then flow to the smaller bottom edge of the other driver via the capillary phenomenon and fill the gap between the substrate and the semiconductor wafer. When the filler material slowly flows to the smaller bottom edge,

00707.ptd Page 8 1220566 V. Description of the Invention (4) The filling material flowing around the wafer and the filling material flowing at the center of the semiconductor wafer flow at approximately the same speed. Therefore, the “backpacking” phenomenon in the aforementioned filling step can be reduced to overcome or at least improve the void problem in the filling step, so as to improve the mechanical and electrical connection between the semiconductor wafer and the substrate (ie, tin-lead connection). Reliability. [Embodiment] FIGS. 3 and 4 show a flip-chip package structure 300 according to an embodiment of the present invention. The flip-chip package structure 3 0 0 mainly includes a substrate 3 2 2, a semiconductor wafer 3 0 6 having a plurality of bumps (such as solder bumps or other metal bumps) 3 0 4 and a filler 3 0 8 . More specifically, the substrate 302 has a plurality of contact pads 3 0 2 a. The bumps 3 0 4 of the semiconductor wafer 3 0 6 are respectively aligned with the contact pads 3 0 2a of the substrate 3 0 2 and Electrically and mechanically connected to the substrate 3 02. Because the difference between the coefficient of thermal expansion of the wafer and the substrate is quite large (the coefficient of thermal expansion (CTE) of the semiconductor wafer is about 2-5ppm XT1, and the coefficient of thermal expansion (CTE) of the substrate is about 1 8-30ppm ° C-i), Therefore, an underfill 1 1 8 is provided between the semiconductor wafer 3 06 and the substrate 3 02 to seal the gap between the semiconductor wafer 3 06 and the substrate 3 2. The filler 3 0 8 can reduce the stress caused by the thermal expansion coefficients of the semiconductor wafer 3 6 and the substrate 3 2 being inconsistent. Referring to FIG. 4, the semiconductor wafer 3 06 has two opposing edges 306a and 306b. The present invention is characterized in that the bumps 3 0 4 are arranged in a trapezoidal pattern 4 0 0. In other words, the bumps 30 4 define a wafer contact region in a trapezoidal pattern on the semiconductor wafer. With

00707.ptd Page 9 1220566 V. Description of the invention (5) In detail, the trapezoidal pattern 4 0 0 has a pair of sides 4 2 2 and 4 0 4, wherein the side 4 2 is roughly the same as the semiconductor wafer 3 0 The edge 3 0 6 a of 6 is parallel, the edge 404 is substantially parallel to the edge 306 b of the semiconductor wafer 306, and the edges 402 and 4 0 4 are parallel to each other. The plurality of bumps 3 0 4 is a line 40 6 passing through the midpoint of the edges 4 2 and 4 0 4 (in this embodiment, the line 4 6 also passes through two opposite sides of the semiconductor wafer). The edges 3 0 6 a and 3 6 b are individually centered) as a reference and are arranged symmetrically to each other. Preferably, the plurality of bumps 3 0 4 have substantially the same pitch (pi t c h), and the trapezoidal pattern 4 0 0 has more bumps 304 on the side 402 than the side 404. The invention further provides a method for manufacturing the flip-chip package structure. First, the aforementioned bump 304 semiconductor wafer 306 having a trapezoidal distribution is placed on a substrate 300. Next, the bump 3 0 4 of the semiconductor wafer 3 0 6 is re-soldered, whereby the semiconductor wafer 3 6 is electrically and mechanically connected to the substrate 3 2. After the reflow step, an automated dispensing system is used to dispense a filler material along the edge 3 0 6 a of the semiconductor wafer 3 0 6 a so that the filler material 3 0 9 is removed from the semiconductor wafer 3 0 6 The edge 3 0 6 a is introduced and fills the gap between the semiconductor wafer 3 6 and the substrate 3 2 by a capillary phenomenon. According to the present invention, the bumps 3 0 4 on the semiconductor wafer 3 6 are arranged in a trapezoidal pattern 4 0 4. When a filler material is injected, the filler material is first dispensed onto the larger one of the trapezoidal pattern 404. The bottom edge 402 (that is, two mutually parallel edges) flows through the capillary phenomenon to another smaller bottom edge 4 0 4 and fills the gap between the substrate 3 02 and the semiconductor wafer 3 06. When the filling material slowly flows to the smaller bottom edge 4 0 4, the bumps 3 0 4 with a trapezoidal distribution can slow down.

00707.ptd Page 10 1220566 V. Description of the invention (6) The flow velocity of the filler material distributed around the semiconductor wafer 3 0 6 is equivalent to the flow velocity of the filler material distributed in the middle of the semiconductor wafer 3 0 6 , So that the wave front (fr ο ntf 1 0w) of the filling material is more consistent. This can reduce the "backpacking" phenomenon in the prior art filling step (as shown in Figure 5), in order to overcome or at least improve the void problem in the filling, so as to improve the semiconductor wafer 3 06 and the substrate 3 2 Reliability between mechanical and electrical connections. The present invention provides a semiconductor wafer having a plurality of semiconductor wafers arranged in an array. The semiconductor wafer has an active surface provided with a plurality of wafer pads. The wafer pads of the semiconductor wafer can be arranged in the trapezoidal pattern 400. However, when the wafer pads of the semiconductor wafer are not arranged in a trapezoidal pattern, the active surface of the semiconductor wafer may be provided with a redistribution layer, and the redistribution layer is provided with a plurality of bumps arranged in the trapezoidal pattern 400 3 0 4, the bumps 3 0 4 are electrically connected to the wafer pad through the redistribution layer. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

00707.ptd Page 11 1220566 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiments of the present invention with the accompanying The figure is described in detail below. Fig. 2 is a perspective view of a packaged image in the glue-filling step of a conventional technique; Fig. 3 is a cross-sectional view of a flip-chip package structure according to an embodiment of the present invention; And FIG. 5 is a diagram for explaining the step of filling glue according to an embodiment of the present invention: 102 filling material 1 04 wafer 104a edge 104b edge 106 aperture 300 flip chip packaging structure 302 substrate 3 0 2a pad 305 Bump 306 semiconductor wafer 3 0 6 a edge 3 0 6b edge 308 filling 309 filling material 400 trapezoidal pattern 402 edge 404 edge 406 line

00707.ptd Page 12

Claims (1)

1220566 VI. Application for Patent Scope 1. A flip-chip package structure comprising: a substrate having a plurality of contact pads provided on the substrate; a semiconductor wafer having a plurality of bumps; And pads connected to the substrate and a wafer contact area defined by the bumps, wherein the wafer contact area is a trapezoid pattern (trapezoid pa 11 er η), the trapezoid pattern Having a pair of sides parallel to each other, and the bumps are symmetrically arranged with each other based on a line passing through a midpoint of the pair of sides parallel to each other; and an adhesive is provided between the substrate and the semiconductor wafer . 2. The flip-chip package structure according to item 1 of the scope of the patent application, wherein the semiconductor wafer has two opposite edges, the pair of parallel sides of the trapezoidal pattern are substantially parallel to the two opposite edges of the semiconductor wafer, and the The plurality of bumps are symmetrically arranged with respect to each other based on a line passing through individual midpoints of two opposite edges of the semiconductor wafer. 3. The flip-chip package structure described in item 1 of the scope of patent application, wherein the plurality of bumps have substantially the same pitch (p i t c h). 4. The flip-chip package structure described in item 1 of the scope of the patent application, wherein the semiconductor wafer has an active surface provided with a plurality of wafer bonding pads, and a redistribution layer is provided on the active surface of the semiconductor wafer. The bumps are provided on the layer, and the bumps are electrically connected to the wafer pads through the redistribution layer. 00707.ptd Page 13 1220566 6. Scope of patent application 5. A method for manufacturing a flip-chip package structure, including the following steps: providing a semiconductor wafer having opposite first and second edges, a plurality of bumps, and a The wafer contact area defined by the bumps, wherein the wafer contact area is a trapezoidal pattern. The trapezoidal pattern has parallel first and second sides, and the first and second sides are roughly Parallel to the edges of the first and second edges of the semiconductor wafer, wherein the first edge of the trapezoidal pattern is closer to the first edge of the semiconductor wafer but farther from the second edge of the semiconductor wafer, the first edge of the trapezoidal pattern is greater than the The second side is long, and the plurality of bumps are symmetrically arranged with respect to each other based on a line passing through individual midpoints of the first and second edges of the semiconductor wafer; placing the semiconductor wafer on a substrate; The bumps of the semiconductor wafer are re-soldered to thereby electrically and mechanically connect the semiconductor wafer to the substrate; after the re-soldering step, a filler material is passed along the semiconductor A first dispensing edge of the sheet (d i s p e n s e), such that the filler material is introduced into and fills a gap between the semiconductor wafer and the substrate by capillary action from the first edge of the semiconductor wafer. 6. The method for manufacturing a flip-chip package structure as described in item 5 of the scope of patent application, wherein the plurality of bumps have approximately the same pitch (pitch) 〇 7. Manufacturing as described in item 5 of the scope of patent application Flip-chip packaging structure 00707.ptd Page 14 1220566 6. The patent application method, wherein the semiconductor wafer has an active surface with a plurality of wafer pads, and the method further includes a step of forming a redistribution layer on the active surface of the semiconductor wafer. The bumps are disposed on the redistribution layer, so that the bumps are electrically connected to the wafer pads through the redistribution layer. 8. A wafer comprising: a plurality of semiconductor wafers, each semiconductor wafer having a plurality of pairs of external contacts and a wafer contact area defined by the pairs of external contacts, wherein the wafer contact area is a trapezoid Pattern (trape ζ 〇idpa 11 er η), the trapezoidal pattern has a pair of sides parallel to each other, and the pair of circumscribed points are symmetrical with each other based on a line passing through the midpoint of the pair of parallel sides arrangement. 9. The wafer according to item 8 of the scope of patent application, wherein the semiconductor wafer has two opposite edges, the pair of parallel sides of the trapezoidal pattern are substantially parallel to the two opposite edges of the semiconductor wafer, and the plurality of The circumscribed points are symmetrically arranged with respect to each other based on a line passing through individual midpoints of two opposite edges of the semiconductor wafer. 10. The wafer according to item 8 of the scope of patent application, wherein the plurality of pairs of circumscribed points have substantially the same pitch (p i t c h). 1 1. The wafer according to item 8 of the scope of patent application, wherein the pair of circumscribed points are bumps. 00707.ptd Page 15 1220566 VI. Patent application scope 1 2. The wafer as described in item 8 of the patent application scope, wherein the semiconductor wafer has an active surface with a plurality of wafer pads, and the semiconductor wafer has the active A redistribution layer is provided on the surface. The redistribution layer is provided with the pair of external points, and the pair of external points are electrically connected to the wafer pad through the redistribution layer. 1 3. A semiconductor wafer comprising: a plurality of pairs of external contacts and a wafer contact area defined by the pairs of external contacts, wherein the wafer contact areas are in a trapezoidal pattern (trape ζ 〇idpa 11 e rn ), The trapezoidal pattern has a pair of sides parallel to each other, and the plurality of pairs of circumscribed points are symmetrically arranged with each other based on a line passing through a midpoint of the pair of sides parallel to each other. 14. The semiconductor wafer according to item 13 of the scope of patent application, wherein the semiconductor wafer has two opposite edges, the pair of parallel sides of the trapezoidal pattern are substantially parallel to the two opposite edges of the semiconductor wafer, and the The plurality of circumscribed points are symmetrically arranged with respect to each other based on a line passing through individual midpoints of two opposite edges of the semiconductor wafer. 15. The semiconductor wafer according to item 13 of the scope of patent application, wherein the plurality of pairs of external points have substantially the same pitch (p i 1: c h). 16. The semiconductor wafer according to item 13 of the scope of patent application, wherein the pair 00707.ptd Page 16 1220566 6. Scope of patent application The circumscribed point is a bump. 17. The semiconductor wafer according to item 13 of the scope of patent application, wherein the semiconductor wafer has an active surface provided with a plurality of wafer bonding pads, and a redistribution layer is provided on the active surface of the semiconductor wafer. The pair of externally connected points are provided on the layer, and the pair of externally connected points are electrically connected to the chip solder pad through the redistribution layer. 00707.ptd Page 17