1220562 五、發明說明（1) 1. 發明所屬之技術領域 本技藝適用於積體電路晶片之封裝。 2. 先前技術 在封裝技藝中，由於晶片以及金屬基材的體積都越來越 小，而且為了獲得輕薄短小之封裝，所以不適合利用切 割刀之機械切割方式，製作溝槽。這種微凹溝的製作， 通常必須使用化學蝕刻的方式蝕刻出溝槽，作為正負極 金屬基材之電性絕緣用。 然而在以同一種蝕刻技藝時，若是使用的基材的厚度較 薄時，蝕刻所獲得的溝槽寬度相對就較窄，有利於產品 之體積縮小的期望。但是，缺點是：基材太薄，堅硬度 不夠，不利於後續之作業，散熱特性上也會比較差。在 某些應用時，希望獲得較堅硬的基材，然而，若是使用 的基材的厚度愈厚，則蝕刻所獲得的溝槽寬度將會變 寬，這樣雖然可以使用，但是不利於產品之體積縮小的 期望。 本技藝便是製作出具有較厚的基材，同時又具有狹窄的 蝕刻寬度之技藝，可以克服習知技藝的缺點。1220562 V. Description of the invention (1) 1. Technical field to which the invention belongs This technology is applicable to the packaging of integrated circuit chips. 2. Prior technology In the packaging technology, since the volume of the wafer and the metal substrate are getting smaller and smaller, and in order to obtain a thin, thin and short package, it is not suitable to use a cutter to mechanically cut the groove. For the production of such micro-grooves, the grooves must usually be etched by chemical etching for electrical insulation of positive and negative metal substrates. However, when the same etching technique is used, if the thickness of the substrate used is thin, the trench width obtained by etching is relatively narrow, which is conducive to the expectation that the volume of the product is reduced. However, the disadvantages are: the substrate is too thin and the hardness is not enough, which is not conducive to subsequent operations, and the heat dissipation characteristics are also poor. In some applications, it is desirable to obtain a harder substrate. However, if the thickness of the substrate used is thicker, the trench width obtained by etching will be wider. Although it can be used, it is not conducive to the volume of the product. Shrinking expectations. This technique is to produce a technique with a thick substrate and a narrow etching width, which can overcome the shortcomings of the conventional technique.
1220562 五、發明說明（2) 圖1 .先前技藝 顯示習知技藝中，以金屬材料丨〇蝕刻出寬度為w的溝槽 14，虛線所包含的第一金屬11以及第二金屬12構成一9個 封裝單元。 晶片1 5安置於第一金屬11上，以打線將表面電極電性搞 合至第二金屬基材1 2。最後，加上封裝膠體（圖i中未表 示）便完成晶片之封裝。金屬材料1 〇具有暫時連接區1 3三 處，暫時連接區1 3在封裝完成以後，便被切割，以便獲 得多顆個別的封裝單元如圖1之虛線方塊所示。 圖2_先前技藝圖1之截面圖 圖2_顯示習知技藝中，在相同的蝕刻製程中，較厚的基 材蝕刻出來的溝槽寬度較寬。圖2_ (A)顯示較薄的金屬 基材T1，蝕刻獲得較窄的的溝槽⑽丨；圖2· (B)顯示較厚 的金屬基材T2，蝕刻獲得較寬的溝槽w2。 3.發明内容 本技藝使用蝕刻完成具有一定寬度之溝槽金屬基材多 片’堆疊成為較厚之金屬基材，致使基材厚度加厚，提 高產品基材的堅硬度，卻仍然維持溝槽之寬度不變。然 後在安置晶片、打線、膠體封裝、以及切割完成具有金 屬片堆疊基材之封裝。1220562 V. Description of the invention (2) Figure 1. In the prior art, the conventional technique shows that a trench 14 having a width of w is etched from a metal material. The first metal 11 and the second metal 12 included in the dotted line constitute a 9 Packaging units. The wafer 15 is placed on the first metal 11, and the surface electrodes are electrically bonded to the second metal substrate 12 by wire bonding. Finally, the encapsulation gel (not shown in Figure i) is added to complete the packaging of the chip. The metallic material 10 has three temporary connection regions 13 and 13 after the packaging is completed, the temporary connection regions 13 are cut to obtain a plurality of individual packaging units as shown by the dashed squares in FIG. 1. Fig. 2_ Sectional view of the prior art Fig. 1 Fig. 2_ Shows that in the conventional art, in the same etching process, a thicker substrate etched a wider trench. Figure 2_ (A) shows a thinner metal substrate T1, and a narrower trench is obtained by etching; Figure 2 (B) shows a thicker metal substrate T2, and a wider trench w2 is obtained by etching. 3. Summary of the Invention This technique uses etching to complete the formation of multiple pieces of grooved metal substrates with a certain width into a thicker metal substrate, which makes the substrate thicker and increases the hardness of the product substrate, but still maintains the grooves. Its width does not change. The package with the metal chip stacking substrate is then placed in the wafer, wiring, colloidal packaging, and dicing.
第5頁 1220562 五、發明說明（3) 實施方式 圖3 A. 本技藝實施例一之截面圖 顯示以金屬片堆疊式基材之封裝，包含： (1) 晶片15 ，具有第一電極以及第二電極；圖示中第一電 極為底面電極，第二電極為表面電極。其他型態的電 極，如多表面電極時，可以採用打線方式1 6，分別耦合 其電性至各別的金屬基材。多底面電極時，可以採用 「覆晶技藝」（flip chip technology)，將多個電極分 別直接接觸耦合於對應之兩片金屬基材。 (2) 堆疊式第一金屬基材21，由至少兩片金屬基材11堆疊 構成，電性搞合於前述之第一電極；以及 (3) 堆疊式第二金屬基材22，由至少兩片金屬基材12堆疊 構成，電性耦合於前述之第二電極。 (4 )封膠2 8，封裝保護前述之晶片以及整合固著前述之第 一金屬基材以及第二金屬基材。 封裝膠體28可以包裹金屬基材21. 22.側邊至少一邊 便固著堆疊之金屬片1 1 . 2 1 .使不分散。 以 圖3 B.本技藝實施例二之戴面圖Page 5 1220562 V. Description of the Invention (3) Implementation Figure 3 A. The cross-sectional view of Example 1 of this technology shows a package with a metal sheet stacked substrate, including: (1) a chip 15 having a first electrode and a first Two electrodes; the first electrode in the figure is the bottom electrode, and the second electrode is the surface electrode. For other types of electrodes, such as multi-surface electrodes, wire bonding methods 16 can be used to couple their electrical properties to their respective metal substrates. When multiple bottom electrodes are used, “flip chip technology” can be used to directly couple multiple electrodes to two corresponding metal substrates. (2) The stacked first metal substrate 21 is formed by stacking at least two metal substrates 11 electrically connected to the aforementioned first electrode; and (3) the stacked second metal substrate 22 is formed by at least two The sheet metal substrates 12 are stacked and electrically coupled to the aforementioned second electrode. (4) Sealant 28, which protects the aforementioned wafer and integrates and fixes the aforementioned first metal substrate and second metal substrate. The encapsulating gel 28 can be wrapped around the metal substrate 21. 22. At least one side can be fixed to the stacked metal sheets 1 1. 2 1. Take Figure 3 B. Wearing view of the second embodiment of this technique
1220562 五、發明說明（4) 與圖3 A不同點為本設計在金屬基材11雙面皆安置有晶片 1 5，以膠體2 8封裝雙面的晶片1 5以及打線1 6。 圖3 C. 本技藝實施例三之截面圖 與圖3B不同點為本設計在金屬基材11. 12.雙面的膠體28 為不對稱封膠，圖3 C虛線顯示上方膠體全覆蓋或是接近 全覆蓋，下方膠體為局部覆蓋。圖3B為矩形封膠28，金 屬基材1 1. 1 2.的雙面為對稱封膠。 圖4 . 本技藝實施例四之頂面圖 圖4顯示製作至少一個通孔27於金屬基材21.22.，讓膠體 28佔據通孔27，以便固著堆疊之金屬片11. 21·。膠體28 也包裹金屬基材2 1. 2 2 .側邊至少一邊，加強固著效果。 圖5 . 本技藝實施例五之頂面圖 顯示膠體282只是局部包裹基材21.22.，藉著通孔中的膠 體以及兩片金屬基材2 1 . 2 2 .之間的膠體填充，固著整個 產品。 圖6 . 本技藝實施例六之頂面圖 圖6顯示將金屬基材2 1 1 . 2 1 2.週邊局部内縮，讓膠體2 8佔 據，以便由金屬基材2 Π. 221.之邊壁固著堆疊之多片金1220562 V. Description of the invention (4) Different from Fig. 3A, the design is based on the placement of wafers 15 on both sides of the metal substrate 11 and the use of gel 2 8 to encapsulate the double-sided wafers 15 and wire 16. Figure 3 C. The third embodiment of the technique is different from Figure 3B in the design of the metal substrate 11. 12. The double-sided gel 28 is an asymmetric sealant, and the dotted line in Figure 3 C shows whether the upper gel is fully covered or not. Near full coverage, the lower colloid is partially covered. Figure 3B is a rectangular sealant 28, and the metal substrate 1 1. 12 is double-sided with a symmetrical sealant. Fig. 4. Top view of the fourth embodiment of the present technology. Fig. 4 shows making at least one through hole 27 in the metal substrate 21.22. The colloid 28 occupies the through hole 27 so as to fix the stacked metal sheets 11. 21 ·. The colloid 28 also wraps the metal substrate 2 1. 2 2. At least one side of the side enhances the fixing effect. Figure 5. The top view of the fifth embodiment of the technique shows that the colloid 282 only partially covers the substrate 21.22. The colloid is filled and fixed by the colloid in the through hole and the two metal substrates 2 1. 2 2. The entire product. Figure 6. Top view of the sixth embodiment of the present technology Figure 6 shows the metal substrate 2 1 1. 2 1 2. The periphery is partially retracted so that the colloid 2 8 is occupied so as to be occupied by the metal substrate 2 Π. 221. 的 边Wall fixed stack of multiple pieces of gold
1220562 五、發明說明（5) 屬片 11. 21.。 圖7. 本技藝實施例七之頂面圖 圖中顯示金屬基材2 12. 222.，相鄰邊為彎折型，提供前 述之膠體2 8具有較長之抓膠區，提高產品之固著效果。 前述描述揭示了本技藝之較佳實施例以及設計圖式， 惟，較佳實施例以及設計圖式僅是舉例說明，並非用於 限制本技藝之權利範圍於此，凡是以均等之技藝手段實 施本技藝者、或是以下述之「申請專利範圍」所涵蓋之 權利範圍而實施者，均不脫離本技藝之精神而為申請人 之權利範圍。1220562 V. Description of the invention (5) Film 11.21. Figure 7. The top view of the seventh embodiment of the present technology shows the metal substrate 2 12. 222. The adjacent sides are bent, providing the aforementioned colloid 2 8 has a longer grip area to improve the solidity of the product.着 效应。 Effect. The foregoing description discloses the preferred embodiments and design drawings of the technique. However, the preferred embodiments and design drawings are merely examples, and are not intended to limit the scope of rights of the technique. Those skilled in the art, or those implemented within the scope of the rights covered by the "Scope of Patent Application" described below, shall not deviate from the spirit of the technology but be the scope of the applicant's rights.
1220562 圖式簡單說明 5. 圖示的簡單說明 圖1.先前技藝 圖2.先前技藝圖1之截面圖 圖3 A.本技藝實施例一之截面圖 圖3 B. 本技藝實施例二之截面圖 圖3C.本技藝實施例三之截面圖 圖4. 本技藝實施例四之頂面圖 圖5 . 本技藝實施例五之頂面圖 圖6 . 本技藝實施例六之頂面圖 圖7. 本技藝實施例七之頂面圖 6. 元件編號表 1 0 . 1 1. 1 2 . 金屬基材 13. 暫時連接區 14. 蝕刻溝槽 15. 晶片 16. 打線 w. w 1. w2 .寬度 ΤΙ . T2.厚度 2 1. 22. 2 1 1. 22 1. 2 1 2. 22 2.堆疊式金屬基材 27. 通孔 2 8.2 82. 膠體 29. Z型相鄰邊1220562 Schematic illustration 5. Simple illustration of the diagram Figure 1. Prior art figure 2. Sectional view of prior art figure 1 Figure 3 A. Sectional view of the first embodiment of the technique Figure 3 B. Section of the second embodiment of the technique Figure 3C. Sectional view of the third embodiment of the technology Figure 4. Top view of the fourth embodiment of the technology Figure 5. Top view of the fifth embodiment of the technology Figure 6 Top view of the sixth embodiment of the technology Figure 7 Top view of the seventh embodiment of this technology 6. Element number table 1 0. 1 1. 1 2. Metal substrate 13. Temporary connection area 14. Etched trench 15. Wafer 16. Wiring w. W 1. w2. Width Ti. T2. Thickness 2 1. 22. 2 1 1. 22 1. 2 1 2. 22 2. Stacked metal substrate 27. Through hole 2 8.2 82. Colloid 29. Z-shaped adjacent sides