TWI220068B - A structure of chip package with copper bumps and manufacture thereof - Google Patents

Abstract

A structure of chip package with copper bumps and manufacture thereof is provided. The copper bumps fabricating on first contacts of a carrier for connection with flip-chip package, is formed by means of electroplating. The length of copper bumps is satisfied with a stand between the chip and the carrier. The pitch between neighboring copper bumps is reduced because the diameter of the copper bumps is more less than the diameter of the tradition ball bumps so that the number of the first contacts and bonding pads is added.

Description

1220068 Amendment No. 92114521 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a flip-chip package structure and process, and in particular to a copper bump (c ο pperb um p) Structure and process of flip-chip package. [Previous technology] In recent years, with the rapid development of electronic technology, the high-tech electronics industry has been introduced in succession, which has led to more innovative and more functional electronic products, and has been designed to be light, thin, short, and small. At present, the 'substrate type carrier' is a commonly used structural component in the semiconductor manufacturing process, and it is mainly divided into two types of substrates: laminated and built-up. Among them, the substrate is mainly composed of a plurality of patterned circuit layers and a plurality of 'insulation layers' alternately stacked, and the surface of the substrate has a plurality of contacts, which are used as an input / output medium for connecting a chip or an external circuit. Because the substrate has the advantages of compactness, compact assembly, and good performance, it has become an indispensable component in flip chip package structures. In addition, each wafer is cut by a wafer The formation of the naked said. (die), through the step of die bonding, the bare wafer is surveyed on the substrate described above, and then the bonding pads (bondin are on the pad) formed on the bare wafer, by wires or bumps (Bump) bonding, to electrically connect the § bare pads to the contacts of the substrate, and then cover it with a chip of the packaging material to prevent the bare chip from being affected by moisture and noise. 4. Bare the wafer, thus completing the wafer packaging process. y 9 ′ and protection intention Figures 1A ~ 1F show the process flow of the conventional flip chip packaging process

1220068 _ Case No. 92114521 _ ^ _ Month ___ Repair 丨 Next ___ 5. Description of the invention (2) Please refer to Figure 1A first, first provide a carrier 100, the carrier 100 is a stacked laminated substrate, for example Its material is, for example, a substrate such as epoxy resin. The surface of the holder 100 has a plurality of first contacts 1 1 0 and a plurality of second contacts 1 1 2. The first contact 1 1 0 is located on the surface of the holder 1 0 0 2, The second contact 1 12 is located on the lower surface 100 of the carrier 100, and the first contact 丨 丨 〇 is formed by a patterned circuit layer (not shown) inside the carrier 100. The "electrical connection" is at the second contact 1 1 2. Among them, the patterned circuit layer can be electrically connected to each other through a through-hole (PTH) or a conductive hole (via) penetrating through the insulating layer. In addition, a solder mask layer 20 is formed on the upper and lower surfaces 102 and 104 of the carrier 100, for example, by lamination or coating, and the first contacts 11 and 10 are formed. The two contacts 丨 12 can be exposed between the solder layers 1 2 0. Next, please refer to FIG. 1B and fill in a solder such as tin boat (Sn / Pb) alloy in the opening 132 of the template 130 by screen printing. The tin-to-error ratio is 63:37 to form a tin-lead bump. 4o on these first contacts 11o. Then, refer to Figures 1C to 1D, remove the template 130 and resolder (refi. w) Tin Convex 1 40 to melt the tin-lead bump 1 40 into a spherical body, and then refer to Figures 1E to IF. Before placing a wafer 150 on the carrier 100, a spherical tin boat bump may be used first. 140 die-casting (coining) is a flat piece, and then Japanese-Japanese film 150 is electrically connected to the first contact 1 10 of Chengyi 100 by flip chip bonding, of which the chip 15 The bonding surface has a plurality of bonding pads 152, and each bonding pad 152 has / has a bump 15 4〃, and the material of the bump 154 can be a soldering material / material such as tin-lead alloy. The tin The lead ratio is 9 5: 5 and is used to electrically connect the eighth contact of the carrier 丨 〇〇

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The U L 1 ^ tin fault bump 1 4 0 is coated on the surface of the bump 1 5 4 due to its low melting point when it returns. # 私 $ 知 In the flip chip bonding technology, 'Since the main component of the chip 150 is Shi Xi ^' and the material of the carrier 100 is a high molecular polymer, the thermal expansion of the two (Coefficient 〇f Thermal Expansion, CTE) is not so different. Therefore, due to the thermal strain mismatch between the two, the height between the two must be able to overcome the bumps 154 connected to the wafer 150 and the carrier 100. Damage caused by excessive stress, or fatigue damage caused by repeated stress. However, in the conventional flip-chip bonding technology, in order to meet a sufficient reliable height d, the outer diameter of the spherical bumps 154 is increased so that the distance between the wafer 丨 5 and the carrier 丨 〇f can be greater than Is equal to the reliable height d. However, it is worth noting that if the outer diameter of the spherical bump 1 54 is increased, the distance p between the bump 54 and the bump 154 is also increased. Therefore, under the condition that the bump pitch cannot be further reduced, the number of contacts of the carrier 丨 〇 〇 and the number of pads 152 per unit area of the wafer 150 cannot be increased. [Summary of the Invention] Therefore, 'the purpose of the present invention is to provide a copper bump chip-on-chip package' to reduce the distance between bumps, thereby increasing the number of contacts of the carrier and the number of poles in the early area of the daily film. Another object of the present invention is to provide a flip-chip package substrate, wherein the contacts of the carrier have a plurality of copper bumps, which are used as bumps for connecting the flip-chip package. Another object of the present invention is to provide a flip-chip packaging process in which copper

10366twfl.ptc Page 8 1220068 _Case No. 92114521_ Year Month Revision_ V. Description of the invention (4) The bumps are formed on the contacts of the carrier, and the height of the copper bumps can meet the requirements of a reliable height. To achieve the above object, the present invention provides a copper bump flip-chip package, which mainly includes a carrier, a plurality of copper bumps, a solder mask layer, and a wafer. The carrier has a first surface and a corresponding second surface, wherein the first surface has a plurality of first contacts, and the second surface has a plurality of second contacts. The first contacts are electrically connected to the second contacts. Sexual connection. Each copper bump is respectively disposed on one of these first contacts and connected to it, and the solder mask layer is disposed on the first surface between the copper bumps, exposing the copper bumps. In addition, the wafer has a plurality of solder pads, each of which is provided with a solder material, and each solder material is connected to one of these copper bumps, respectively. In order to achieve the above object, the present invention provides a flip-chip package substrate, which is applied to a flip-chip package of a wafer, wherein the wafer has a plurality of bonding pads. The flip-chip package substrate mainly includes a carrier, a plurality of copper bumps and Solder shield layer. The carrier has a first surface and a corresponding second surface, wherein the first surface has a plurality of first contacts, and the second surface has a plurality of second contacts. The first contacts are electrically connected to the second contacts. Sexual connection. In addition, each copper bump is disposed on one of these first contacts and connected to it, and the copper bump corresponds to one of these pads, respectively, and is suitable for connection with the pad of the wafer. In addition, the solder mask layer is disposed on the first surface between the copper bumps, exposing the copper bumps. '' In order to achieve the above-mentioned object, the present invention provides a flip-chip packaging process. First, a carrier is provided. The carrier has a first surface and a corresponding second surface. The first surface has a plurality of first contacts. Two surfaces have more

10366twf1.ptc Page 9 1220068 Case No. 92114521 Amendment V. Description of the Invention (5) The second contacts are formed to weld these first contacts to the first contact surfaces and expose the first contact surface to some copper; Then bump, perform a crystal-covering step. One of these fresh tadpoles can be without alloy degumming sodium bumps and the crystals are preferably thermally expanded. It is easy to elaborate. The expansion coefficient of the spacer sheet is for the sake of understanding, and the following method is used to explain the point of this cover; the exposed surface of the point is provided and this step, 〇 Invent a gold. The surface butt welding is due to the reduction of the planarity and the different inventions. The special surface and the first surface are shaped by a few crystals. The welding is made of copper, which is an adhesive layer that is more adhesive. Because of the tensile strength of the product, Lift up the contacts and these first surfaces; remove the electroless plating of the first part; and then form a picture of the first contacts into a copper bump. The surface of the wafer pad is divided into a solder material and a solid layer. This resistance to soldering results in a better embodiment, without electricity, and its surface is covered with a number of wafer carriers. Therefore, the two-layer split welding layer is implemented, and the copper is removed from the map; the block is added; there are multiple Welding is configured with a solder connection to each copper dot electrical mask layer, which is formed on the photoresist layer electroplating. Case 4 dipped optical pads are respectively connected to material bumps and connected with solder masks to be soldered to correspond to the resist layer. Each of the exposed layer and the cover layer is implanted in this way. The contacts of the conventional surface packaging of the metal bonding electroplating method can increase the purpose and example of overcoming the strain, and the copper protruding layer described above Before the material sub-layer, such as treatment with permanganic acid. Spacing between structure and system. In addition, the copper wafer was damaged with the carrier. Features', Heyou cooperates with the attached drawing. The surface of the block is nickel-gold and can also be used for bell or nanmeng process, while copper can be shortened, and the points between the bumps can be more explicit. Details

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2A ~ 2 The edge of the figure shows a preferred embodiment of the present invention— "Provided first-the carrier 200, the carrier 200 is, for example, a stack: plate, whose material is, for example, glass epoxy resin (FR _4, FR 疒 w arylene diimide (BT), epoxy resin (with 0} ^ resin) ^ Mei ^ Shun: work, device 2 0 0 Yixin: laminated substrate, the material such as "Asia Poly ammonia (Polyiimde) netting substrate. The surface of the carrier 200 has a plurality of 2j 0 and a plurality of second contacts 2 1 2, wherein the first contact 2 is located at the first of the carrier 2 0 On the surface 200, and the second contact 212 is located on the second surface 204 of the carrier 200, and the first contact 21 is a patterned circuit layer through the interior of the carrier 200 ( (Not shown) and is electrically connected to the second contact 2 丨 2. Then, referring to FIG. 2B, a solder mask layer 220 is formed on the first surface 202, wherein the solder mask layer 2 2 0 is formed on the first surface 202 by, for example, lamination or coating, and a portion of the solder mask layer 220 is removed by laser drilling to expose the first contact point 21. In addition, the solder mask Layer 220 can also be a photosensitive The solder mask layer has a photo-imageable material, and a part of the photo-sensitive material is removed by a photolithography process such as exposure and development to expose the first contact 2 1 0. Please refer to FIG. 2C 'A seed layer 230 is formed on the solder mask layer 220 and the surface of the first contact 210 by electroless plating. The material of the seed layer 230 may be copper, and the bonding between copper and the solder mask layer 220 Therefore, the copper can be completely adhered to the solder mask layer 220 and will not be detached, and the material of the seed layer 230 and the first contact point 21 is copper. Therefore, the distance between the seed layer 230 and the first contact point 2 1 0 Good electrical conductivity. In addition, in electroless plating seeds

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5. Description of the invention (7), before 23 0 ^, the steps of removing gum residue and surface roughening can also be performed.苴 For example, the solvent of the welding mask 2 is washed with a solvent such as potassium manganate or sodium permanganate, etc. The two aspects are used to remove the glue on the surface of the removed mask layer at 22 ° = 21 °. On the other hand, the surface of the solder mask layer 22 can be roughened to facilitate the bonding of the seed layer 230 and the solder mask layer 220. Referring to FIG. 2D, a patterned photoresist layer 24o is formed on the surface of the solder mask layer 22o. For example, a photoresist is applied to the solder mask layer 22o, and a photolithography process such as exposure and development is used to form the photoresist layer. A patterned photoresist is 2 40, and the first contact 21 is exposed. Next, please refer to the diagrams 2E to 2ρ. Said = plating, using the seed layer 2 3 0 as one end of an electrode (not shown) in a plating solution to plate copper (Cu) ions in the plating solution onto the seed layer. On the surface of 23 ′, a copper bump 2 50 is formed on each of the seed layers 2 3 0 exposed to the surface of the first contact 21 of the patterned photoresist layer 24 0, and then a solvent (not green :) The patterned photoresist layer 240 is removed, and the exposed seed layer 230 is removed with an etchant (not shown), so as to obtain the structure shown in FIG. 2F. Please refer to FIG. 2F, wherein copper bumps 2 50 are respectively disposed on the first contacts 210 of the first surface 202 of the carrier 200, and the solder mask layer 220 is wrapped between the copper bumps 2 50 and welded These copper bumps 250 'are exposed on the surface of the cover layer 220 to serve as bumps for connecting the flip-chip package. In addition, the surface of the copper bump 2 50 is also provided with a metal adhesive layer 2 5 2, wherein the metal adhesive layer 2 5 2 is formed on the surface of the copper bump 2 50 by electroless nickel-gold alloy or tin. 'To prevent the surface of the copper bump 250 from generating oxides. In addition, after the copper bump 250 is fabricated, multiple solder balls can be further configured.

10366twf1.ptc Page 12 1220068 __Case No. 92114521_year month chromium ff___ 5. Description of the invention (8) (not shown) on the second contact 2 1 2 of the carrier 2 0 0 to form a ball Grid Array (BGA) package substrate. Of course, the second contact 2 12 of the carrier 2000 may also have multiple pin terminals (not shown on the edge) to form a pin grid array package substrate (Pin Grid Ai ^ / y (PGA), or the plane on which the second contact 212 is located is used as a bonding surface to form a planar contact grid array package substrate (Land Grid Amy, LGA). ′ Please refer to FIG. 2G. After the copper bump 250 of the carrier 200 is completed, a flip-chip package is then mounted on the carrier 200. Among them, a wafer 260 has completed the production of internal integrated circuits, and a plurality of solder pads 262 are arranged on the joint surface of the wafer 260, and a solder material 264 such as a solder paste or a tin-lead bump is disposed on the surface of the solder pad 262, respectively. Soder bumps, etc., so that the solder bumps 262 of the wafer 260 can be connected to the copper bumps 250 by the soldering material 264, and the wafer 2 60 and the carrier 2 0 can be electrically connected to each other to transfer electrons. Signal. It is worth noting that, since the copper bump 250 is formed on the first contact 210 of the carrier 200 by electroplating, the different thermal strain caused by the thermal expansion between the carrier 200 and the wafer 260, The distance between the carrier 200 and the wafer 2 60 can be increased by the bump height d 1 formed by the electric copper smelting, and if the solder material 2 64 is a tin-lead bump, the final height d is copper. The sum of the height dl of the bump and the height d2 of the tin-lead bump (dl + d2). Among them, the higher the height dl of the copper bump 250 is, the smaller the thermal strain caused by the copper bump 250 connected to the carrier 200 and the two ends of the wafer 260 can be reduced. In addition, the materials of the copper bump 250 and the first contact 210 are copper, and copper has good ductility, so

10366twf1.ptc Page 13 1220068 Case No. 921UW1 Description of Invention (September) Month Even if the two ends of the steel bump are subjected to repeated thermal stress, it can still have better fatigue life than the block. Known tin-lead bumps and protrusions outside "ΛRefer to Figure 2H" After the flip-chip packaging is completed, the joint between the copper bump 2 50 and the soldering material 2 6 4 is subjected to better thermal strain failure welding. The material 2 6 4 can be optionally filled with the 'two-bottom filling' material H sheet 2 6 0 and the first surface 2 0 2 of the carrier 2 0 0: the bottom material 2 7 0 such as Epoxy resin (shown as a dashed line) is used to cover the soldering material. Similarly, the copper bump 25o is covered by the solder mask layer 22o, so the damage of thermal strain can be avoided. Of course, except for underfill material 2 7 0 In addition, a packaging material 2 72 can also be used to cover the wafer 2 60, wherein the packaging material '272 ^: resin' is coated on the surface of the wafer 2 60 'but the back of the crystal "6 can be exposed. Since the material of the wafer 2 60 is fragile, the packaging material 272 prevents the surface of the wafer 2 60 from being damaged by external forces. It can be known from the above description that the structure and process of the steel projection disclosed in the present invention is formed on the first contact of the carrier = the mounting method is formed on the first contact, and the height of the projection can conform to the chip washing. g ^ The requirement of reliable height between the devices makes it highly reliable and fatigue life. 'The distance between adjacent two copper bumps can overcome the conventional radial tin-lead bumps are too large' and can no longer be reduced. — The distance between the contacts. Therefore, the use of copper bumps can further reduce the distance between the first contacts (about 165 microns), so the number of first contacts of the carrier can be increased, and the number of pads per unit area of the wafer can be increased. Therefore, it is suitable for flip-chip packaging with high lead count and high density.

10366twfl.ptc Page 14 1220068 _Case No. 92114521_Year Month Day Amend_ V. Description of the invention (10) Structure. In summary, the structure and process of the copper bump flip-chip package of the present invention has the following advantages: 1. For the copper bump flip-chip package of the present invention, the distance between the copper bumps is small, so the carrier can be improved. The number of contacts and the number of fresh rice per unit area of the chip. 2. For the flip-chip package substrate of the present invention, the distance between the first contacts of the carrier can be reduced by using a copper bump as a bump connected to the flip-chip package. 3. For the flip-chip packaging process of the present invention, the copper bumps are formed on the contacts of the carrier by electroplating, and the height of the copper bumps can meet the requirements of a reliable height, making it reliable and fatigue long life. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes and retouch without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

10366twf1.ptc Page 15 1220068 _Case No. 92114521_ Year Month Day Amendment _ Schematic illustrations 1 A ~ 1 F diagrams show the flow chart of the conventional flip chip packaging process; and 2 A ~ 2 diagrams A schematic diagram of the structure and process of a copper bump flip-chip package according to a preferred embodiment of the present invention is shown. [Illustration of drawing marks] 1 00, 200 Carrier 102 202 First surface (upper surface) 104% 204 Second surface (lower surface) 110 210 First contact 112 212 Second contact 120 220 Welding cover layer 130 2 Photoresist 132 • Opening 140: Tin bump 150 λ 260 Wafer 152 262 Pad 154 264 Solder material 230 Seed layer 240 Patterned photoresist layer 250 Copper bump 252 Metal adhesion layer d, dl, d2: Height P: Pitch

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Claims (1)

1220068 _Case No. 92114521_Amended in January / August 6, Application scope 1. A copper bump flip-chip package, comprising: a carrier having a first surface and a corresponding second surface, wherein the first surface There are a plurality of first contacts, and the second surface has a plurality of second contacts, and the first contacts are electrically connected to the second contacts; a plurality of copper bumps, each of the copper bumps The blocks are respectively disposed on one of the first contacts and connected to them; a solder mask layer is disposed on the first surface between the copper bumps, exposing the copper bumps; and A wafer, the wafer having a plurality of solder pads, each of which is configured with a solder material, and each of the solder materials is connected to one of the copper bumps, respectively. 2. The copper bump flip-chip package described in item 1 of the scope of patent application, further comprising an underfill material filled between the wafer and the first surface. 3. The copper bump flip-chip package as described in item 1 of the scope of the patent application, wherein the carrier is a ball grid array package substrate, and further includes a plurality of solder balls arranged at the second contacts, respectively. 4. The copper bump flip-chip package described in item 1 of the scope of the patent application, wherein the carrier is a pin grid array package substrate, and the second contacts are pin terminals. 5. The copper bump flip-chip package as described in item 1 of the patent application scope, wherein the carrier is a planar contact grid array package substrate. 6. The copper bump flip-chip package described in item 1 of the patent application scope further includes a packaging material to cover the wafer. 7. The copper bump flip-chip package described in item 1 of the patent application scope, which 10366twf1.ptc Page 17 1220068 _Case No. 92114521_Year_Month__ Sixth, the scope of the patent application in the copper bumps also includes a metal adhesive layer to connect with the welding material. 8. The copper bump flip-chip package described in item 7 of the scope of the patent application, wherein the material of the metal adhesive layer is selected from the group consisting of nickel-gold alloy, tin, and combinations thereof. 9. The copper bump flip-chip package according to item 1 of the scope of the patent application, wherein the soldering material includes a tin-lead alloy. 1 0. — A flip-chip package substrate applied to a flip-chip package of a wafer, wherein the wafer has a plurality of bonding pads, and the flip-chip package substrate includes: a carrier having a first surface and a corresponding second A surface, wherein the first surface has a plurality of first contacts, and the second surface has a plurality of second contacts, and the first contacts are electrically connected to the second contacts; a plurality of copper bumps Each of the copper bumps is respectively disposed on one of the first contacts and connected to it, and the copper bumps respectively correspond to one of the solder pads and are suitable for being connected to the wafers. Solder pad connection; and a solder mask layer disposed on the first surface between the copper bumps, exposing the copper bumps. 1 1. The flip-chip package substrate as described in item 10 of the scope of patent application, wherein a surface of each of the copper bumps is provided with a metal adhesive layer. 1 2. The flip-chip package substrate as described in item 11 of the scope of patent application, wherein the material of the metal adhesion layer is selected from the group consisting of nickel-gold alloy, tin and combinations thereof. 1 3. The flip-chip package substrate as described in item 10 of the scope of patent application, wherein the carrier is a ball grid array package substrate, and further includes a plurality of solder balls 10366twf1.ptc Page 18 1220068 _Case No. 92114521_Year Month Day Amendment_ Sixth, the scope of patent application is arranged at these second contacts respectively. 14. The flip-chip package substrate as described in item 10 of the scope of patent application, wherein the carrier is a pin grid array package substrate, and the second contacts are pin terminals. 15. The flip-chip package substrate as described in item 10 of the scope of patent application, wherein the carrier is a planar contact grid array package substrate. 16. The flip-chip package substrate as described in item 10 of the scope of patent application, wherein the carrier is a laminated board. 17. A process for manufacturing a flip-chip package substrate includes: providing a carrier having a first surface and a corresponding second surface, wherein the first surface has a plurality of first contacts and the second surface has A plurality of second contacts, the first contacts being electrically connected to the second contacts; forming a solder mask layer on the first surface; removing a part of the solder mask layer to expose the first contacts A contact; electroless plating a sub-layer formed on the surface of the solder mask layer and the first contacts; forming a patterned photoresist layer on the surface of the solder mask layer and exposing the first contacts; Copper plating, forming a copper bump on the surface of each of the first contacts, and removing the patterned photoresist layer and the seed layer. 18 · The flip-chip substrate manufacturing process described in item 17 of the scope of patent application, further comprising electroless plating a metal adhesive layer on the surfaces of the copper bumps, wherein the gold 10366twf1.ptc Page 19 1220068 _Case No. 92114521_Year Month Date Amendment_ VI. Scope of Patent Application The material of the adhesive layer is selected from the group consisting of nickel-gold alloy, tin and combinations thereof. 19. According to the flip-chip substrate manufacturing process described in item 17 of the scope of patent application, before the electroless plating of the seed layer, it further comprises a step of removing glue residue and surface roughening. 20. The flip-chip substrate manufacturing process according to item 19 in the scope of the patent application, wherein the steps of removing slag and surface roughening include surface treatment with one of potassium permanganate and sodium permanganate. 2 1. The process for manufacturing a flip-chip substrate according to item 17 of the scope of patent application, wherein the fresh cover layer is a dry film and is formed on the first surface in a laminating manner. 2 2. The flip-chip substrate manufacturing process as described in item 17 of the scope of patent application, wherein the solder mask layer is formed on the first surface by a coating method. 2 3. The process for manufacturing a flip-chip substrate according to item 17 in the scope of the patent application, wherein the method of removing a part of the solder mask layer includes laser drilling. 2 4. The process for manufacturing a flip-chip substrate as described in item 17 of the scope of patent application, wherein the solder mask layer is a photosensitive material, and the method of removing a part of the solder mask layer includes lithography. 25. The process for manufacturing a flip-chip substrate according to item 17 in the scope of the patent application, wherein the seed layer is copper, and the method for forming the seed layer includes electroless copper plating. 2 6. — A flip chip packaging process, including: providing a carrier having a first surface and a corresponding second surface, wherein the first surface has a plurality of first contacts and the second surface has a plurality of Second contacts, the first contacts are electrically connected to the second contacts; 10366twfl.ptc Page 20 1220068 _Case No. 92114521_Year Month and Day Amendment_ Sixth, the scope of the patent application forms a solder mask layer on the first surface; remove part of the solder mask layer to expose the first contacts Electroless plating a sub-layer formed on the surface of the solder mask layer and the first contacts; forming a patterned photoresist layer on the surface of the solder mask layer and exposing the first contacts; copper plating Forming a copper bump on the surface of each of the first contacts; removing the patterned photoresist layer and the seed layer; providing a wafer having a plurality of solder pads corresponding to the copper bumps, A soldering material is respectively disposed on the surfaces of the soldering pads; a flip-chip step is performed, and each of the copper bumps and one of the corresponding soldering pads are connected by the soldering material. 2 7. According to the flip-chip packaging process described in item 26 of the patent application scope, after removing the patterned photoresist layer and the seed layer, it further comprises electroless plating a metal adhesive layer on the surfaces of the copper bumps, wherein the metal The material of the adhesive layer is selected from the group consisting of nickel-gold alloy, tin and combinations thereof. 2 8. The flip-chip packaging process described in item 26 of the scope of patent application, before the electroless plating of the seed layer, further includes a step of removing glue residue and surface roughening. 29. The flip-chip packaging process according to item 28 of the scope of the patent application, wherein the steps of removing the slag and surface roughening include surface treatment with one of potassium permanganate and sodium permanganate. 30. The flip-chip packaging process as described in item 26 of the scope of patent application, further including an underfill process, an underfill is filled between the wafer and the first surface. 10366twf1.ptc Page 21 1220068 _Case No. 92114521_Year Month Date Amend_ Sixth, the scope of patent application Materials. 31. The flip-chip packaging process as described in item 26 of the patent application scope further includes an adhesive process to cover the chip with a packaging material. 3 2. The flip-chip packaging process as described in item 26 of the scope of patent application, wherein the solder mask layer is a dry film, which is formed on the first surface in a laminating manner. The flip-chip packaging process according to item 6, wherein the solder mask layer is formed on the first surface in a coating manner. 3 4. The flip-chip packaging process according to item 26 of the scope of patent application, wherein the method of removing part of the solder mask layer includes laser drilling. 3 5. The flip-chip packaging process as described in item 26 of the patent application scope, wherein the solder mask layer is a photosensitive material, and the method of removing a part of the solder mask layer includes lithography. 36. The flip-chip packaging process as described in item 26 of the patent application scope, wherein the seed layer is copper, and the method for forming the seed layer includes electroless copper plating. 10366twfl.ptc Page 22