1299563 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種P通道快閃記憶體裝置，且特別 是有關於一種具有含鍺通道區之P通道快閃記憶體裝置。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a P-channel flash memory device, and more particularly to a P-channel flash memory device having a germanium-containing channel region. [Prior Art]
非揮發性快閃記憶體被提出後，引起各界研究單位注 意。時至今日’其技術已成熟，並應用於各種不同領域之 中’如風靡全球蘋果電腦商品j_p〇d，即便是此快閃記憶體 應用之一。且根據市調公司Web-Feet Research的一份報 告指出’整體快閃記憶體市場會以每年超過10%的比例成 長。 隨著電子元件縮小化，造成現今電子產品效能強大， 同時也強調快速、省電、高密集度以及可攜性。其中，而 依產品本身功能不同而有不同的程式化操作模式，而最主 要有以下兩種：1、通道熱電子注入機制（CHE)，速度快但 效率低，這樣的操作模式適合配合N0R的架構形成一個系 統，應用於電腦的 BIOS(Basic mput 〇utput system) ; 2After the non-volatile flash memory was put forward, it attracted the attention of researchers from all walks of life. Today, its technology has matured and is used in a variety of different fields, such as the popular Apple computer product j_p〇d, even one of the flash memory applications. According to a report by the market-adjusted company Web-Feet Research, the overall flash memory market will grow by more than 10% per year. With the shrinking of electronic components, today's electronic products are powerful, while also emphasizing fast, power-saving, high-density and portability. Among them, depending on the function of the product itself, there are different stylized operation modes, and the main ones are as follows: 1. Channel hot electron injection mechanism (CHE), fast but low efficiency, such operation mode is suitable for matching with NOR The architecture forms a system for the BIOS of the computer (Basic mput 〇utput system); 2
Fow丨er-Nordheim注入機制（FN)，效率高但速度慢可配 合NAND架構組織成高密集度的記憶體產品，如隨身碟、 MP3播放器。 近年來已有專利提出_些方法來改進快閃記憶體元件 工作效能’ *中華民國專利公開編號2〇〇421346所示，利 用調變偏壓條件來提高快閃記憶體的寫人速度；又如中華 民國專利公告編號577172所示，改變快閃記憶體的結構來 5 1299563 達到雙位70儲存。除此之外，於美國電子電機協會（丨EEE) 所舉辦知名研討會中（丨EDM，NVMT)，矽化鍺合金被提出 可應用於N型快閃記憶體，進而提高初始通道載子引發二 -人電子注入（CHISEL)速度，例如D· l· Kencke等人發表 ^ IEDM Tech. Dig., pages 105-108, 2000.. L. M. Weltzer 等人發表在 Non-Volatile Memory Technology Symposium， 2004，15-17, pages 31 · 33。 ☆除了 Nit道快閃記龍外，p通道㈣記憶體也是另 又矚目的„己憶體元件。第’圖係繪示習知p通道快閃記 憶體的剖面示意圖。P通道快閃記憶體係在N型半導體基 底11上以P型離子摻雜形成源汲極12、17。穿遂氧化層The Fow丨er-Nordheim Injection Mechanism (FN), high efficiency but slow speed, can be combined with NAND architecture to organize into high-density memory products such as flash drives and MP3 players. In recent years, patents have been proposed to improve the performance of flash memory components. * The Republic of China Patent Publication No. 2〇〇421346 shows the use of modulation bias conditions to improve the writing speed of flash memory. As shown in the Republic of China Patent Bulletin No. 577172, the structure of the flash memory is changed to 5 1299563 to achieve double-bit 70 storage. In addition, in the well-known seminar held by the American Electro-Electrical Machinery Association (丨EEE) (丨EDM, NVMT), bismuth telluride alloy was proposed to be applied to N-type flash memory, thereby improving the initial channel carrier induced - Human Electron Injection (CHISEL) speed, for example, D. l. Kencke et al. published by IEDM Tech. Dig., pages 105-108, 2000.. LM Weltzer et al., published in Non-Volatile Memory Technology Symposium, 2004, 15- 17, pages 31 · 33. ☆In addition to the Nit Road flashing dragon, the p-channel (four) memory is also another eye-catching component. The 'picture' shows the cross-section of the conventional p-channel flash memory. The P-channel flash memory system is The source drains 12, 17 are formed by doping with P-type ions on the N-type semiconductor substrate 11.
予動閘極13、閘間介電層15及控制閘極^依序位於 牛導體基底11上之丄甬请P -沪邏親1 D 道快閃記憶體與 輯7"件p通道金氧半導體電晶體極為類似，最大不 同在於快閃記憶體多了一声多a 个 m 夕了層夕日日矽汙動閘極（Floating on 存電荷，並依料閘極13中有無電荷來 通道載子、主° l P通道快閃記憶體中’除了耳熟能詳的熱 献載子穿隧注人外’尚可利料對帶穿随 制（BBHE)。相對於通道熱載子注人，此 也接> = /，、、载子誘發注人方法有較高的注人效率，同時 也提南了穿隧氧化層的可靠度。 丰门日守 相較於靜態隨機存取記憶體（SR 6個電晶i#而一 a )母δ己憶胞需要 是速产=_憶體會有較高的密集度，但是即令 、又父陕的Ρ通道快閃記憶體，也比 體的速度慢了的Q / a 静機存取記憶 個數量級。因此，如何提升快閃記憶體 1299563 的速度而使快閃記憶體寫入速度，幾乎與SRAM速度相當 (10 sec) ’並且具有咼密集度（快閃記憶體每一記憶胞為— 個電晶體）與非揮發性記憶的優點，是一個非常重要的課 題。 另外，鍺合金在提升金氧半導體電晶體的效能上，扮 演了一個重要的角色，例如，以矽化鍺合金為通道的調制 掺雜場效電晶體（MODFET)，或是利用矽化鍺當作汲極或源 極，進而改善短通道效應、汲極導致能障下降效應⑴旧匕）、 及本體碰穿效應（Punch-through)。於覌今英代爾微處理器 (Intel Micro Processor)則是利用矽化鍺與矽的晶格常數 差，而施加應力於矽或是矽化鍺，使其能帶產生變化，提 高通道載子遷移率，增加輸出電流，進而提高晶片處理速 度效能。 【發明内容】 因此，為了提升P通道快閃記憶體的速度，本發明的 長:供種P通道快閃兄憶體結構，能較習知ρ通道快閃記 憶體結構具有較快的寫入速度。 本發明提供一種P通道快閃記憶體結構，係以矽化鍺 或鍺形成通道區，相較於習知的矽通道P通道快閃記憶 體’快閃記憶體的速度提高至少10倍以上。 本發明提供一種P通道快閃記憶體結構，係以矽化鍺 或鍺形成通道區，可增加P通道快閃記憶體的穿遂電流。 根據帶對帶穿隧效應的基本物理機制，若要提高p通 道快閃記憶體此穿隧電流，進而增加p通道快閃記^隱體的 7 1299563 寫入速度，由下列公式，扁厶 式中，G係為帶對帶穿遂電 Ϊ發生率、九仰和8•抑均為-特定數值、E為電場強 又且6為能帶間距，可知，可以藉著兩種方法，—是提高 電場㈤’但因為提高電場會對元件造成傷害，而降低元 件可靠度·，二是選擇較低能帶（Eg)的半導體材料，於是 選擇使用較小能帶的材料，如：ϋ神㈣合金或鍺，當 作Ρ型㈣記憶體的表面料，應可提高帶對帶穿遂電流The pre-action gate 13, the inter-gate dielectric layer 15 and the control gate are sequentially located on the base 11 of the cattle conductor. P-Shanghai Logic 1 D-channel flash memory and series 7" The semiconductor transistor is very similar. The biggest difference is that the flash memory has more than one m, and the floating gate is floating on the surface. In the main ° l P channel flash memory, in addition to the well-known hot-selling carrier through the tunnel, the singularity of the BBHE is compared with the hot carrier of the channel. ; = /,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Electro-crystal i# and a) The mother δ self-recalling cell needs to be a fast-growing product. _Recalling the body will have a higher density, but the immediate and the parent-speaking Ρ channel flash memory is also slower than the body speed. Q / a The static memory access memory is an order of magnitude. Therefore, how to increase the speed of the flash memory 1299563 to make the flash memory write speed Almost the speed of SRAM (10 sec) and the advantages of 咼 density (flash memory for each memory cell) and non-volatile memory is a very important issue. It plays an important role in improving the performance of MOS transistors, for example, a modulated doped field effect transistor (MODFET) with a bismuth telluride alloy as a channel, or a bismuth or source using a bismuth telluride. In turn, the short channel effect is improved, the bungee is reduced, and the energy barrier is reduced (1) old 匕), and the bulk collision effect (Punch-through). In this case, the Intel Micro Processor uses the difference in lattice constant between bismuth and antimony, and applies stress to enthalpy or bismuth, which causes the band to change and improve the channel carrier mobility. Increase the output current, which in turn increases the efficiency of wafer processing. SUMMARY OF THE INVENTION Therefore, in order to improve the speed of the P-channel flash memory, the length of the present invention: for the P-channel flashing brother-remembering structure, can have a faster writing than the conventional ρ-channel flash memory structure. speed. The present invention provides a P-channel flash memory structure in which channel regions are formed by strontium telluride or germanium, which is at least 10 times faster than conventional 矽 channel P-channel flash memory' flash memory. The invention provides a P-channel flash memory structure, which forms a channel region by using bismuth or bismuth, which can increase the puncturing current of the P-channel flash memory. According to the basic physical mechanism of band-to-band tunneling, if you want to increase the tunneling current of the p-channel flash memory, and then increase the write speed of the p-channel flash memory, the 7 1299563 write speed is determined by the following formula. , G system is the band-to-band 遂 遂 、 、 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九 九Electric field (5) 'But because the electric field increases the damage to the components, and the reliability of the components is reduced, the second is to select the lower energy band (Eg) semiconductor material, so choose to use a smaller energy band material, such as: ϋ神(四)合金Or 锗, as the surface material of the Ρ type (4) memory, should increase the current through the belt
發生率（G’’進而增加Ρ通道快閃記憶體的穿遂電流以 加速Ρ通道快閃記憶體的寫速度。 G = Α ΒΤΒΤ '^ ^χρ(^Β.ΒΤΒΓ 本發明主要是以帶對帶穿随熱載子注入（BBHE)的物理 機制為基礎，進一步利用此機制來提高P通道快閃記憶體 的寫入速度。帶對帶穿隧熱載子注入的操作方法，是於閘 極端施加-正偏壓’同時在没極端施加_負偏壓，這將會 ^成在閘極與沒極的重疊處會有很大的電場，使得重疊處 靠近介面的能帶會有很大的能帶彎曲（Band Bending)，於 是在此重疊區域產會因為帶對帶穿随效應而產生電子電洞 對’其中的電子被側向電場加速而得収夠能量，跨越穿 遂氧化層的能障’完成寫人。這樣的寫人方式有很高的注 入效率。 操作寫人時，可《提高帶對帶穿隨電流，造成更多的 電子被側向電場加速得到能量以跨越穿隧氧化層，提高閘 極注入電流’進而提高寫入速度。 8 1299563 •另外，在本發明另一較佳實施例中，提供一種P通道 2閃圮憶體結構，係以矽化鍺或鍺形成通道區，並在通道 品及穿遂氧化層間形成一單晶矽層，相較於習知的矽通道P ^道快閃記憶體’快閃記憶體的速度提高至少1G倍以上。 通道區及穿遂氧化㈣單晶碎層的形&，可進一步提升石夕 鍺或疋鍺與牙隧氧化層間介面性質的穩定性，以避免降 低元件工作性能，或是避免降低讀取電流（Read Current), 進而能提高讀取電流。 曰在本發明再一較佳實施例中，提供一種p通道快閃記 憶體結構，係以矽化鍺或鍺形成通道區，並以金屬氧化物 代氧化矽以形成穿遂氧化層。由於氧化矽與矽化鍺或是 錯之間的介面性質較不理想，但是金屬氧化物，例如氧化 給^ Hf〇2)和碎化鍺或是鍺之間的介面性質良好而且氧化 銓能提供較氧化矽更低的電子跨越能障（AEc)，因此，本 實施例所提供一種P通道快閃記憶體結構，不只具有較快 的寫入速度，更具有穩定的通道與穿遂氧化層介面，進而 能提高讀取電流。 習知利用電晶體組合而成的SRAM，但其缺點為低密 集度，並且只有在有電源供應的情形下才能儲存資料 (Volatile Memory)。而在本發明中利用矽化鍺及鍺等小能 帶半導體材料來提高P_型快閃記憶體寫入速度，幾乎$ SRAM速度相當（1〇-9咖），並且具有高密集度與非揮發性 記憶的優點，所以，運用本發明所提供p_型快閃記惊體， 可用來取代現今具有SRAM或是-些高速的記㈣穿置 另外，現今許多可攜式電子裝置強調低功;、低操作 1299563 ㈣的需求’運用本發明所提供卜型快閃記憶體，因使用 車乂】的月匕页材料當作表面通道或是埋藏通道，使得在一樣 的偏【條件下就具有大量的電子電洞對產生，進而提高寫 入速度，換句話說，也就是可以在低電壓操作下，便產生 與傳統p-型快閃記憶體一樣量的電子電洞對，達到低電壓 的操作模式，有利於整體記憶體系統的電路設計。 【實施方式】 第2圖係繪示本發明第一較佳實施之例p通道快閃記 憶體的剖面示意圖。P通道快閃記憶體係在N型半導體基 底21上以p型離子摻雜形成源汲極22、27。含鍺材料層 28、穿遂氧化層26、浮動閘極23、閘間介電層25及控制 閘極24依序位於半導體基底11之上，其中含鍺材料層28 係作為通道區之用。含鍺材料層28可以為矽化鍺材料或是 鍺金屬。 利用二維半導體元件模擬軟體MEDIC丨對第2圖所示 之P通道快閃記憶體進行模擬，以不同鍺含量的矽化鍺合 至以及純鍺g作p通道快閃記憶體表面通道，模擬帶對帶 ，穿隨電流G即）與閘極注入電流（/g)與表面通道鍺含量的關 係，模擬結果如第4圖所示。在矽化鍺合金為表面通道的 P通道快閃記憶體，於相同的BBHE操作條件之下 (Vg = 1〇V，Vd=-6V)，可觀察到，隨著鍺含量的提高，帶對 帶穿遂電流也同時被提高，造成大量的電子被側向電場加 速，進而得到較大的閘極穿隧電流。其中當鍺含量達到8〇% 時，與傳統單晶矽表面通道（鍺含量為，，〇%，，）比較，帶對 1299563 帶牙隨電流，/^(/ββ)，從傳統單晶石夕表面通道之1 〇_7安典/ 微米提升至2·7Χ1 0·4安培/微米，被提高約27〇〇倍。再以 純鍺為表面通道的P通道快閃記憶體為例，其帶對帶穿隧 電流也提高了將近1000倍，造成閘極穿隧電流也大量提 高。即使將鍺含量降到20%，其帶對帶穿隧電流也提高了 超過10倍。 第5圖係繪示具有不同鍺含量之矽化鍺合金為表面通 道的P通道快閃記憶體的寫入速度。在閘極穿隧電流提高 之後，便提高P通道快閃記憶體的寫入速度。當矽化鍺合 金中的鍺含量達嶋時，可在）奈秒（价9秒）内使臨界; 壓’示移l(AVth)達到2伏特，比傳統單晶碎表面通道的寫 入速度快約2000倍。以純鍺表面通道的p通道快閃記憶 ，，其寫入速度亦可在約2奈秒㈣价^少），使臨界電壓 你移里UVth)達到2伏特，其寫入速度也提高約1〇〇〇倍· 即使將鍺含量降到20%，其寫入速度亦可在約2〇〇 ^秒 (2X10秒），使臨界電壓漂移量（△▽“達到2伏特，比傳 統單晶矽表面通道的寫入速度快約2〇倍。 、由第5圖中可以發現，應用矽化鍺合金或純鍺於p通 道&閃&憶體來提高帶對帶穿遂注人（BBHE)速度，遠比前 人利用石夕化鍺合金於N型快閃記憶體，來提高初始通道載 子引，二次電子注入（CHISEL)速度，快上更多。 第3圖係繪示本發明第二較佳實施之例P通道快閃記 It體的剖面不意圖。P通道快閃記憶體係在N型半導體基 底3\上以P型離子摻雜形成源沒極32、37。含鍺材料層 8單曰曰石夕層39、穿遂氧化層36、浮動閘極33、閘間介 1299563 電層35及控制閘極34依序位於半導體基底11之上，其中 含鍺材料層38係作為通道區之用。含鍺材料層38可以為 矽化鍺材料或是鍺金屬而單晶矽層39的厚度不超過20奈 米。 在含鍺材料層38，例如矽化鍺通道或純鍺通道，與穿 隧氧化層36之間插入一單晶矽層39，期望改進含鍺材料 層38與穿隧氧化層36之間的介面特性。同樣使用二維半 導體元件模擬軟體MEDICI對笫3圖所示之p通道快閃記 憶體進行模擬，只是將其中矽化鍺合金的比例固定在 Si〇.6Ge〇.4。 第6圖係繪示帶對帶穿隧電流（/ββ)與閘極注入電流（y 與表面通道單晶矽層厚度關係之模擬結果。此新穎矽化鍺 埋藏P通道快閃記憶體於相同的BBHE操作條件之下 (Vg = 10V，Vd=-6V)，可觀察到，帶對帶穿隧電流（/即)及閘 極注入電流（/g)隨著表面單晶矽厚度的增加而降低。因為矽 化鍺或純鍺通道被埋藏在距離表面較遠的地方，不在最大 電場處，造成矽化鍺或純鍺等小能帶材料的能帶不夠彎 曲，使得帶對帶穿1¾電流（/ββ)下降，進而降低閘極注入電 流。習知ρ通道快閃記憶體的閘極注入電流（/j約為1x1〇_Q 安培/微米。由第6圖可知，在無單晶矽層存在時，本實施 例之ρ通道快閃記憶體的閘極注入電流（/g)約為17χι〇_7 安培/微米。、Ik著含者通道表面上之單晶矽層39的厚度增 加到10奈米時，閘極注入電流（/g)約為6X1 (T8安培/微米， 為習知的60倍；當單晶石夕層的厚度達20奈米時，其問極 注入電流下降至UXW安培/微米，仍比純石夕基底p 12 1299563 通道快閃記憶體之閘極注入電流()高出〇 · 8倍。 第7圖係繪示具有不同厚度翠晶石夕層位於石夕化錯合金 表面通道之上的Ρ通道快閃記憶體的寫人速度。由第7圖 可知’ Ρ現著單晶矽層厚度增加，因閘極注入電流下降，進 而降低原有寫人速度。在無單㈣層存在時，本實施例之ρ ，道快閃記憶體可在2Χ10·8秒達到2伏特之臨界電壓漂移 量（△、）’當單晶石夕層39的厚度為2〇奈米時，則須約价6 秒才能達到2伏特臨界電壓漂移量（ΔΝΛ(ι)，但是與純石夕基 底Ρ通道快閃記憶體速度（約5Χ1()_5秒）相較，仍然快了 約2倍。雖然在含鍺材料層38與穿隧氧化層％之間插入 單晶石夕層39可以改善介面特性，但卻影響石夕化錯埋藏μ 道快閃記憶體的寫人速度，但是，由模擬結果可知，在單 晶石夕層39的厚度不超過2Q奈米的情形下，本實施例〇 通道快閃記憶體仍具有較習知ρ通道快閃記憶體較大的對 帶穿隧電流（/ββ)與閘極注入電流（/g)，以及較快的寫人速 度。因此’可藉著調整單晶韻的厚度，例如不超過2〇奈 米’才能使魏錯埋藏ρ通道快閃記憶體有好的介面特性 外’仍維持高速的寫入速度。 應用石夕化錯合金或純鍺為表面通道或埋藏通道的ρ通 道快閃記憶體’除高速操作外’亦可降低操作電壓來達到 相同的寫入速度。"圖係繪示在相同閑極電壓（、）下 具有相同寫人速度之ρ通道快閃記憶體的單晶@層厚9度與 沒極電壓（Vd)間的ρ通道快閃記憶體具有石^匕 鍺合金比例為SiQ.6GeQ.4表㈣化錯通道，如第8圖所示， 在不同單晶⑦層的厚度下，隨著單晶⑦層的厚度下降，若 13 1299563 二底P通道快閃記憶體操作在Vg=10伏特和 合不斷 同寫人速度，其操作所需线極電麼（vd) :需-3 當單晶矽層的厚度為0時，沒極電墨(Vd) 通道快閃記憶體，汲極電壓（Vd)下降約=,切基底P 苐9圖係緣示本發明第三較佳實施之例 憶體的剖面示意圖。P通道快閃記憶體係在_半導體 1基己 ^ 41上w型離子摻雜形成源沒極42、仏含鍺材料層 、金屬氧化層46、浮動閘極43、閘間介電層的及 間極料依序位於半導體基底41之上，其中含錯材料層48 係作為通道區之用。含鍺材料層48可以為石夕化錯材料或是 鍺金屬。金屬氧化層46的材料可為氧化銓（Hf〇2)。 氧化給與石夕化錯和鍺金屬之間的介面特性相當良好， 並不遜於石夕基板和二氧化石夕之間的介面特性。利用二維半 導體元件模擬軟體MEmci對三種不同介面組合（SWA、 SiGe/Si〇2、SiGe/所〇2)的p通道快閃記憶體進行模擬， 具有不同通道/穿遂氧化層介面之p通道快閃記憶體的寫入 速度’其結果繪示於第1〇圖。在此次模擬中，石夕化錯中的 鍺含量固^為4G%，亦即為SiQ6GeQ4，並在相同的寫入偏 壓條件之下（Vg = 1〇V，Vd=_6V)進行模擬。 由第10圖可知，當通道區/穿遂氧化層介面為Si/Si〇2 之傳統快閃記憶體，約需2X10-6秒以達到2伏特之臨界電 壓漂移量（Δν^);當通道區/穿遂氧化層介面為Sj/Hf〇2i 快閃記憶體，約需5X1 (T7秒以達到2伏特之臨界電壓漂移 量（AVth);當通道區/穿遂氧化層介面為s丨〇6Ge〇4/S|〇2i Ϊ299563 記憶體’約需2X10·8秒以達到2伏特之臨界電1漂移 里（△、），當通道區/穿遂氧化層介面為si〇 6Ge^ η叫 之快閃記憶體，僅約需2_5X1G.9秒就可以達到2伏特之臨 界電壓漂移量（△ vth)。 當石夕化錯應用於p型快閃記憶體時，帶對帶穿隧引發 熱載子注入速度隨著鍺含量的上升而提高，而氧化铪的應 用，也能有效提高帶對帶穿随引發熱載子注入速度。值得 注意的是，切㈣與氧化給結合在—料，則能將兩者 各别提同BBHE的寫入速度綜合，也就是說，寫入 ，度能比單獨的使时化錯或是單獨的使用氧化給來的 南。更值得注意的是’氧⑽財化鍺和錯金屬之間的介 特!·生相田良好’無須插人單晶⑦層即可解決⑦化錯和錯 金屬與氧化矽間介面較不理想之問題。 =然本發明已以一較佳實施例揭露如上，然其並非用 以限^本發明，任何熟習此技藝者，在不脫離本發明之精 神和乾圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂，所附圖式之詳細說明如下： 第1圖係缘示習知P通道快閃記憶體的剖面示意圖； 第2圖係繪示本發明第一較佳實施之例P通道快閃記 憶體的剖面示意圖； 15 1299563 第3圖係繪示本發明第二較佳實施之例p通道快閃記 憶體的剖面示意圖； 第4圖係繪示帶對帶穿隨電流Μ與閘極注入電流⑹ 與第3圖之Ρ通道快閃記憶體表面通道鍺含量的關係圖；The incidence rate (G'' further increases the transmission current of the Ρ channel flash memory to accelerate the writing speed of the Ρ channel flash memory. G = Α ΒΤΒΤ '^ ^χρ(^Β.ΒΤΒΓ The present invention is mainly in the pair Based on the physical mechanism of hot carrier injection (BBHE), this mechanism is further used to improve the writing speed of P-channel flash memory. The operation method of band-to-band tunneling hot carrier injection is at the gate terminal. Applying a positive bias while simultaneously applying no negative bias, this will result in a large electric field at the junction of the gate and the pole, so that the energy band near the interface will be large. Band Bending, so in this overlapping area, the electrons are generated by the band-to-band effect, and the electrons in the electrons are accelerated by the lateral electric field to obtain energy. The barrier 'completes the writer. This way of writing people has a high injection efficiency. When the operator writes, it can improve the band wear current, causing more electrons to be accelerated by the lateral electric field to obtain energy to cross the tunnel oxidation. Layer, increase gate injection current' Increasing the writing speed. 8 1299563 • In addition, in another preferred embodiment of the present invention, a P-channel 2 flash memory structure is provided, which forms a channel region with germanium or germanium, and is oxidized in the channel and the via. A single crystal germanium layer is formed between the layers, which is at least 1 G times higher than that of the conventional germanium channel P^-channel flash memory. The channel region and the shape of the tantalum oxide (four) single crystal layer are & , can further improve the stability of the interface properties between Shi Xiyu or 疋锗 and the tunnel oxide layer, in order to avoid reducing the working performance of the component, or to avoid reducing the read current (Read Current), thereby improving the read current. In still another preferred embodiment of the present invention, there is provided a p-channel flash memory structure in which a channel region is formed by bismuth telluride or germanium, and yttrium oxide is formed by metal oxide to form a tantalum oxide layer. The interface between 锗 or 性质 is less than ideal, but the interface between metal oxides, such as oxidation to Hf〇2) and mash or ruthenium, is good and yttrium oxide provides lower ruthenium oxide. Electronic spanning energy (AEc), therefore, the P-channel flash memory structure provided in this embodiment not only has a faster writing speed, but also has a stable channel and a tantalum oxide layer interface, thereby improving the read current. SRAMs using a combination of transistors, but have the disadvantage of low density, and can only store data (Volatile Memory) in the case of power supply. In the present invention, small-band semiconductor materials such as germanium and germanium are utilized. To improve the P_ type flash memory write speed, almost $ SRAM speed is equivalent (1〇-9 coffee), and has the advantages of high density and non-volatile memory, so the p_ type provided by the present invention is fast. Flash flashing, can be used to replace today's SRAM or some high-speed recording (four) wearing. In addition, many portable electronic devices today emphasize low-power; low-operation 1929563 (four) needs 'using the present invention to provide flash The memory, because of the use of the rut of the moon 匕 page material as a surface channel or buried channel, so that under the same bias [there are a large number of electronic hole pairs generated, thereby increasing the write speed , In other words, can operate at low voltage, it generates a conventional p- type flash memory as the amount of electron-hole pairs, to achieve a low voltage mode of operation, the circuit design is conducive to the overall system memory. [Embodiment] Fig. 2 is a cross-sectional view showing a p-channel flash memory of a first preferred embodiment of the present invention. The P-channel flash memory system is formed on the N-type semiconductor substrate 21 by p-type ion doping to form source drains 22, 27. The germanium-containing material layer 28, the passivation oxide layer 26, the floating gate 23, the inter-gate dielectric layer 25, and the control gate 24 are sequentially disposed on the semiconductor substrate 11, wherein the germanium-containing material layer 28 serves as a channel region. The layer of germanium containing material 28 may be a germanium telluride material or a base metal. The P-channel flash memory shown in Fig. 2 was simulated by using the two-dimensional semiconductor component simulation software MEDIC丨, and the p-flash memory surface channel was simulated with different germanium contents and pure germanium g as the p-channel flash memory surface channel. The relationship between the band, the wear current G, and the gate injection current (/g) and the surface channel 锗 content, the simulation results are shown in Figure 4. In the P-channel flash memory with the surface channel of bismuth telluride alloy, under the same BBHE operating conditions (Vg = 1〇V, Vd=-6V), it can be observed that with the increase of strontium content, the band is The passing current is also increased at the same time, causing a large amount of electrons to be accelerated by the lateral electric field, thereby obtaining a larger gate tunneling current. When the content of strontium reaches 8〇%, compared with the surface channel of traditional single crystal germanium (锗 content, 〇%,,), the band pair 1929563 has teeth with current, /^(/ββ), from traditional single crystal The surface of the eve surface is 〇_7Andian/micron is raised to 2·7Χ1 0·4 amps/μm, which is increased by about 27 times. Taking the P-channel flash memory with pure 锗 as the surface channel as an example, the band-to-band tunneling current is also increased by nearly 1000 times, resulting in a large increase in gate tunneling current. Even if the germanium content is reduced to 20%, the band-to-band tunneling current is increased by more than 10 times. Fig. 5 is a graph showing the writing speed of a P-channel flash memory having a bismuth telluride alloy having a different germanium content as a surface channel. After the gate tunneling current is increased, the write speed of the P-channel flash memory is increased. When the bismuth content in the bismuth telluride alloy reaches 嶋, the critical value can be made in nanoseconds (valence 9 seconds); the pressure shift 1 (AVth) reaches 2 volts, which is faster than the writing speed of the conventional single crystal broken surface channel. About 2000 times. The p-channel flash memory with pure surface channel, the writing speed can also be less than 2 nanoseconds (four) price, so that the threshold voltage you move to UVth) reaches 2 volts, and the writing speed is also increased by about 1〇. 〇〇倍· Even if the yttrium content is reduced to 20%, the writing speed can be about 2 〇〇 ^ sec (2X10 sec), so that the threshold voltage drift amount (△ ▽ "up to 2 volts, than the conventional single crystal 矽 surface The writing speed of the channel is about 2 times faster. It can be found from Fig. 5 that the use of bismuth telluride or pure germanium in p-channel & flash & memory to improve the speed of the belt-to-belt (BBHE) , far more than the former use of Shi Xihuayu alloy in N-type flash memory, to improve the initial channel carrier, secondary electron injection (CHISEL) speed, faster on. Figure 3 shows the invention The preferred embodiment of the P-channel flash flash is not intended for the cross section of the body. The P-channel flash memory system is doped with P-type ions on the N-type semiconductor substrate 3\ to form source dipoles 32, 37. The germanium-containing material layer 8 The monolithic layer 39, the tantalum oxide layer 36, the floating gate 33, the gate dielectric 1929563, the electrical layer 35 and the control gate 34 are sequentially located in the middle. Above the bulk substrate 11, wherein the germanium-containing material layer 38 serves as a channel region. The germanium-containing material layer 38 may be a germanium telluride material or a germanium metal and the single crystal germanium layer 39 may have a thickness of no more than 20 nanometers. Inserting a single crystal germanium layer 39 between the material layer 38, such as a germanium germanium channel or a germanium channel, and the tunnel oxide layer 36, is desired to improve the interface characteristics between the germanium containing material layer 38 and the tunnel oxide layer 36. The two-dimensional semiconductor component simulation software MEDICI simulates the p-channel flash memory shown in Fig. 3, except that the proportion of the antimony telluride alloy is fixed at Si〇.6Ge〇.4. Fig. 6 shows the tape pair Simulation results of tunneling current (/ββ) and gate injection current (y vs. surface channel monolayer thickness). This novel bismuth buried P-channel flash memory is under the same BBHE operating conditions (Vg = 10V). , Vd = -6V), it can be observed that the band-to-band tunneling current (/) and the gate injection current (/g) decrease as the thickness of the surface single crystal germanium increases. Because the germanium telluride or pure germanium channel is Buried in a place far from the surface, not at the maximum electric field, resulting in The energy band of the small energy band material such as bismuth telluride or pure germanium is not sufficiently curved, so that the current of the strip is reduced by 13⁄4 current (/ββ), thereby reducing the gate injection current. The gate injection current of the conventional ρ channel flash memory ( /j is about 1x1〇_Q Amperes/μm. As can be seen from Fig. 6, the gate injection current (/g) of the p-channel flash memory of this embodiment is about 17χι in the absence of a single crystal germanium layer. _7 amps/μm. When the thickness of the single crystal germanium layer 39 on the surface of the Ik-bearing channel is increased to 10 nm, the gate injection current (/g) is about 6X1 (T8 amps/μm, which is conventional). 60 times; when the thickness of the single crystal layer reaches 20 nm, the polarity of the injection current drops to UXW amps/μm, still more than the gate injection current of the pure flash slab p 12 1299563 channel flash memory () 8 times higher than 〇. Fig. 7 is a diagram showing the writing speed of a stroboscopic flash memory having a different thickness of emeraldite layer on the surface channel of the Shihuahua alloy. It can be seen from Fig. 7 that the thickness of the single crystal layer increases, and the gate injection current decreases, which in turn reduces the original writing speed. In the absence of a single (four) layer, the ρ, the track flash memory of the present embodiment can reach a threshold voltage drift amount (Δ,) of 2 volts at 2 Χ 10 · 8 seconds ' when the thickness of the single crystal layer 39 is 2 〇 For nanometers, it takes about 6 seconds to reach the 2 volt threshold voltage drift (ΔΝΛ(ι), but it is still faster than the pure stone Ρ base channel flash memory speed (about 5Χ1()_5 seconds). About 2 times. Although the insertion of the single crystal layer 39 between the germanium-containing material layer 38 and the tunneling oxide layer can improve the interface characteristics, it affects the writing speed of the Shixia fault-buried μ-channel flash memory. However, it can be seen from the simulation results that in the case where the thickness of the single crystal layer 39 does not exceed 2Q nanometers, the channel flash memory of the present embodiment still has a larger pair of conventional ρ channel flash memory. With tunneling current (/ββ) and gate injection current (/g), and faster writing speed. Therefore, 'by adjusting the thickness of single crystal rhyme, for example, no more than 2 nanometers' can make Wei wrong Buried ρ channel flash memory has good interface characteristics and still maintains high speed writing speed. The ρ channel flash memory of the wrong alloy or pure tantalum is a surface channel or a buried channel. In addition to high-speed operation, the operating voltage can be lowered to achieve the same writing speed. The graph is shown at the same idle voltage ( The ρ channel flash memory with a single channel @layer thickness of 9 degrees and the immersion voltage (Vd) with the same writing speed is a ratio of SiQ.6GeQ.4 Table (4) Deformation channel, as shown in Figure 8, under the thickness of 7 layers of different single crystals, as the thickness of the 7-layer single crystal decreases, if 13 1299563 two-bottom P-channel flash memory operates at Vg=10 volts Harmony and writing speed, the line required for its operation (vd): need -3 When the thickness of the single crystal layer is 0, the electrodeless flash (Vd) channel flash memory, bungee voltage ( Vd) descent ==, the cut substrate P 苐9 is a cross-sectional view of the memory of the third preferred embodiment of the present invention. The P-channel flash memory system is doped with w-type ion on the semiconductor 1 Forming the source electrode 42, the germanium-containing germanium material layer, the metal oxide layer 46, the floating gate 43, the inter-gate dielectric layer, and the inter-electrode layer Located on the semiconductor substrate 41, the fault-containing material layer 48 serves as a channel region. The germanium-containing material layer 48 may be a stone-like material or a base metal. The material of the metal oxide layer 46 may be hafnium oxide (Hf〇). 2) The interfacial properties between the oxidation and the cerium and the ruthenium metal are quite good, which is not inferior to the interface characteristics between the shixi substrate and the ruthenium dioxide. The two-dimensional semiconductor device is used to simulate the software MEmci for three different interfaces. The p-channel flash memory of the combination (SWA, SiGe/Si〇2, SiGe/〇2) is simulated, and the write speed of the p-channel flash memory with different channels/through oxide interface is drawn. It is shown in Figure 1. In this simulation, the yttrium content in Shi Xihua is 4G%, which is SiQ6GeQ4, and under the same write bias condition (Vg = 1〇V, Vd = _6V) for simulation. It can be seen from Fig. 10 that when the channel area/through oxide layer interface is a conventional flash memory of Si/Si〇2, it takes about 2×10-6 seconds to reach a threshold voltage drift of 2 volts (Δν^); The area/through oxide interface is Sj/Hf〇2i flash memory, which requires about 5X1 (T7 seconds to achieve a threshold voltage drift of 2 volts (AVth); when the channel region/through oxide interface is s丨〇 6Ge〇4/S|〇2i Ϊ299563 Memory 'about 2X10·8 seconds to reach 2 volts of critical electric 1 drift (△,), when the channel area / through the oxide interface is si〇6Ge^ η called Flash memory, only about 2_5X1G.9 seconds can reach the threshold voltage drift of 2 volts (△ vth). When Shi Xihua is applied to p-type flash memory, band-to-band tunneling causes hot load The sub-injection rate increases with the increase of niobium content, and the application of niobium oxide can also effectively improve the injection speed of the belt-to-belt-inducing hot-loading. It is worth noting that the cutting (four) and oxidation are combined in the material. Can combine the two with the BBHE's write speed, that is, write, the degree can be more than the individual time is wrong or separate The use of oxidation to the south. More notable is the 'between oxygen (10) between the chemical and the wrong metal! · Good phase of the field 'no need to insert a single crystal 7 layer can solve 7 faults and wrong metals and oxidation The present invention has been described above with reference to a preferred embodiment. However, it is not intended to limit the invention, and anyone skilled in the art can be without departing from the spirit and scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. The following description and other objects, features and advantages of the present invention are intended to be The embodiment can be more clearly understood. The detailed description of the drawings is as follows: FIG. 1 is a schematic cross-sectional view showing a conventional P-channel flash memory; FIG. 2 is a view showing a first preferred embodiment of the present invention. A cross-sectional view of a P-channel flash memory; 15 1299563 FIG. 3 is a cross-sectional view showing a p-channel flash memory according to a second preferred embodiment of the present invention; and FIG. 4 is a cross-sectional view of the tape. Injection current with gate (6) and after Figure 3 FIG germanium content relationships surface CHANNEL flash memory;
第5圖係繪不Ρ通道快閃記憶體表面通道之鍺含量與 寫入速度之關係圖；Figure 5 is a graph showing the relationship between the germanium content of the channel surface of the flash memory and the write speed;
第6圖係繪不帶對帶穿隧電流（丨ΒΒ)與閘極注入電流 (lg)與Ρ通道快閃記憶體表面通道單晶矽層厚度之關係圖I 第7圖係繪不卩通道快閃記憶體表面通道上不同厚度 單晶石夕層與寫入速度之_係圖； 第8圖係繪示在相同閘極電壓（Vg)下具有相同寫入 速度之p通道快閃記憶體的單晶矽層厚度與汲極電壓（”vd 間的關係圖； 」 P通道快閃記 第9圖係繪示本發明第三較佳實施之例 憶體的剖面示意圖；以及 第1 〇圖係繪示P通道快閃記憶體之不同通道/穿 化層介面與寫入速度之關係圖。 氣 【主要元件符號說明】 11 ' 21、31、41 :半導體基底 12、22、32、42 :汲極 13 ' 23、33、43 :浮動閘極 14、24、34、44 :控制閘極 16 1299563 15、 25、35、45 :閘間介電層 16、 26、36 :穿隨氧化層 17、 27、37、47 :源極 28、38、48 :含鍺材料層 39 :單晶矽層 46 ··金屬氧化層Figure 6 shows the relationship between the tunneling current (丨ΒΒ) and the gate injection current (lg) and the thickness of the single-channel germanium layer on the surface channel of the flash memory. Figure 7 Figure 7 shows the channel P-line flash memory with different writing speeds of different thicknesses on the surface channel of the flash memory; Figure 8 shows the p-channel flash memory with the same writing speed at the same gate voltage (Vg) FIG. 9 is a cross-sectional view showing a memory cell of a third preferred embodiment of the present invention; and a first diagram showing a relationship between a thickness of a single crystal layer and a drain voltage ("vd relationship"; Diagram showing the relationship between different channel/through layer interface and write speed of P-channel flash memory. [Main component symbol description] 11 ' 21, 31, 41: semiconductor substrate 12, 22, 32, 42: 汲Pole 13 ' 23, 33, 43: floating gates 14, 24, 34, 44: control gate 16 1299563 15 , 25 , 35 , 45 : inter-gate dielectric layers 16, 26, 36: through the oxide layer 17, 27, 37, 47: source 28, 38, 48: layer containing germanium material 39: single crystal germanium layer 46 · metal oxide layer
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