TWI298500B - - Google Patents

Description

1298500 V. DESCRIPTION OF THE INVENTION (1) Technology to which the Invention pertains The present invention relates to a high speed SRAM, and more particularly to a single-ended high speed sense amplifier in a SRAM. The prior art has been invented due to various visual devices. The ejjjbeddecOSRAM memory technology has become an indispensable part of the future integrated display chip. In order to enable the embedded SRAM memory to read data at high speed, it can stably save data. Affected by internal operations. Most random access memory systems use a differential inductive amplifying circuit with a good common mode rejection ratio' but in a multiprocessing architecture, multiple memories are required. Based on the consideration of the wafer space, the use of single-ended sense amplifiers is greatly increased. Figure 1 shows a conventional single-ended inductive amplifying circuit. When the input signal v in is a low voltage level, the NM0S transistor is not conducting, NM0S is The crystal 12 boosts the voltage of the node A to a certain level, at which the (four) (10) transistor P1 6 and the NM0S transistor N16 of the inverter 16 are both turned on, so that the voltage level of the node B is between Vdd and Vss. The NM0S transistor 12 forms a negative feedback, so the node A cannot be charged to Vdd. When the input signal Vin is at a high voltage level, the nm〇S transistor 10 is turned on. The above node A is discharged, and the voltage of the node A is lowered to be lower than the threshold voltage of the inverter 16. At this time, the nm〇S transistor 12 will also be turned on, so that the voltage of the node A is between V ss and inverted. Between the threshold voltage values of the device 16, the voltage of the node A is thus limited to the vicinity of the threshold voltage.

When the input signal Vin is the local voltage level, the NM0S transistors N12 and NM0S

0702-7362TWF(nl);90P104;Rliu.ptd

1298500 V. INSTRUCTIONS (2) The transistor N1 〇 is turned on at the same time, forming a rate. The NM0S transistor N12 blocks the node = the time for consuming the static work to be *level, which is not conducive to = 増 addition - pulling the road surface When the selected memory cell connected to the plurality of read bit lines and a low voltage source is low logic, the read circuit is turned on so that the read cell is coupled to the memory cell, and the complex read bit is The power line is connected by a multiplexer and the second is reduced by ^ = low power, the voltage source and the complex read bit line: when the charging nickname is enabled, 'multiple reading lines and data lines should be charged to amplify the circuit' The input terminal is lightly connected to the reading data=, when the terminal voltage is lower than a critical level and the pre-charging signal is disabled, the accelerating circuit is turned on to accelerate the discharge of the input terminal; and one switch is coupled to the inductive amplifying circuit at one end thereof. The output end; and a latching circuit coupled to the other end of the open, when the pre-charge signal is enabled, the switch is open, when the pre-charged nickname is not enabled, the switch is turned on, and the output data of the latch-sensing amplifying circuit is . Hereinafter, the present invention will be described with reference to the drawings. Embodiment Fig. 2 is a view showing the architecture of a static random access memory (SRAM) in an embodiment of the present invention. As shown in Fig. 1, the SRAM of the present invention has a plurality of memory arrays A 0 to A 7 arranged in an array, and the read bit lines are respectively I circles.

0702-7362TW(nl); 90P104; RIiu.ptd No. 6 Buy 1298500 V. Invention Description (3) 〇~RBL7, II is selected by the multi-guard 110 to read the position of one of the arrays. The output of the multiplexer 110 is coupled to a read data line RDAT coupled to the inductive amplifying circuit 2A for accelerating the reading of the data of the memory unit. The memory arrays Α0~Α7 can receive the precharge signal RPC, the PM〇s transistor 15〇 source is coupled to a high voltage source VDD, and the drain is coupled to the read data line (10) and the gate is coupled to the precharge signal. RPC.

An NM0S transistor 1 〇5, which is used as a switch, one end is coupled to the output terminal SAOUT of the inductive amplifying circuit, and the gate is connected to the precharge signal Rpc, and one end is coupled to the latch circuit 130, which includes the inversion The inverter 1131 and the inverter 1132 form a latch circuit for latching the data of the inductive amplifying circuit 200 in a positive feedback manner. The D-type flip-flop 120 has a data input end coupled to the latch circuit 13A, and the logic data of the memory unit is latched by the clock signal RCLK.

Fig. 3 is a view showing the architecture of the memory array A in the embodiment of the present invention, and the other arrays have the same architecture. The memory array a includes memory cells C0 to C7, and the word read signals RWL〇 to RWL7 are respectively coupled to the read control terminals RWL of C0 to C7, and the read terminals RBL of C0 to C7 are all coupled to the read bits. The line RBL0, the PMOS transistor 151 source is coupled to the high voltage source VDD, the drain is coupled to the read bit line RBL0, and the gate is coupled to the precharge signal RPC. The PMOS transistor 152 has an electrical connection state similar to that of the PMOS transistor 151, and its drain is coupled to the other end of the read bit line RBL0 to prevent the propagation delay of the read bit line RBL0 at precharge. Figure 4 shows the memory cell C0 of the memory array A0 in the embodiment of the present invention.

〇702-7362TWF(nl);90P104;Rliu.ptd

1298500 V. Description of the invention (4) ------- Circuit diagram. Other memory units have the same circuit architecture. * * is coupled to the read bit line RBL0, the transistor M1 and the transistor M2 are connected in series. The body M1 is coupled to the read bit line RBL, and the transistor M2 is coupled to the low-level crystal VSS ' The gate of the crystal M1 is coupled to the read word line RWL〇, and the gate of the circuit is coupled to the complementary logic data terminal])B. The positron-2 inverter 1135 and the inverter 1136 form a sneak peek unit for latching logic data in a positive feedback manner, and the logic data terminal D and the complementary logic data 钿DB respectively store logic data of opposite polarities. The logic data terminal write transistor M4 is coupled to the write bit line WBL, and the complementary logic data ^DB is coupled to the complementary write bit line WBLB by the transistor M3. When the write signal WWL is enabled, The transistor "and the transistor ^ is turned on, and the complementary logic device" can be stored by the write bit line WBL and the complementary write bit line WBLB to the logic/data terminal D and the complementary logic data terminal j) b Fig. 5 is a circuit diagram showing an inductive amplifying circuit 2' in the embodiment of the present invention, wherein the PM0S transistor MP1 and the NM0S transistor MN1 are connected in series, and the source of the pm〇s transistor MP1 is coupled to the high voltage source VDD, NMOS. The source side of the transistor MN1 is connected to the low voltage source VSS, the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1 are both coupled to the input terminal of the inductive amplifying circuit 2, pM〇s transistor MP1 The drain and the drain of the NM0S transistor MN1 are coupled to the output of the inductive amplifying circuit 200 The drain of the NMOS transistor MN2 is coupled to the input terminal of the inductive amplifier 4 circuit 200, and the gate is coupled to the output terminal of the inductive amplifying circuit 2〇〇 and the drain of the NMOS transistor MN3 is coupled to Together, the source of the NMOS transistor MN3 is coupled to the low voltage source VSS, and the gate is coupled to the precharge signal RPC.

0702-7362TW(nl); 90P104; Rliu.ptd Page 8 1298500 V 'Invention Description (5) Fig. 6 shows a schematic diagram of each signal waveform in Fig. 2. Next, the operation procedure of the signals of the respective phases will be described: Before time 11: The precharge signal RPC is at the low level, and the PMOS transistor 151 and the PMOS transistor 152 in the memory arrays A0 to A7 are turned on, for all the read bits. The line RBL0 to RBL7 are charged to a high level. At the same time, the PM0S transistor 150 is also turned on, charging the read data line RDAT to a high level. The precharge signal Rpc is at a low level, and the transistor 105 and the inductive amplifying circuit 2〇〇*NM0S transistor MN3 are both turned off. The multiplexer 110 selects the memory array A0' before the read word lines RWL〇 to RWL7 are turned on. That is, before time t1, the read bit line RBL has been selectively coupled to the read data line RDAT. At time 11: The read word line RWL0 rises to a high level and is selected to the memory unit (3), assuming that the stored data of the memory unit C0 is 〇. The precharge signal Rpc rises to a high level. The PMOS transistor 150 is turned off, charging of the read data line RDAT is stopped, and the PMOS transistors 151, 152 are turned off to stop charging the read bit line RBL. Since the precharge signal is at a high level, the NM〇s transistor 1〇5 is turned on, and the NMOS transistor JJN3 in the sense amplifier 200 is turned on. The storage data of the memory unit C0 is 〇, the logical level of the node ^ is 〇, the logical position of the node DB, 1, NM〇s transistor 〇 is in the on state, and the read bit 7G line RBL0 is at the high level, NM〇 The s transistor M1 is in an on state, the NM〇s transistors M2, M1 form a discharge path, and the read bit line RBL 〇 starts to discharge 1298500. 5. Description of the invention (6) 'The read data line RDAT starts to discharge. At time 12: When the level of the read data line RDAT is lowered to the inverted level of the sense amplifier 200', the PM0S transistor MP1 starts to conduct, and the output terminal SA0OUT of the sense amplifier 200 is charged, and the NMOS transistor MN1 is gradually turned off. When the voltage at the output of the sense amplifier 200 rises to the threshold voltage of the NMOS transistor MN2, the NMOS transistor MN2 is turned on, forming a second discharge path with the NMOS transistor MN3, accelerating the reading of the data line RDAT, as shown in the figure. As shown, after the time t2, the discharge rate of the read bit line RBL0 and the read data line RDAT is significantly improved. As the read data line RDAT is discharged, the node SAOUT is gradually raised to a high level. With the NMOS transistor 105, the latch circuit 130 latches the node OUT to the 0 level. At time 13: the read word line RWL0 is lowered to the low level, and the precharge signal rpc is lowered to the low level. The PMOS transistors 151, 152 in the memory arrays A0 to A7 are turned on, and the read bit lines RBL0 to RBL7 are charged, and the PMOS transistor 150 is turned on to charge the read data line RDAT. ' The precharge signal RPC is at the low level, the NMOS transistor 105 is turned off, and the NMOS transistor MN3 in the sense amplifier 200 is turned off. Therefore, in the initial stage of precharge, the read point data line is eliminated before the RO 0 UT has been pulled back to the low level. (10) The discharge path of a τ improves the charging efficiency. At time t4:

0702-7362TW(nl); 90P104; Rliu.ptd Page 10 1298500 V. Invention Description (7) The read data line RDAT is charged to the inversion level of the sense amplifier 200, and the node SAOUT is lowered to the 0 logic level. Since the NMOS transistor 105 is turned off, the node SAOUT does not affect the data of the latch circuit 130 during the precharge process. At time 15: another read action is initiated and the precharge signal RPC rises to a high level. If the memory list = C1 stored data is 〇, repeat the above action of reading 二 2. If the data stored in memory unit C1 is! The NM〇s transistors are turned off, the read bit το line RBL 0, and the read data line RDAT are maintained at the high level. SAOUT also maintains the low level at the time of precharge. ... and as can be seen from the right, the single-ended static random access memory of the present invention shortens the reading time of high-level data, and the single number is not only the reading time of the low-level level, but also the code-inducing circuit of the induction amplifier circuit. Input, & h φ 5 & In the read cycle, the data can be closed. Prevent data level impact of pre-charge cycle has been read

Although the present invention PW is intended to limit the present invention, any of the above is not intended to be used in the context of the present invention, and the present invention may be made without departing from the scope of the present invention. The scope defined by the scope of the patent application shall prevail. 〇702-7362TW(nl);9〇Pi〇4;Riiu>ptd face

11th I 1298500

Figure 1 shows a conventional single-ended inductive amplifying circuit. 2 is a block diagram showing the structure of a static random access memory in the embodiment of the present invention. FIG. 3 is a block diagram showing the memory array A in the embodiment of the present invention. Fig. 4 is a circuit diagram showing a memory cell c in the memory array A in the embodiment of the present invention. Fig. 5 is a circuit diagram showing an inductive amplifying circuit 2 in the embodiment of the present invention. Fig. 6 is a view showing the waveforms of the respective signals in Fig. 2. [Symbol Description]

A0_7~memory array; C0-7~memory unit; 105~NM0S transistor; 110~multiplexer; 120~D type flip-flop; 130~ latch circuit; 200~inductive amplifier circuit; 150, 151,152 ~ PM0S transistor; Ml, M2, M4, M3 ~ NMOS transistor; MP PMOS transistor; MN1, MN2, MN3 ~ NMOS transistor.

0702-7362TWF(nl);90P104;R1i u.ptd 12th buy

Claims (1)

—9A5,QQ^_91132688_ VI. Patent Application Scope 1 · A static random number read bit line, versatile, with the first multiplexer coupling unit having the first end and the second suffix The bit circuit is used to describe the character circuit of the memory unit and read the character circuit circuit; the first first character circuit is connected to the second end of the J, the memory forms a pre-charged wire, and when enabled, the input end line Between the second line and the second end, to the above-mentioned single-ended input terminal, the above-mentioned acceleration switch, one end of which is coupled to one high-field electric; the vehicle is charged with the moon< and the memory, with, reading the data line, to In the above-mentioned reading data end, the above static static, each reading word voltage source is 'and the second end of the reading word 兀k unit is a path, so that the corresponding path is coupled to a high pre-charging signal The enable voltage; when the circuit is coupled to a high-voltage signal, the input terminal is coupled to a critical bit and the amplifying circuit is turned on by a modified complex memory unit, wherein the complex read bit line 'each Above Recalling the memory access memory, the packet circuit is coupled to a relative one end and coupled to the upper surface to select the high logic level, and the above-mentioned read bit line discharges the voltage source and the complex number The voltage source and the reading enable the read data to be connected to the read data f, and the precharge signal non-acceleration circuit causes the above-mentioned wheel connected to the inductive discharge check circuit to be connected to the other circuit of the switch One end, when the above pre-charged ΐΙ ΐΙ 'ΐΙ 0702-7362-TWf1 (4.2); 90pl04 ; yens.ptc 13 1 6 , when the application of the patent range electrical signal enable, the above switch is broken, ... as the above pre-charge When the signal is not enabled, the above-mentioned lock-up circuit holds the data and the output data of the large circuit. 'The above switch is turned on, and the latch is inductively placed. 2. As claimed in the patent application, the above-mentioned inductive amplifying circuit includes the first P-type MOS transistor of the static random access memory, and the output end of the circuit. The source is coupled to the J, , and ^ poles to be coupled to the input terminal of the inductive amplification inductive amplifying circuit; a voltage source, the gate is coupled to the first N-type gold oxide semi-transistor, 1 circuit The output terminal is coupled to the input terminal of the inductive amplifying circuit, and the low voltage source is closed (four) connected to the upper second N-type metal oxide semi-transistor, which is connected to the thunder Give #b日1 > Six times to the above-mentioned induction amplification:: The input " pole face is connected to the output of the above-mentioned inductive amplifier circuit; the first N-type gold-oxygen semi-transistor, its pole-coupled To the source of the second n-type MOS transistor, the source is coupled to the low voltage source, and the gate receives the precharge signal. 3. The static random access memory according to claim 1, wherein the plurality of first precharge circuits comprise: a plurality of P-type MOS transistors, the drain of which is coupled to the read bit line The source is coupled to the voltage source, and the gate receives the precharge signal. The static pre-charge memory of the eighth aspect of the invention is as follows: Patent application line: Gold-oxide semi-transistor, which is not coupled to the above-mentioned reading data W to the above-mentioned high-voltage housing source 1 pole receiving _ charging = , the description of the static random access memory ^ ^ t θ% ΝΛ1Λ/^ #/, J/ ^ ^ ^ n ^ ^ The source is coupled to the above low voltage source. ^ The second end of the memory 70, 6 · as described in the scope of the patent application, in which the above-mentioned plurality of memory cells, each machine access memory first write transistor, for N penalty ^ ^ / hidden As early as possible: to the first: bit line, the interpole receives a write letter + transistor, its drain is switched to the source first inverter, and its input is lightly connected to the first write-write The second write transistor of the crystal is a Ν type gold to a second bit line, and the terminal receives the above write: the electric 曰曰 body, which has no pole face connected to the output end of the inverter; and · 乜 ,, source The first second inverter is coupled to the input end of the first end of the inverter, and the output end is coupled to the first inverting crying device to rotate the read word circuit. The turn-in end of β and is coupled to ί page 15 〇702-7362-TlVfl(4.2); 90pl〇4; yens.ptc