TW200407909A - Single-port static random access memory cell - Google Patents

Abstract

A semiconductor memory with a sense amplifier for high-speed sensing of the signal from a memory cell. The semiconductor memory includes plural memory arrays having plural memory cells, a sense amplifier, and a latch circuit. The memory cells are precharged when a precharge signal is enabled. The sense amplifier has an additional discharge path enabled by the disabled precharge signal to speed up reading data. The latch circuit is turn off by the enabled precharged signal to hold the data.

Description

200407909 V. Description of the invention (l)-The present invention relates to high-speed static random access memory, and more particularly to single-ended high-speed inductive amplifiers in static random access memory. With the advent of various video devices, the embedded SRAM technology has become an integral part of future integrated display chips. In order to enable the embedded SRAM memory to read data at high speed, and at the same time, it can stably save data from internal operations. Most random access memory systems use a good differential mode amplifier circuit with a good common mode rejection ratio, but in a multi-processing architecture, multi-port memory is required. Considering the chip space, the opportunity for using a single-ended sense amplifier is greatly increased. The first chart is not familiar with the single-ended sense amplifier circuit. When the input signal v in is at a low voltage level, the NMOS transistor 10 is not turned on, and the NMOS transistor 12 raises the voltage at node A to a certain level. At this level, the P16 transistor P16 of the inverter 16 Both N16 and NMOS transistor N16 are turned on, so that the voltage level of node B is between Vdd and Vss. The NMOS transistor 12 forms a negative feedback, so the node A cannot be charged to Vdd. When the input signal ^ 丨 hits a high voltage level, the nmqs transistor 10 is turned on, so that the above-mentioned node A is discharged, and the voltage of the node a drops to a value lower than the threshold voltage of the inverter 16. At this time, the NMOS transistor 12 will also be turned on, so that the voltage of node A is between the threshold voltage value of vss and the inverter 16, so that the voltage of node A is limited near the threshold voltage. When the input signal Vin is at a high voltage level, the NMOS transistor N12 and the NMOS transistor N1 0 are turned on at the same time, forming a direct current path. In addition to consuming static power, the NMOS transistor N12 hinders the discharge of node a, increasing Node a pull

200407909

The time from the lower voltage level is not conducive to high-speed operation. In view of this, the present invention proposes a static random access memory: an amplifying circuit, which includes: a complex memory unit, wherein the complex circuit is coupled between the complex read bit line and a low voltage source, ♦ When the memory cell selected by a read character is “low logic”, the readout circuit is turned on so that the read bit line connected to the memory cell is discharged to a low $ position. The multiplexer is coupled to a read data line; a complex precharge circuit is coupled between a high voltage source and a complex read bit line, and $ — when the precharge signal is enabled, the complex read line and data When the line is charged, the voltage is an inductive amplifier circuit. Its input terminal is connected to the read data line. When the input terminal voltage is lower than a critical level and the pre-charge signal is not enabled, an acceleration circuit is turned on so that the input terminal is accelerated to discharge. A switch with one end coupled to the output of the inductive amplifier circuit; and a latch circuit connected to the other end of the switch. When the precharge signal is enabled, the switch is disconnected, and when the precharge signal is not enabled, Switch on, latch sense Output data of the amplifier circuit. Fig. 2 shows the structure diagram of the static random access memory (SRAM) in the embodiment of the present invention. As shown in Fig. 1, the SRAM of the present invention has a plurality of memory arrays A0 to A7. , Arranged in the form of an array, the read bit lines of which are RBL0 ~ RBL7, and the multiplexer 110 selects one of the read bit lines of the array for data reading. The output of the multiplexer 110 The terminal is coupled to a read data line RDAT, which is coupled to the inductive amplifier circuit 20 for accelerating the reading of the data of the memory unit.

200407909 V. Description of the invention (3) The memory array A0 ~ A7 can receive the precharge signal rpc, the PM0S transistor 1 50 source is coupled to a high voltage source VDD, and the drain is coupled to the read data line RDAT 'gate coupling Received a precharge signal RPC. An NM0S transistor 1 05, which is used as a switch, one end is connected to the output terminal SA0UT of the induction amplifier circuit, and its gate is coupled to the precharge signal RPC, so that one end is coupled to the latch circuit 1 30, which includes The phase inverters 11 to 31 and the inverter 1132 form a latch circuit in a positive-feedback connection manner to latch the data of the induction amplifier circuit 200. The data input terminal of the D-type flip-flop 120 is coupled to the latch circuit 130, and the logic data of the latch memory unit is synchronized by the clock signal RCLK. Fig. 3 shows the architecture of the memory array A0 in the embodiment of the present invention. Other memory arrays have the same architecture. The memory array A 〇 includes memory cells C0 to C7, and the character read signals RWL0 to RWL7 are respectively coupled to the read control terminals RWL 'C 0 to C7 of the f buy terminals RBL all connected to the read bits The source line 151 of the element line RBLO 'PMOS transistor 152 is connected to the high voltage source VDD, and the pole _ is connected to the read bit line RBL0, and the gate is coupled to the precharge signal {^ (^ 〇pM〇s transistor 152's The electrical connection state is similar to that of the PM0S transistor 15i, and its drain is lightly connected to the other end of the read bit line RBL0 to prevent the read bit line rblq from propagating the precharge delay. Figure 4 shows this The circuit diagram of the memory cell c in the memory array A0 in the embodiment of the invention. The other memory cells also have the same circuit structure. The read end is lightly connected to the read bit line RBL0, and the transistor M1 and the transistor M2 are connected in series. The crystal M1 is coupled to the read bit line RBL0, the transistor M2 is coupled to the low-voltage source VSS 'the gate of the transistor M1 is coupled to the read word line ML0, and the transistor

200407909 V. Invention description (4)-The gate of the invention is coupled to the complementary logic data terminal DB. The inverter 1135 and the inverter 1136 are connected in a positive feedback manner to form a memory unit for latching logic data. The logic data terminal D and complementary logic: The material terminal DB stores logic data of opposite polarities respectively, and the logic data terminal d The write transistor M4 is coupled to the write bit line WBL, and the complementary logic data ^ = is coupled to the complementary write bit line wblb through the transistor M3. When the write number WWL is enabled, the transistor " The transistor 0 is turned on, and the complementary logic data is stored in the data bit terminal D and the complementary logic data terminal ββ through the write bit line WBL and the complementary write bit line WBLB. FIG. 5 shows the implementation of the present invention. The circuit diagram of the inductive amplifier circuit 200 in the example 'where' PM0S transistor MP1 and NM0S transistor MN1 are connected in series, the source of the pmos transistor MP1 is coupled to a high voltage source 01), and the NMOS transistor Ba surface is connected to The low voltage source VSS, the gate of the PM0S transistor MP1 and the gate of the crystal MN1 are all coupled to the input terminal of the induction amplifier circuit 200, the drain of the pM0s transistor MP1 and the drain of the NM0S transistor MNι are all Coupled to the output of the inductive amplifier circuit 200, the drain of the NM0S transistor MN2 Connected to the input terminal of the inductive amplifier circuit 200, the gate surface is connected to the output terminal of the inductive amplifier circuit, the source is coupled to the drain of the NMOS transistor MN3, and the source of the NMOS transistor MN3 is coupled to low The voltage source Vss, the gate is coupled to the precharge signal RPC. Υ Figure 6 shows the waveform of each signal in Figure 2. Next, the operation and operation procedures of the signals in each phase are explained: Before time 11:

Precharge signal RPC is at low level, PM0S in memory arrays A0 ~ A7

0702-7362TWF (nl); 90P104; Rliu.ptd Page 8 2004007909 V. Description of the invention (5) Transistor 1 5 1. PM0S transistor 1 52 is turned on, and all read bit lines RBL0 ~ RBL7 are charged to the high position quasi. At the same time, the 'PM0S transistor 150 is also turned on, and the read data line RDAT is charged to the south level. The precharge signal rpc is at a low level, and the transistor 105 and the NM0S transistor MN3 in the induction amplifier circuit 200 are both turned off. The multiplexer 110 selects § memory array A0 before reading the word lines RWL0 to RWL7. 'That is, before time t1, the read bit line RBL0 has been selected to be coupled to the read data line RDAT.

At time 11: The read character line RWL0 is raised to a high level, and a memory cell CU is selected. It is assumed that the stored data of the S memory cell C0 is zero. The precharge signal Rpc rises to a high level. The PMOS transistor 150 is turned off, and the charging of the read data line rdat is stopped, and the PMOS transistors 151 and 152 are turned off, and the charging of the read bit line RBL0 is stopped. Because the precharge signal is at a high level, the NMOS transistor 105 is turned on, and the NMOS transistor MN3 in the sense amplifier 200 is turned on.

The data stored in the memory unit C 0 is 0, the logic level of node j) is 0, the logic level of node DB}, the NMOS transistor M2 is in the on state, the bit is read, and RBL0 is at the high level. The NM0S transistor M1 is in a conducting state, the nm0s transistors M2 and M1 form a discharge path, and the read bit line RBL0 starts to discharge. The read data line RDAT starts to discharge. At time 12: · When the level of the read data line RDAT is lowered to the inverse level of the sense amplifier 200, the PMOS transistor MP1 starts to conduct, and the rotation of the sense amplifier 200 is turned out.

200407909 V. Description of the invention (6) The terminal SA0UT is charged, and the NM0S transistor MN1 is gradually closed. When the voltage at the output of the inductive amplifier 200 rises to the critical voltage of the NMOS transistor MN2, the NMOS transistor MN2 is turned on and forms a second discharge path with the NMOS transistor MN3 to accelerate the discharge of the data line rdAT as shown in the figure. It is shown that after time t2, the discharge rate of the read bit line Rbl0 and the read data line RDAT is significantly increased. As the read data line RDAT is discharged, the node SAOUT gradually rises to a high level. With the NMOS transistor 105, the latch circuit 130 latches the node OUT at the level 0. At time 13: the read word line RWL0 is lowered to a low level, and the precharge signal RPC is lowered to a low level. The PM0S transistors 151 and 152 in the memory arrays A0 to A7 are turned on, and the read bit lines RBL0 to RBL7 are charged, and the PM0S transistor 150 is turned on to charge the read data line RDAT. '' The pre-charge signal RPC is at a low level, the NM0S transistor 105 is turned off, and the NM0S transistor MN3 in the sense amplifier 200 is turned off. Therefore, at the initial stage of pre-charging, the Lang point SA 0 UT has not been pulled back to the low level before reading The discharge path of the data line rda τ improves the charging efficiency. At time t4: the read data line RDAT is charged to the inversion level of the sense amplifier 200, and the node SA 0 U T is lowered to the logic level 0. Because the N M 0 S transistor 105 is turned off, the node SAOUT does not affect the data of the latch circuit 130 during the precharge process.

200407909 V. Description of the invention (7) At time 15: If the second reading is opened and the second reading is performed, the pre-charging signal sail is raised to a high level. The second stored data is 0 ', then the previous reading is repeated. The noisy bit JrH1 stores the figure is 1, the NMOS transistor M2 is turned off, the read bit line RBL 0, and the read data line RDAT maintain the ancient slave. SAOUT is also maintained at a low level during precharge. n〆, according to the above description, the single-ended static tracking of the present invention has the functions of high-speed reading and data saving, and it shortens the reading time of high-level data in advance, because 0 ~ is only the low-level reading. Take time, pre-input === put = add == to prevent the data level of the pre-charge cycle. Although the present invention has been disclosed as above with a preferred embodiment, U limits the present invention. Anyone skilled in this art, In the ^ ς non-use: and _ 'when you can make a few changes and ::: the scope of the protection of the Ming should be regarded as the scope of the attached patents as defined by the two claims of the present invention, page 11 0702-7362TWF (nl ); 90P104; Rliu.ptd 200407909

Hereinafter, the present invention will be described with reference to the drawings. Brief Description of the Drawings Fig. 1 shows a conventional single-ended inductive amplification. Fig. 2 shows a still picture in the embodiment of the present invention. Circuit. Architecture of the State Random Access Memory The second embodiment is a structural diagram of the memory array A0 in the embodiment of the present invention. The circuit diagram of the present invention only shows the memory cell C 0 in the memory array A 0 in the example. FIG. 5 shows a circuit diagram of an induction amplifier circuit 200 in the embodiment of the present invention. FIG. 6 is a schematic diagram of each signal waveform in FIG. 2. [Symbol description] A0-7 ~ memory array; c0-7 ~ memory unit; 105 ~ NM0S transistor; 110 ~ multiplexer; 120 ~ D type flip-flop; 130 ~ latch circuit; 200 ~ inductive amplification Circuit; 150, 151, 152 ~? 1 ^ 03 transistor; ^ 11, ^ 12, 1 ^ 4, M3 ~ NMOS transistor; MP and PM0S transistor; MN1, MN2, MN3 ~ NMOS transistor.

0702-7362TWF (nl); 90P104; Rliu.ptd Page 12

Claims (1)

200407909 VI. Scope of patent application1. A static random access memory has a read bit line and a multiplexer. The read bit line is coupled to a memory unit through the multiplexer, and has a first end and The machine access memory includes: a plurality of read character circuits, each read word should be between a read bit line and a low voltage source, and the second end of the memory unit, when a read character word And the second read word circuit of the memory unit forms a path for corresponding electricity; the plurality of first precharge circuits are coupled between a read bit line and when a precharge signal is caused to read The bit line is charged to a high voltage; a plurality of second precharge circuits are coupled between a data line, and the line is charged to the above high voltage when a precharge signal is enabled; a single-ended inductive amplifier circuit whose input terminal Line, when the input terminal voltage is lower than a critical level and is enabled, the above-mentioned single-ended inductive amplifier circuit turns on the input terminal to accelerate the discharge; a switch, one end of which is coupled to the above-mentioned induction and multiple memory cells, a plurality of material lines, and The middle and plural numbers read the above-mentioned read data line. At each second end, the static static element circuit surface is connected to an opposite side and one end is coupled to the upper L number to select the above read to be a high logic level. When the bit line puts the South voltage source and the complex energy, the complex South voltage source and the readout are made so that the readout data is coupled to the readout data and the precharge signal is not an acceleration circuit that makes the amplifier circuit Output terminal; a latch circuit, coupled to the other end of the switch, when the precharge 0702-7362TWF (nl); 90P104; Rliu.ptd Page 13 akjkj ^ kj I yyjy VI. When the patent application scope of the electrical signal is enabled, p When the above pre-charge signal; The second description of the latching circuit holds information, Output data. The above switch is turned on, and the first random type Λ Λ A large circuit of the static random access memory described in item 1 is latched inductively. The circuit includes the output end of the circuit, the source of which is coupled to the inductive amplifier. The input end of the inductive amplifier circuit; j the above high voltage source, the gate surface is connected to the output terminal of the first N-type metal oxide circuit, the source is extremely high, and the pole surface is connected to the inductive amplification circuit described above. Input = the above low voltage source 'idle pole is coupled to the upper half of the circuit = its-pole surface is connected to the above-mentioned inductive amplifier and the surface is connected to the output terminal of the above-mentioned inductive amplifier circuit; The source / non-polar side of the transistor is connected to the second N-type metal-oxide semi-precharge letter IW to the above low voltage, and the gate receives the static random access memory as described in the above item 3. The plurality of first pre-charging circuits include a line, 1 pole = gas, oxygen semi-transistor, whose drain is coupled to the read bit ^, and connected to a voltage source, and the gate receives the pre-charge. Charging signal ^ 4 Static random access memory as stated in the first patent claim The first pre-charging circuit includes: 0702.7362TW (nl); 90P104; Rliu.ptd 200407909 on page 14 6. Scope of patent application. The same electric explosion original 'gate receives the above-mentioned pre-charge signal, and its 5 electric gardens: the item includes the static random access memory line described above, a gold-on-oxygen transistor, and its' and pole are coupled to the above read The bit-selecting ankle gate receives the above-mentioned read character signal; and the oxygen half-d type gold Λ semi-electric wide stomach is coupled to the fourth N-type gold source and is coupled to the low voltage source. The second end of Jiji Yinzao's, "its 6: HH; r second-mentioned write transistor, is N-type metal-oxide half-thunder said in # to the -bit line 'gate receiving-write number . Said body, whose wave pole surface is connected to the source electrode "connected to the first written transistor to the first = to = connected: = half two crystal Zhao, whose-pole • to the output terminal of the inverter; and ^ Write "No.", the source is coupled to the first and second inverters, and the input end and the output end of the inverter are connected to the above-mentioned first character inverter circuit. , Input terminal 'and is coupled to page 15 0702-7362TWF (nl); 90〇Pl〇4; Rliu.ptd