TWI295852B - Semiconductor structure and fabricating method thereof - Google Patents

Description

[9585] IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a doping structure and a method for fabricating the same, and a structure and a method of fabricating the same. , a kind of semiconductor junction as a source/dippole. [Prior Art] Gold-oxide semi-transistor is an extremely important link. The integrated circuit (VLSI) also has a very wide range of semiconductor memory trees. As a basic structure of the light element, all of them can read the oxygen half-electric crystal device. ί, 2:2 = Increasing the element of the gold-oxygen semi-transistor produces a strain-relieving conductor; forming an open σ, and then filling the M ^ 千 版 枓 (such as SiGe) into the opening as a source / ' "Improving electrons or holes in the channel Figure 1A to 1B are cross-sectional views showing a manufacturing process of a conventional gold oxide semi-electrode. First, referring to Fig. 1A, a substrate 1 is provided. The substrate 100 has been shaped: well 101 Then, using well-known techniques on the well region 101 = a dummy structure 102 comprising a gate dielectric layer 104 and a gate 106 sequentially formed on the substrate 1 . Next, at the gate structure 102 The side wall is shaped like a gap wall 108. Subsequently, the gate structure 102 and the spacer wall 108 are used as a mask to perform a rhyme process, and a part of the substrate 10 is removed to form an opening 11 (). Next, please refer to FIG. 1B, at the opening 110. The strained layer 112 is formed as a source/drain and the surface of the strained layer 112 is higher than the surface of the substrate 1' The upper portion is labeled 113. Thereafter, a self-aligned metal telluride layer 114 is formed on the gate structure 102 and the strained layer 112. 1295 doc/e, since the surface of the strained layer 112 is higher than the surface of the substrate 1〇〇, Therefore, the influence of the stress generated by the metal telluride layer 114 can be reduced or eliminated. Further, in order to increase the stress applied to the strained layer 112, a P-type gold-oxygen semi-transistor can be used as an example, and the opening 110 can be filled with a germanium concentration of more than 20 % niobium alloy: = increase the thickness of the alloy layer, that is, form a deeper opening. However, the thickness of the niobium alloy layer is inversely proportional to the concentration of niobium, that is, the higher the concentration of the fault, The thinner the thickness of the alloy layer is, the higher the concentration of bismuth is, the larger the lattice constant of the alloy layer will be, the more the lattice size difference between the alloy layer and the substrate is A, and it is easy to be in the alloy. The line is trapped between the layer and the substrate, which affects the efficiency of the device. In addition, when the self-aligned metal material process is performed, the crucible also enters the metal layer to reduce the quality. A The purpose of the invention is A semiconductor structure is provided which utilizes a strained layer having a lattice constant which is not a source/drain to avoid a defect in the lattice size of the strained layer and the substrate, and a defect in the junction between the strained layer and the substrate. The semiconductor structure of the present invention comprises a substrate, a first gold-type semi-electrode of a first conductivity type and a second MOS transistor of a second conductivity type. The first well region and the second type of the second-electrode type in the substrate a second conductivity type second well region, wherein the first-gold oxide semi-transistor is disposed on the second well region, and the second gold-oxygen semi-transistor is disposed on the first well region. a first pole structure and a first conductivity type first strain layer, wherein the first gate structure is configured to be 6 I295§^, oc/e on the second well region, and the second well region on both sides has the first An opening. The first strain layer is disposed in the first opening, and the difference between the lattice constant of the portion of the first strain layer adjacent to the bottom of the first opening and the lattice constant of the substrate is smaller than the lattice of the portion away from the bottom of the first opening The difference between the constant and the lattice constant of the substrate. In a preferred embodiment of the invention, the lattice constant of the first strained layer is a gradient distribution. In some embodiments, the first conductivity type is a P-type, and a lattice constant of a portion of the first strainer layer adjacent to a bottom portion of the first opening is smaller than a lattice constant of a portion distant from a bottom portion of the first opening. The material of the first strain layer is, for example, a stone alloy. In still other embodiments, the first conductivity type is N-type, and a lattice constant of a portion of the first strain layer adjacent to a bottom portion of the first opening is greater than a lattice constant of a portion away from a bottom portion of the first opening. The material of the first strain layer is, for example, carbon carbide. In an embodiment of the invention, the second MOS transistor includes a second gate structure disposed on the first well region, and a source/drain region of the second conductivity type disposed at the second gate In the first well area on both sides of the structure. The semiconductor structure may further include a germanium layer disposed on the first strain layer, and a metal dream layer disposed in the dream layer, the source/drain region, the first gate structure, and the second gate structure. on. In another embodiment, the second MOS transistor includes a second gate structure disposed on the first well region, and a source/drain region of the second conductivity type disposed in the second gate structure The doc/e of the second opening in the first well region of the side is further configured to be disposed on the first bank layer/and a metal chicken layer, and is disposed in the foregoing two ', region, and first gate structures. With the second gate structure. In the first well region, the second oxy-halide transistor includes a layer disposed on the second layer: the second strain of the second conductivity type. "The number of bases in the second doorway in the first-well area on both sides of the gate m-structure and the vapor: lattice constant two = near the fourth =: tt is _ 'the portion of the bottom of the first-strain layer格常】,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The lattice constant is greater than the lattice constant of the second Η口广刀, and the lattice constant of the second strain layer at the adjacent portion is smaller than the bottom of the second opening. The lattice constant of the second strain layer is, for example, a/knife. The semiconductor structure of this embodiment may further include a layer disposed on the strained layer, and a metallization layer disposed on the layer And the foregoing first and second gate structures. The semiconductor structure is fabricated as follows. First, a base is provided: a first well region of the first conductivity type and a first well region of the second conductivity type have been formed in the north 7 'The first idle structure is formed on the second well area, and then the first

3 second conductivity type gold oxide semi-transistors on the well region. In some embodiments, the first-conducting plastic is P-type, and the atomic diameter of the first -Iv is larger than the sub-path, and the first-thick layer is reduced to the ink layer.

A. In some embodiments, the first conductivity type is an N-type, and the _IV^ element is a carbon having a small atomic diameter and a tensile strain layer. Further, in an embodiment, the first mixed gas may further include a first doping body so that the first strained layer may be directly formed into a first conductive type film layer. First. The method for forming the gold oxide semi-transistor in the well region, for example, forms a second gate structure on the first well region, and forms a second conductivity type in the first well = on both sides of the second gate structure. Source / no pole area. In this case, the semiconductor structure coating method may further include the steps of forming a germanium layer on the first strain layer, and further forming a germanium layer on the first layer, the first gate structure, the second gate structure, and the source/drain. Yu Meng is under. First, a second gate structure is formed on the first well region, and a second opening is formed in the first well region on both sides of the structure, and a source/drain region is formed in the seed wall and the first well region below. In another embodiment, the method of forming the MOS transistor may be as follows, and then on the second gate and then on the second opening side. In this case, the method for fabricating the semiconductor j may further include forming a rhyme on the first strain layer, and further forming a layer, a source-level polar region, a first-closed-pole structure, and a second inter-metallization layer. In another embodiment, the method of forming the aforementioned gold oxide semi-electrode can be as follows. First, a second gate structure is formed on the first well region, and then a part of the base on both sides of the pole structure is removed to form a second opening, and a second gas is provided to perform the roofing process for the second opening towel. A second strained layer comprising a tree and a: iv group element is formed. Wherein, the second mixed gas comprises the foregoing gas and the third gas containing the second group 1V element, and the content of the third gas in the second mixed gas increases with time. When the first conductivity type is P type and the second conductivity type is N type, the atomic diameter of the first group IV element is equal to the atom L of the eve, and the group of the group IV is carbon having an atomic diameter smaller than the diameter of the stone atom; When the first conductivity type is and the second conductivity type is p type, the group IV element is carbon having an atomic diameter smaller than the 矽 atomic diameter, and the atomic diameter of the second ιν group element is larger than the atomic diameter of 矽. Further, the second mixed gas may further include a second doping gas so that the second strained layer can be directly formed into a film layer of the second conductivity type. In this embodiment, the method for fabricating the semiconductor structure further includes the steps of forming a germanium layer on the first and second strain layers, and forming a metallization layer on the germanium layer and the gate structure. . In the epitaxial process for forming a strained layer as a source/drain of a metal oxide semi-crystal, the ratio of the non-矽IV element source gas to the helium source gas is increased with time, so that The difference between the lattice constant of the strained layer formed at the portion near the bottom of the opening and the lattice constant of the substrate is smaller than the difference between the lattice constant of the portion away from the bottom of the opening and the lattice of the substrate often 10 I295^oc/e 'Therefore, it is avoided that the difference between the size of the grid at the bottom of the adjacent opening and the lattice size of the substrate is too large. In addition, the present invention precedes the strained layer to open/form the tantalum layer and then form the metal telluride layer on the tantalum layer, thereby preventing the special group IV elements in the intersecting layer from entering the metal impurity layer and reducing the quality. The above and other objects, features, and advantages of the present invention will become more apparent from the <RTIgt; [Embodiment] ^ In the following embodiments, the same members will be given the same reference numerals, and the semiconductor structures in the respective embodiments will be described in conjunction with the manufacturing method thereof. Fig. 2 is a schematic cross-sectional view showing a semiconductor structure in accordance with an embodiment of the present invention. The semiconductor structure includes a substrate 2, a first conductivity type MOS transistor 202, a second conductivity type MOS transistor 2 〇 4, and an isolation junction I 2 〇 6. The substrate 200 has a well region 2〇8 of a first conductivity type and a well region 210 of a second conductivity type. The MOS transistor 202 is disposed on the well region 21, and includes a gate structure 212 and a strain layer 216 of a first conductivity type. The gate structure 212 includes a gate 212a, a gate 212a and a substrate disposed on the substrate 200. A gate dielectric layer 212b between 200, and a spacer 212c on the sidewalls of the gate 212a and the gate dielectric layer 212b. The gate structure 212 is disposed on the 210 well region and has an opening 214 in the well region 210 on both sides. The material of the gate electrode is, for example, polysilicon or metal. The material of the gate dielectric layer 212b is, for example, hafnium oxide, tantalum nitride or hafnium oxynitride, and the material of the spacer 212c is, for example, tantalum nitride. The strain layer 216 of the first conductivity type is disposed in the opening 214 to serve as a source of gold 11 Ι 295 · an oxygen half transistor 2 〇 2, and a portion of the bottom of the Fenton wide opening 2H, which is applied between the adjacent layers The difference is less than the distribution of the lattice constants far from the substrate. The difference between the H and the lattice constant is, for example, a ladder. When the electric type is P type, the strain layer 216 is a compressive strain layer, and the crystal is 200 ΓΧ 214 and smaller than the portion away from the bottom of the opening 214: - Conductive type In the case of the type, the strained layer 216 is a tensile strained layer, and the lattice constant of the portion of the bottom portion (four) is equal to the base crystal, and the crystal of the portion is away from the bottom portion of the opening 214. Hang i: In addition, the 'gold-oxygen semiconductor half-transistor includes a push-type τ region 217 of the first conductivity type and a source/no-pole extension region of the first conductivity type. The doped region 2U is disposed under and around the open region 214 as a further portion of the source/drain region of the MOS transistor 202. The source/drain extension 219 is disposed in the well 21a below the spacer 212c. The gold oxide semi-transistor 204 is disposed on the well region 208. The isolation structure 206 is located in the bottom 2GG of the county to define the active area of the element, which is, for example, a shallow trench isolation (STI) structure or other type of element isolation structure. In the present embodiment, the MOS transistor 〇4 includes a gate structure 218 and a strain layer 222 of a second conductivity type. The gate structure 218 is disposed on the well region 208 with openings 22 in the well regions 208 on either side thereof. The gate structure 218 includes a gate 218a disposed on the substrate 200, a gate dielectric layer 218b between the gate 218a and the substrate 200, and a spacer 218c on the sidewalls of the gate 2i8a and the gate dielectric layer 218b. The material of the gate electrode 218a is, for example, 12 1295 ^ doc / e polycrystal, and the material of the metal or gate dielectric layer is, for example, oxygen-cut, tantalum nitride or hafnium oxynitride, and the material of the spacer 218c is, for example, tantalum nitride. The strained layer 222 is disposed in the opening 22A as part of the source/drain region of the MOS transistor 〇4. Similarly, the strain layer a: the difference between the lattice constant of the portion adjacent to the bottom of the opening 220 and the lattice constant of the substrate 200 is less than the lattice constant of the portion of the lattice constant 盥200 from the portion of the bottom portion of the opening 220. The difference, and the lattice constant is, for example, a ladder. However, the lattice constant of the strained layer 222 changes in a tendency opposite to the strained layer 216. That is, when the first conductivity type is p-type (ie, the second conductivity type is N-type) and the strain layer 216 is a compressive strain layer, the strain layer 222 is a tensile strain layer whose lattice is adjacent to the bottom portion of the opening 220. The constant is less than or equal to the lattice constant of the substrate 2〇〇 and is greater than the lattice constant of the portion away from the bottom of the opening 22〇. When the first conductivity type is N-type (ie, the second conductivity type is p-type) and the strain layer 216 is a tensile strain layer, the strain layer 222 is a compressive strain layer whose lattice constant is greater than or equal to a portion adjacent to the bottom of the opening 220. The lattice constant of the substrate 2〇〇 is smaller than the lattice constant of the portion away from the bottom of the opening 220. In addition, the MOS semiconductor 204 further includes a doping region 223 of a second conductivity type and a source/ gt; and a polarity extension region 225 of the first conductivity type, wherein the doping region 223 is disposed under the opening region 220 and the sidewall. As another part of the source/drain region of the metal oxide semi-transistor 2〇4. Source/drain extension 225 is disposed in well region 208 below spacer 218c. In particular, in the present embodiment, when the first conductivity type is p-type and the second conductivity type is N-type, the material of the compressive strain strain layer 216 is, for example, a lattice constant larger than a pure 矽. The alloy, and the strain-strained layer 13 I295 § 52f.doc/e 222 is, for example, a carbonization second having a lattice constant smaller than that of pure stone. On the other hand, when the first conductivity type is N type and the second conductivity type is P type, the strain layer 216 = material is, for example, tantalum carbide, and the strain layer 222 is made of, for example, a stone alloy.

Furthermore, the difference between the lattice constant of the portion of the strained layer 216/222 adjacent the opening 214/220 and the lattice constant of the substrate 200 is smaller than the lattice constant of the portion away from the bottom of the opening 214/220 and the substrate 2〇〇 The difference between the lattice constants, so that the interface between the strain layer 216/222 at the bottom of the opening 214/22〇 and the substrate 200 is less likely to cause defects due to excessive difference in lattice size, thereby affecting the device performance.

In addition, the semiconductor structure of the present invention can also be provided with the corresponding conductive type germanium layers 22 and 224b on the strain layer 216, and the metal layer can be disposed on the germanium layer 22', the 224b and the idler structures 212 and 218. . The thickness of the layer 224a, 224b is, for example, between 1 〇〇A and 5 〇〇A. The material of the metal telluride layer 226 is, for example, Shi Xihua Tungsten, Shi Xihua Titanium, Shi Xi Hua Ming, Shi Xihua Mo, Shi Xihua Nickel, Shi Xi Bi Ba or Shi Xi Hua. Furthermore, it is also possible to arrange the contact window termination layer and the crucible on the substrate and the surface. Contact window side = 2 Qing, the material is Nitride. The contact window _ 止 二 &amp; 208b can be used as a stress layer for the metal oxide half crystal 2 〇 2, 2 〇 4 to provide m force, bribe-step to increase the gold-oxygen semi-electrode. The following will explain the Figure 2 An example of the fabrication process of the semiconductor structure is that the structure of the left and right halves of the structure is similar, so the process of the left half structure will be described below. 〃 Figures 3A to 3C show the production flow profile of the gold-oxygen semi-transistor 2〇2 14 1295§^.—/e, ^ first 'ming tea, 11 3A, providing the substrate 200, the substrate 200 has formed a conductive (four) Lai (tree), second guide Lai 210 and:: „f 206 ' where the isolation structure 206 defines the active area of the component. The formation method of the f曰 type well area and the second conductivity type well area 21G The substrate 2QG is subjected to a first conductivity type and a second conductivity type ionization process. The isolation structure 206 is formed by, for example, a shallow trench isolation structure process. Then, a closed pole 212a and a closed dielectric are formed on the well region 210. Floor

212b' method, for example, forming a layer of material and material on the substrate sequentially

The 1-pole material layer is then sequentially patterned in a micro-aliasing manner to form a gate material layer dielectric material layer. J ... please continue to refer to FIG. 3A, forming a first type doped region 211 in the well region 21 两侧 on both sides of the gate 212a, which is, for example, a gate 212a as a mask for the ion implantation process, and the first conductive A type of dopant is formed by implanting into the substrate. Next, a spacer 212c is formed on the sidewalls of the gate 212a and the closed dielectric layer 212b. Here, the interpole 212a, the inter-dielectric layer 212b, and the spacer 212c are collectively referred to as a gate structure 212.

Then, referring to FIG. 3B, a portion of the substrate 200 on both sides of the gate structure 212 is removed to form an opening 214, at which time the doped region 211 is partially removed to form a source/drain extension 219. The opening 214 is formed, for example, by forming a patterned photoresist layer (not shown) on the bottom 200, the patterned photoresist layer exposing the gate structure 212 and the region where the opening 214 is intended to be formed. Then, an etching process is performed with the gate structure 212 and the patterned photoresist layer as a mask to remove a portion of the substrate 200. The etching process described above may be an isotropic etching process, an anisotropic etching process, or a tilting etching process. The depth of the opening 21 &lt; 15 , doc / e is, for example, between 100A and l_A, preferably between 3〇〇a and 500. Subsequently, the image recording process is performed by using the gate structure 212 as a mask, and the dopant of the first conductivity type is implanted into the substrate 200 below the opening 214 and the sidewall to form a doping region 217. As the source of the full 'half ♦ crystal movement / the part of the non-polar zone. In particular, the upper implantation process may also be performed before the opening 214 is formed, and then a portion of the substrate 200 is removed to form the opening 214 and the doped region 217, but the opening 214 must have a smaller bead than the ion. The depth of implantation. Please continue to participate in 3C, providing a first mixed gas to perform a stupid process, forming a strained layer 216 in the opening 214, wherein the first mixed gas includes a first gas containing gas and a second gas containing a group IV element And the content of the second gas and the second gas of the crucible increases with time. The above-mentioned epi-crystals are two kings. For the selective insect crystal growth process, and the first gas is, for example, Shi Xijia = two buckle burn. In addition, the 'first-mixed gas preferably further includes the first push-type=eight&quot; to make the strained layer 216 directly formed into the first conductive type film layer, and the source/drain region of the ? portion. The first group IV element selected for the first conductive green ^' to produce a larger lattice constant to form a compressive strain 216' has an atomic diameter larger than the 矽 atomic diameter constant. When the first conductivity type is a Ν type, a strain layer 216 having a strain is formed to produce a smaller lattice ,, and the selected first group IV is carbon having an atomic diameter smaller than the 矽 atomic diameter. The method for fabricating the 202 卜 'gold oxide semi-transistor 2 〇 4 is substantially the same as the method for galvanic semi-transistor enamel coating, the difference is that the gold-oxide semi-transistor 2 〇 2 is 16 1295 ^, 00 / e first conductive And the MOS transistor 204 is of a second conductivity type, and the second gas mixture comprising the first gas and the third gas containing the second group IV element is used to form the strain layer 222. Of course, the second mixed gas may further include a second doping gas so that the strained layer 222 is directly formed as a second conductive type film layer as a part of the source/drain regions of the MOS semiconductor 204. In order to form the strain strain layer required for the PMOS and the tensile strain layer required for the NMOS, when the first conductivity type is P type and the second conductivity type is N type, the atomic diameter of the first group IV element is larger than the germanium atom diameter. The larger lattice constant is obtained, and the second group IV element is carbon having an atomic diameter smaller than the 矽 atomic diameter to obtain a smaller lattice constant. On the other hand, when the first conductivity type is N type and the second conductivity type is P type, the first group IV element is carbon having an atomic diameter smaller than the 矽 atomic diameter, and the atomic diameter of the second group IV element is larger than the 矽 atom diameter. In particular, when the first conductivity type is a P type and the second conductivity type is an N type, the second gas is, for example, decane, and the content of the second gas in the first mixed gas in the epitaxial process For example, it increases from 〇 to 40% over time, and the first doping gas is, for example, diborane. The third gas is, for example, decane or ethane, and the content of the third gas in the second mixed gas in the epitaxial process is, for example, increased from 0 to 20% with time, and the second doping gas is, for example, scalar nitrogen. . On the other hand, when the first conductivity type is N-type and the second conductivity type is P-type, the second gas is, for example, decane or ethane, and the content of the second gas in the first mixed gas in the epitaxial process is, for example, It is increased from 〇 to 20% over time, and the first doping gas is, for example, bismuth phosphide. The third gas is, for example, decane, and the content of the third gas in the second mixed gas in the epitaxial process is as described in Example 17 I295S52vf.d〇c/e and the second doping gas is, for example, ethyl boron, separately produced 5疋_ 'The above-mentioned gold-oxygen semi-transistors 202, 2G4 are not limited to the gold oxide half crystal 2, the process of making 2Q2 gold oxide semi-transistor 2Q2 is integrated with the white coating process' to simplify the process steps. Sexually after the ^, Meng oxygen semi-transistor 2 〇 2 (or 2 〇 4), you can also choose: also should be formed on layer 216 (or 222) rhyme (or black), such as

Figure =. The formation method of the second layer 224a (or 224b) is, for example, after the formation of the strain layer 216 (or 222) in the insect crystal system 1 , the supply of the second (or brother-) milk body is stopped, and the first gas is supplied. And

Miscellaneous gases, until the Shixi layer pool (or Tongna into the required thickness. After the formation of the Shihua layer 224a and 224b), the selective scale-like layering of the heart and the formation of metal structures on the gate structures 212, 218 The layer is moved as shown in Fig. 2. The method for forming the metal telluride layer 226 is, for example, a self-aligned siHdide (salidde) process. After forming the metal telluride layer 226, it is more suitable for the substrate 200. The contact window stop layer 228' is formed as shown in Fig. 2. The contact window etch stop layer 228 is formed by a chemical vapor deposition method, for example, in the above C Μ 0 S structure, except that the same salty lattice constant can be used. The first conductivity type MOS transistor 2〇2 of the inconsistent strain layer is combined with the second conductivity type MOS transistor 204, and the first conductivity type gold oxide=the transistor 202 and other structures may also be used. FIG. 4 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. In this embodiment, a first conductivity type MOS transistor is used. ^已18 I295§52f.d〇c/ej first-guided private gold oxide semi-transistor 20 4, disposed on the well region 208, including the gate structure 218 and the source region pole region 227 of the second conductivity type, wherein the source/drain region 227 is disposed in the well region 208 on both sides of the gate structure 218. The metal oxide semiconductor transistor 2〇4 further includes a source/drain extension region 225 of a second conductivity type disposed in the well region 2〇8 below the spacer 218C. Similarly, the semiconductor structure of the embodiment is also A layer of diarrhea 224 may be disposed on the strained layer 216, and a metal telluride layer 226 may be disposed on the layer 224, the gate structures 212, 218, and the source/_/polar regions 227. The thickness of the layer 224 The material of the metal telluride layer 226 is, for example, the above. Further, a contact window-termination layer 208b may be disposed above the metal lithium layer 226, and the material thereof is tantalum nitride. The formation method of 202 has been made in the previous embodiment! Tian fans, no further explanation here. In the present embodiment, the formation method of the metal oxide semi-crystal crystal, for example, is formed on the well 2〇8. The gate structure 218 further forms a source/drain region 227 of the second conductivity type in the well region 2〇8 on both sides of the gate structure 218. The method is, for example, an ion implantation method. Figure 5 is a schematic cross-sectional view of a semiconductor structure according to still another embodiment of the present invention. In the present embodiment, the f-conducting gold type is matched with the first conductive type MOS transistor 202. The oxygen semiconductor transistor 204 is also disposed on the well region 2〇8, including the gate structure 218 and the source/drain region 229 of the second conductivity type, wherein the source/no-pole region 229 is disposed under the opening 231 and The well region 2 〇 8 of the sidewall. The MOS semi-transistor 204 ′′ further includes a source-level extension region 225 of the second conductivity type disposed in the well region 2〇8 below the spacer 218c. Similarly, the semiconductor structure of the present invention may also be disposed on the strained layer 216, and disposed on the shoal layer 224, the structures 212, 218, and the source 汲t(10). The thickness of the slice 224 "the material of the cup diarrhea layer 226 is, for example, the above. Further, the contact window stop layer 228a and 208b may be disposed above the metal dream layer 226, and the cover layer of the cover layer 228a and 208b may be disposed. The thickness of the crucible is at least sufficient to fill the opening 23^' to provide sufficient stress to the channel region of the MOS transistor 2 to increase the carrier mobility. The material of the contact window side termination layers 228a and 208b is, for example, The method for forming the gold oxide semi-transistor 202 has been described in the previous embodiments, and will not be further described herein. In the present embodiment, the method of forming the gold-oxide semi-transistor 204" is, for example: A gate junction = 218 is formed on the well region gauge, and then a portion of the substrate 2 两侧 on both sides of the gate structure 218 is removed to form an opening 231. Then, it is formed in the well region 2〇8 below the opening 231 and the sidewall. a source/drain region 229 of a second conductivity type, such as ion implantation It is worth mentioning that the above-mentioned gold-oxygen semiconductor transistor 2〇4, or 2〇4, is also not limited to being fabricated separately from the gold-oxygen semiconductor transistor 202, and the gold-oxygen semiconductor transistor 202 can also be fabricated. It is integrated with the manufacturing method of MOS semi-transistor 2〇4, or 2〇4, to simplify the process steps. In particular, in another embodiment of the present invention, a gold-oxygen semi-transistor can also be used. 202 is matched with another gold-oxygen semi-transistor (not shown) having a similar structure but different conductivity types to the gold-oxygen semi-transistor 2〇2. The difference between the two is that the metal oxide semiconductor crystal 202 has the foregoing crystal. The strain layer 216 whose lattice constant is inconsistent has a lattice constant such as a gradient distribution; and the lattice constant of the strain layer in the MOS semi-electrode is constant. 20 doc/e I2958s^i^wf·f The content of the gas containing the non-stone group W element in the mixed gas for the insect crystal in the crystal forming process of the source layer which is the source electrode of the metal oxide semi-crystal is increased with the coffee, so that The difference between the lattice tilt of the formed strain layer at the portion adjacent to the bottom of the π opening and the lattice constant of the base filament Less than the difference between the lattice constant of the portion far from the bottom of σ and the lattice constant of the substrate, it is possible to avoid the difference in the size of the mesh size of the mesh, which causes the defect of the interface between the strained layer and the substrate to affect the performance of the element. The formation of the layer of the stone layer on the strain layer and the formation of the metal layer on the layer of the stone layer can prevent the above-mentioned special group IV elements from entering the metal-stone layer in the process of self-alignment to the group of stone-like compounds. The present invention has been disclosed in the above-described embodiments, and is not intended to limit the invention, and any skilled person can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1B are cross-sectional views showing a manufacturing process of a conventional gold oxide semi-electrode. 2 is a cross-sectional view showing a semiconductor structure in accordance with an embodiment of the present invention. 3A to 3C are cross-sectional views showing the manufacturing process of the gold oxide semiconductor transistor 202. Figure 4 is a cross-sectional view showing a semiconductor structure in accordance with another embodiment of the present invention. Figure 5 is a cross-sectional view showing a semiconductor structure in accordance with still another embodiment of the present invention. [Main component symbol description] 21, doc/e 100, 200: substrate 206: isolation structure 102, 212, 218: gate structure 104, 212b, 218b: gate dielectric layer 106, 212a, 218a: gate 108, 212c 218c: spacers 110, 214, 220, 231: openings 114, 226: metal telluride layers 202, 204, 204', 204": MOS semi-transistor 1 (U, 208, 210: well 211, 217 223: doped regions 112, 216, 222: strained layers 219, 225: source/drain extensions 224a, 224b: germanium layers 227, 229: source/drain regions 228a, 228b: etch stop layer 22

Claims (1)

I2958^ iwf.doc/e X. Patent application scope: 1. A semiconductor structure comprising: an electric type: a first-conducting type-first well region and a second conducting region-first-gold oxide semi-transistor The first well is disposed on the second well, and includes: a first opening in the second well region; and the first opening in the well region; and a first strained layer disposed in the first opening, wherein the difference between the crystal-opening and the bottom lattice constant of the portion adjacent to the bottom of the first opening is smaller than the distance between the first strained layer and the first strained layer The difference is::: the lattice constant of the sub-base and the lattice constant region of the substrate, the di-nano-oxygen semiconductor, which is disposed in the semiconductor structure described in the first item of the first well patent range, Among them, the continuous lattice-distribution of the lattice constant of the k layer. 4. The first conductivity type of the sea is 4. If the scope of the patent application is the third item, the material of the strain layer includes the stone alloy. The semiconductor structure of claim 1, wherein the first conductivity type is N-type, and the first strain layer is A lattice constant of a portion adjacent to a bottom portion of the first opening is greater than a lattice constant of a portion thereof away from a bottom portion of the first opening. 6. The semiconductor structure of claim 5, wherein the material of the first strain layer comprises a fossilized fossil. 7. The semiconductor structure of claim 1, wherein the second MOS transistor comprises: a second gate structure disposed on the first well region; and a second conductivity type A source/drain region is disposed in the first well region on both sides of the second gate structure. 8. The semiconductor structure of claim 7, further comprising: a germanium layer disposed on the first strained layer; and a metallization layer disposed on the litmus layer, the source/none a pole region, the first gate structure and the second gate structure. 9. The semiconductor structure of claim 1, wherein the second MOS transistor comprises: • a second gate structure disposed on the first well region; and a second conductivity type The source/drain regions are disposed on sidewalls and a lower side of a second opening in the first well region on both sides of the second gate structure. 10. The semiconductor structure of claim 9, further comprising: a dream layer disposed on the first strain layer; and a metal lithium layer disposed on the layer, the source/none a pole region, the first gate structure and the second gate structure. 24 I295852wf. doc/e The first-special (4) 1 job material structure, in which the brother-one gold 虱 + transistor includes · · Danbian two second gate structure, placed on the first well area; a conductivity-type second strain layer, in the second opening in the first well region on both sides. The semiconductor structure according to item 11 of the interpolar structure range, wherein the constant is different from the lattice of the base L of the base; the lattice difference of the part of the ft portion; the second of the number === the second When the conductivity type is N-type, the lattice constant of the portion away from the bottom of the 苐-open bottom is less than the lattice constant of the layer adjacent to the second gate, and the second strain is opened. bottom. The lattice constant of the portion of the crucible is larger than the lattice constant of the portion of the bottom of the opening of the dipole; and the first-two conductivity type of the Tonghaihai is. When the type is away from the bottom of the first opening; the second layer of the crystal layer is adjacent to the second opening, and the portion of the bottom portion of the second opening The lattice constant is smaller than the distance from the 13. As shown in the patent application; the lattice constant of the strain layer is a ladder + conductor structure, which includes the semiconductor structure described in the patent _ η, and includes 25 1295853⁄4 A layer of wf.doc/e is disposed on the first strain layer and the second strain layer. A metal telluride layer is disposed on the germanium layer, the first gate structure and the second gate structure. 15. A method of fabricating a semiconductor structure, comprising: providing a substrate in which a first well region of a first conductivity type and a second well region of a second conductivity type have been formed; forming a second well region a first gate structure; removing a portion of the substrate on both sides of the first gate structure to form a first opening; providing a first mixed gas for performing an epitaxial process, forming a germanium and a a first strain layer of the first group IV element, wherein the first mixed gas comprises a first gas containing one of a first gas and a second gas containing one of the first group IV elements, and the first gas in the first mixed gas The content of the two gases increases with time; and a MOS transistor of the second conductivity type is formed on the first well region. 16. The method of fabricating a semiconductor structure according to claim 15, wherein the first conductivity type is P type, and the atomic diameter of the first group IV element is larger than the atomic diameter of ruthenium. 17. The method of fabricating a semiconductor structure according to claim 15, wherein the first conductivity type is N-type and the first Group IV element is carbon. 18. The method of fabricating a semiconductor structure according to claim 15, wherein the first mixed gas further comprises a first doping gas such that the first strained layer is directly formed as a first conductive type film layer. The method for fabricating a semiconductor structure according to claim 18, wherein the method for forming the MOS transistor comprises: forming a second gate structure on the first well region And forming a source/drain region of the second conductivity type in the first well region on both sides of the second gate structure. 20. The method of fabricating a semiconductor structure according to claim 19, further comprising: forming a germanium layer on the first strain layer; and the germanium layer, the first gate structure, and the second gate A metal structure is formed on the pole structure and the source/nopole region. 21. The method of fabricating a semiconductor structure according to claim 18, wherein the method of forming the MOS transistor comprises: forming a second gate structure on the first well region; Forming a second opening in the first well region on both sides of the pole structure; and forming a source/&gt; and a pole region in the second open sidewall and the lower first well region. 22. The method of fabricating a semiconductor structure according to claim 21, further comprising: forming a germanium layer on the first strain layer; and the germanium layer, the source/drain region, the first gate A metal structure is formed on the pole structure and the second gate structure. 23. The method of fabricating a semiconductor structure according to claim 18, wherein the method for forming the MOS transistor comprises: 27 1295 85 ι 2 Avf.doc/e forming a second gate on the first well region a pole structure; removing a portion of the substrate on the rain side of the second gate structure to form a second opening; and providing a second mixed gas for performing an epitaxial process, wherein the second opening comprises a defect and a second a second strained layer of the group IV element, wherein the second mixed gas comprises the first gas and a third gas containing the second group IV element, and the content of the third gas in the second mixed gas is Increasing time, wherein, when the first conductivity type is P type and the second conductivity type is N type, the atomic diameter of the first group IV element is larger than the atomic diameter of 矽, and the second group IV element is Carbon; and when the first conductivity type is N type and the second conductivity type is P type, the first group IV element is carbon, and the atomic diameter of the second group IV element is larger than the atomic diameter of ruthenium. The method of fabricating a semiconductor structure according to claim 23, wherein the second mixed gas further comprises a second doping gas such that the second strained layer is directly formed into a film layer of the second conductivity type. The method of fabricating the semiconductor structure of claim 24, further comprising: forming a germanium layer on the first strain layer and the second strain layer; and the germanium layer, the first gate A metal structure layer is formed on the pole structure and the second gate structure. 28