TWI453834B - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Description

Semiconductor device and method of manufacturing the same

The present invention relates to a semiconductor device having a MOS transistor having a LOCOS separation structure and a method of fabricating the semiconductor device.

In order to realize a high withstand voltage MOS transistor, a structure is formed in which a region (LDD region) having a high impurity concentration in contact with the drain electrode and having a lower impurity concentration than the drain region is formed. By forming the LDD region, the electric field in the vicinity of the drain region can be alleviated. Further, a method of forming a field insulating film (hereinafter referred to as "LOCOS insulating film") having a gate insulating film thickness by the LOCOS method to alleviate the electric field between the gate electrode and the drain region has been discussed (for example, refer to Patent Document 1) ). The structure having the LOCOS insulating film formed to be thicker than the gate insulating film is hereinafter referred to as "LOCOS separation structure".

Patent Document 1: Japanese Laid-Open Patent Publication No. 2010-206163

In the MOS transistor in which the LOCOS is separated, a phenomenon occurs in a region between the gate/source voltage at which the threshold voltage of the gate is lower than that at the time of design, and leakage current flows between the source region and the drain region.

It is an object of the present invention to provide a semiconductor device and a method of manufacturing a semiconductor device having a LOCOS separation structure for suppressing generation of a leakage current between a source region and a drain region.

A semiconductor device according to an aspect of the present invention includes: (a) a semiconductor substrate; (b) a first conductive type source region and a drain region, which are formed apart from each other in a portion of the upper portion of the semiconductor substrate; and (c) a gate insulating film; a region sandwiched between the source region and the drain region is disposed on the semiconductor substrate; (d) a LOCOS insulating film surrounds the channel region formed between the source region and the drain region and is continuous with the gate insulating film Arranged on the semiconductor substrate, the film thickness is thicker than the gate insulating film; and (e) the gate electrode is composed of a polycrystalline germanium film continuously in the region sandwiched between the source region and the drain region It is distributed over the LOCOS insulating film disposed on the gate insulating film and around the gate insulating film; the gate threshold voltage at the end portion of the gate electrode in the channel width direction is a gate electrode in the central region of the gate electrode The threshold voltage is high.

A method of fabricating a semiconductor device according to another aspect of the present invention, comprising: (a) a step of forming a LOCOS insulating film by a LOCOS method on a portion of a surface of the semiconductor substrate; (b) a region other than a region where the LOCOS insulating film is formed; a step of forming a gate insulating film having a thinner film thickness than the LOCOS insulating film on the surface of the semiconductor substrate in a continuous manner with the LOCOS insulating film; (c) LOCOS insulating over the gate insulating film and around the gate insulating film a step of continuously forming a gate electrode composed of a polycrystalline germanium film on the film; (d) a step of forming a first conductivity type source region and a drain region on the upper portion of the semiconductor substrate via a region in which the gate electrode is formed And (e) making the gate threshold voltage at the end portion in the channel width direction of the gate electrode higher than the gate threshold voltage in the central region of the gate electrode, from the gate insulating film and the LOCOS insulating film A step of injecting a conductive type impurity into the gate electrode on the gate insulating film at a certain distance from the central region of the gate electrode toward the gate electrode.

According to the present invention, it is possible to provide a semiconductor device and a method of manufacturing a semiconductor device having a LOCOS separation structure for suppressing generation of a leakage current between a source region and a drain region.

Next, the first and second embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar parts are given the same or similar symbols. However, the drawings are shown in a schematic manner, and it should be noted that the relationship between the thickness and the plane size, the ratio of the thicknesses of the layers, and the like are different from the actual ones. Therefore, the specific thickness or size should be judged by considering the following instructions. Moreover, the drawings also of course include portions having different dimensional relationships or ratios from each other.

In addition, the first and second embodiments shown below exemplify an apparatus or method for embodying the technical idea of the present invention. In the embodiment of the present invention, the material, shape, structure, arrangement, and the like of the components are not Limited to the following instructions. In the embodiment of the present invention, various modifications can be added within the scope of the patent application.

(First embodiment)

1 to 3 show a semiconductor device 1 according to a first embodiment of the present invention. 1 is a cross-sectional view taken along the line I-I of FIG. 2, showing a cut surface of a channel region along the gate width direction of the semiconductor device 1. 3 is a cross-sectional view taken along line III-III of FIG. 2, showing a cut surface of a central region of the gate electrode 50 along the gate length direction of the semiconductor device 1. In the plan view of Fig. 2, the gate insulating film 40 is omitted.

As shown in FIGS. 1 to 3, the semiconductor device 1 includes a semiconductor substrate 10, a first conductive type source region 20 and a drain region 30, which are formed apart from each other in a portion of the upper portion of the semiconductor substrate 10, and a gate insulating film 40. The region including the source region 20 and the drain region 30 is disposed on the semiconductor substrate 10; the LOCOS insulating film 60 is thicker than the gate insulating film 40; and the gate electrode 50 is made of the first conductive type polycrystal In the ruthenium film, the polycrystalline ruthenium film is continuously spread over the LOCOS insulating film 60 disposed on the gate insulating film 40 and around the gate insulating film 40 in a region sandwiched between the source region 20 and the drain region 30. The LOCOS insulating film 60 surrounds the channel region formed between the source region 20 and the drain region 30, and is continuously disposed on the semiconductor substrate 10 with the gate insulating film 40. Further, the first conductivity type and the second conductivity type are opposite conductivity types. That is, when the first conductivity type is an n-type, the second conductivity type is a p-type, and the semiconductor device 1 is an n-channel MOS transistor. Further, when the first conductivity type is a p-type, the second conductivity type is an n-type, and the semiconductor device 1 is a p-channel MOS transistor.

The semiconductor device 1 is a MOS transistor having a gate threshold voltage at a terminal portion in the channel width direction of the gate electrode 50, that is, a gate threshold voltage higher than a gate threshold voltage in a central region of the gate electrode 50. Further, a region other than the peripheral region is referred to as a central region of the gate electrode 50. Here, the gate threshold voltage is a voltage applied between the gate electrode 50 and the source region 20 required to turn on the semiconductor device 1. In FIGS. 1 and 2, the peripheral region S of the gate electrode 50 is surrounded by a thick line to be displayed (the same applies hereinafter). The peripheral region S includes a region of the gate electrode 50 disposed on the gate insulating film 40 from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 toward the central portion of the gate electrode 50. Further, in Fig. 2, the end portions of the LOCOS insulating film 60 under the gate electrode 50 are shown by broken lines.

As will be described later in detail in the semiconductor device 1, the concentration of the first conductivity type impurity in the peripheral region S of the gate electrode 50 is formed to be lower than the central region of the gate electrode 50.

As shown in FIGS. 1 to 3, the semiconductor device 1 is a LOCOS separation structure having a LOCOS insulating film 60. Since the LOCOS insulating film 60 is formed by the LOCOS method, a lower portion of the LOCOS insulating film 60 is buried in a portion of the upper surface of the semiconductor substrate 10.

Further, as shown in FIG. 1, both ends of the gate electrode 50 in the gate width direction are disposed on the LOCOS insulating film 60. Further, a side wall 51 is formed in contact with the side surface of the gate electrode 50.

The source region 20 of the semiconductor device 1 has a first conductivity type low concentration source region 21 formed in a region close to the gate electrode 50 and a high concentration source higher in the first conductivity type impurity concentration lower concentration source region 21. The LDS (lightly Doped Source) structure of the area 22 is connected. The drain region 30 has a first-conductivity-type low-concentration drain region 31 formed in a region close to the gate electrode 50, and is connected to the high-concentration drain region 32 having a higher first-concentration-type impurity concentration lower concentration drain region 31. LDD (lightly Doped Drain) construction.

As shown in FIG. 1 to FIG. 3, the semiconductor substrate 10 has a structure in which the first conductive type epitaxial layer 12 is grown on the second conductive type germanium substrate 11 and the second conductive type well region 13 is formed in the epitaxial layer 12. A so-called "active region" of the semiconductor device 1 is formed in a region of the well region 13 surrounded by the LOCOS insulating film 60.

When the LOCOS insulating film 60 is formed, impurities diffused in the well region 13 below the LOCOS insulating film 60 are absorbed by the ends of the LOCOS insulating film 60. Thereby, the impurity concentration of the well region 13 near the end portion of the LOCOS insulating film 60 is lowered. As a result, at the end of the LOCOS insulating film 60, the gate-source voltage (hereinafter referred to as "leakage voltage V (leak)") at a gate threshold voltage lower than the design threshold current flows to the source region. 20 and bungee area 30. The "gate threshold at design time" is a predetermined gate threshold voltage determined by a predetermined impurity concentration in the case where the impurity concentration of the well region 13 in the vicinity of the end portion of the LOCOS insulating film 60 is not lowered.

The above leakage current is generated, especially in the n-channel MOS transistor. Therefore, the case where the first conductivity type is an n-type and the second conductivity type is a p-type is exemplified below.

In the semiconductor device 1, the n-type impurity concentration in the vicinity of the boundary T between the gate insulating film 40 and the LOCOS insulating film 60, that is, in the peripheral region S of the gate electrode 50 is lower than the n-type impurity concentration in the central region of the gate electrode 50. Therefore, in the end portion of the LOCOS insulating film 60 located under the peripheral region S of the gate electrode 50, channel inversion is less likely to occur than in the central region of the gate electrode 50. That is, the gate threshold voltage rises locally in the peripheral region S of the gate electrode 50.

As described above, in the semiconductor device 1, the gate threshold voltage (hereinafter referred to as "peripheral gate threshold voltage V(th) 2") in the peripheral region S of the gate electrode 50 is larger than that in the central region of the gate electrode 50. The pole threshold voltage (hereinafter referred to as "central gate threshold voltage V(th) 1") is high. In a region other than the peripheral region S of the gate electrode 50, the gate threshold voltage is the center gate threshold voltage V(th)1. Further, the central gate threshold voltage V(th)1 is the gate threshold voltage at the time of design.

Further, the difference between the central gate threshold voltage V(th)1 and the peripheral gate threshold voltage V(th)2 is preferably set to the n-type impurity concentration of the peripheral region S of the gate electrode 50 and the gate electrode 50. The difference in the n-type impurity concentration in the central region is equal to or greater than the difference between the gate threshold voltage and the leakage voltage V (leak) at the time of design.

Therefore, in the semiconductor device 1, the gate/source voltage at which the threshold voltage of the gate is lower than that of the design is not generated between the source region 20 and the drain region 30 at the end of the LOCOS insulating film 60. Leakage current.

Further, the conductivity type of the peripheral region S of the gate electrode 50 is p-type, and the conductivity type of the region other than the peripheral region S may be n-type. In the semiconductor device 1 constructed as described above, the peripheral gate threshold voltage V(th)2 of the semiconductor device 1 can be made higher than the center gate threshold voltage V(th)1.

The characteristic A shown in FIG. 4 is a current-voltage characteristic showing the relationship between the gate-source voltage Vgs and the drain current Ids of the semiconductor device 1 of the first embodiment, and the characteristic B to the characteristic C are current-voltage characteristics of the comparative example. .

That is, the characteristic A is a n-type impurity concentration of the gate electrode 50 on the gate insulating film 40 from the boundary T of the gate insulating film 40 and the LOCOS insulating film 60 toward the central region of the gate electrode 50 over a certain distance. The current-voltage characteristics of the semiconductor device 1 having a low n-type impurity concentration in the central region of the gate electrode 50.

The characteristic B is a current-voltage characteristic of Comparative Example B in which a p-type impurity is ion-implanted into the gate electrode 50 on the LOCOS insulating film 60 and in a region up to the boundary T between the gate insulating film 40 and the LOCOS insulating film 60. That is, Comparative Example B is a semiconductor device in which the n-type impurity concentration of the gate electrode 50 on the LOCOS insulating film 60 to the boundary T is lower than the n-type impurity concentration in the central region of the gate electrode 50.

The characteristic C is a current-voltage characteristic of Comparative Example C in which the gate electrode 50 is not implanted with p-type impurity ions and the n-type impurity concentration of the gate electrode 50 is the same in all regions.

As shown in FIG. 4, compared with the characteristics B and C, the characteristic A has a small drain current Ids in a region where the gate-source voltage Vgs is low. That is, it can be seen that the occurrence of leakage current can be suppressed by making the n-type impurity concentration of the gate electrode 50 on the gate insulating film 40 in the peripheral region S lower than the n-type impurity concentration in the central region of the gate electrode 50. .

As in the case of the characteristic B, in the peripheral region S of the gate electrode 50, only the p-type impurity is implanted into the gate electrode 50 on the LOCOS insulating film 60, and the p-type impurity is not implanted into the gate electrode 50 on the gate insulating film 40. In the case of Example B, although the characteristics were somewhat improved as compared with Comparative Example C, the leakage current could not be suppressed. Therefore, it can be understood that the peripheral gate threshold cannot be achieved if the impurity concentration of the gate electrode 50 is not lowered from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 toward the central portion of the gate electrode 50 at a certain distance w. The semiconductor device 1 has a voltage V(th) 2 higher than the central gate threshold voltage V(th)1. The distance w is, for example, about 0.5 μm.

As described above, in the semiconductor device 1 according to the first embodiment of the present invention, the n-type impurity concentration in the vicinity of the end portion of the LOCOS insulating film 60, that is, in the peripheral region S of the gate electrode 50 is higher than that in the central portion of the gate electrode 50. The n-type impurity concentration is low. Therefore, the peripheral gate threshold voltage V(th)2 in the peripheral region S of the gate electrode 50 is higher than the central gate threshold voltage V(th)1 in the central region of the gate electrode 50. As a result, according to the semiconductor device 1 shown in FIG. 1, even in the MOS transistor of the LOCOS separation structure, generation of leakage current between the source region 20 and the drain region 30 can be suppressed.

In addition, although the case where the first conductivity type is the n-type and the second conductivity type is the p-type is described above, the same effect can be obtained in the case where the first conductivity type is the p-type and the second conductivity type is the n-type. That is, the gate electrode 50 composed of the p-type polycrystalline germanium film is formed in the n-type well region 13 to form the p-type source region 20 and the drain region 30, and the gate insulating film 40 and the LOCOS insulating film 60 are disposed. In the above semiconductor device 1, the p-type impurity concentration in the peripheral region S of the gate electrode 50 is made lower than the p-type impurity concentration in the central region of the gate electrode 50. Thereby, the gate threshold voltage in the peripheral region S of the gate electrode 50 can be made higher than the gate threshold voltage in the central region of the gate electrode 50. Further, in the above embodiment, in order to obtain desired characteristics, the conductivity type and impurity concentration of the gate electrode may be appropriately changed.

Hereinafter, an example of a method of manufacturing the semiconductor device 1 in which the n-type impurity concentration in the peripheral region S of the gate electrode 50 is lower than the n-type impurity concentration in the central region of the gate electrode 50 will be described with reference to FIGS. 5 to 12. The method of manufacturing the semiconductor device described below is an example, and the modified example thereof can of course be realized by various other manufacturing methods. In addition, in each of FIGS. 5 to 12, (a) is a cross-sectional view taken along line I-I of FIG. 2, and (b) is a cross-sectional view taken along line III-III.

(a) As shown in FIG. 5, a p-type well region 13 is formed in the n-type epitaxial layer 12 after epitaxial growth on the p-type germanium substrate 11. Thereby, the semiconductor substrate 10 is prepared. The well region 13 is formed by thermally injecting a p-type impurity into a predetermined position of the epitaxial layer 12 by, for example, ion implantation.

(b) As shown in FIG. 6, a LOCOS insulating film 60 is formed on one of the surfaces of the epitaxial layer 12 and the well region 13. For example, after a tantalum nitride (SiN) film is formed on the entire surface of the epitaxial layer 12 and the well region 13, the tantalum nitride film in the region where the LOCOS insulating film 60 is formed is removed by photolithography or the like. Next, the patterned LONX insulating film 60 is selectively formed by the LOCOS method using the patterned tantalum nitride film as a photomask. The film thickness of the LOCOS insulating film 60 is, for example, about 300 nm to 600 nm.

(c) After removing the tantalum nitride film on the semiconductor substrate 10, the surface of the exposed well region 13 is oxidized by a thermal oxidation method or the like to form a gate insulating film 40 having a film thickness smaller than that of the LOCOS insulating film 60. The film thickness of the gate insulating film 40 is, for example, about 40 nm to 60 nm. Thereby, as shown in FIG. 7, a gate insulating film 40 continuous with the LOCOS insulating film 60 is formed in a region other than the region where the LOCOS insulating film 60 is formed.

(d) An n-type polycrystalline ruthenium film is formed on the entire surface by a chemical vapor deposition (CVD) method or the like. The n-type polycrystalline tantalum film is patterned by photolithography or the like, and the gate electrode 50 is formed as shown in FIG. That is, the gate electrode 50 composed of the n-type polycrystalline germanium film is formed on the LOCOS insulating film 60 which is continuously spread over the gate insulating film 40 and around the gate insulating film 40. Further, after the undoped polycrystalline germanium film is formed, the gate electrode 50 may be formed by ion implantation of an n-type impurity.

(e) ion-implanting n-type impurity such as phosphorus (P) or arsenic (As) into the well region 13 using the gate electrode 50 as a mask, as shown in FIG. 9, forming a low-concentration source region 21 and a low-concentration drain Area 31. The surface impurity concentration of the low-concentration source region 21 and the low-concentration drain region 31 is, for example, about 1 × 10 ¹⁷ cm ^-3 .

(f) After the tantalum nitride film is formed over the entire surface, the tantalum nitride film is anisotropically etched by a reactive ion etching (RIE) method or the like. As a result, as shown in FIG. 10, the side wall 51 is formed in contact with the side surface of the gate electrode 50. A ruthenium oxide film or the like may be used for the side wall

(g) using the photolithography technique to pattern the photoresist film or the gate electrode 50 and the sidewall 51 as a mask, and implant an n-type impurity such as phosphorus or arsenic into a predetermined region of the well region 13, as shown in FIG. It is shown that a high concentration source region 22 and a high concentration drain region 32 are formed. The surface impurity concentration of the high-concentration source region 22 and the high-concentration drain region 32 is, for example, about 2 × 10 ¹⁹ cm ^-3 . As shown in FIG. 11, the low-concentration source region 21 is connected to the high-concentration source region 22, and the low-concentration drain region 31 is connected to the high-concentration drain region 32.

(h) After the photoresist film 90 is applied over the entire surface, as shown in FIG. 12, the photoresist film is exposed in such a manner that the gate electrode 50 is exposed above the boundary T region of the gate insulating film 40 and the LOCOS insulating film 60. 90 patterning. At this time, at the end portion in the channel width direction of the gate electrode 50, at least from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 toward the central region of the gate electrode 50, the distance W is exposed to the gate electrode 50. The photoresist film 90 is patterned. Next, the photoresist film 90 is used as a mask, and p-type impurity ions such as boron (B) are implanted into the gate electrode 50. Thereby, a p-type impurity is implanted in the peripheral region S of the gate electrode 50. The implantation amount of the p-type impurity is, for example, about 1 × 10 ¹⁶ cm ^-2 . As a result, the n-type impurity concentration in the peripheral region S of the gate electrode 50 is lower than the n-type impurity concentration in the central region of the gate electrode 50. The photoresist film 90 is removed, and the semiconductor device 1 shown in Fig. 1 is completed.

The above description is directed to the case of forming an LDS region and an LDD region. However, the semiconductor device 1 may have a structure that does not have an LDS region and an LDD region.

Further, the step of implanting the p-type impurity into the peripheral region S of the gate electrode 50 may be performed as a separate step, and may be performed simultaneously with the manufacturing steps of other semiconductor elements. For example, in the case where the p-channel MOS transistor (not shown) is formed on the semiconductor substrate 10 simultaneously with the semiconductor device 1, in the ion implantation step of forming the source region or the drain region of the p-channel MOS transistor, p The type impurity may be implanted into the peripheral region S of the gate electrode 50.

Further, by increasing the concentration of the p-type impurity implanted in the peripheral region S of the gate electrode 50, the peripheral region of the gate electrode 50 is maintained in a state where the conductivity type in the central portion of the gate electrode 50 is maintained in the n-type. The conductivity type of S may be p-type.

As described above, according to the method of manufacturing the semiconductor device 1 of the first embodiment of the present invention, the n-type impurity concentration in the peripheral region S of the gate electrode 50 can be made lower than the n-type impurity concentration in the central region of the gate electrode 50. As a result, the peripheral gate threshold voltage V(th) 2 in the vicinity of the boundary region between the gate insulating film 40 of the semiconductor device 1 and the LOCOS insulating film 60 can be set to be the center gate of the central region of the gate electrode 50. The threshold voltage V(th)1 is high. Therefore, the semiconductor device 1 of the LOCOS separation structure which suppresses the generation of the leakage current between the source region 20 and the drain region 30 can be provided.

(Second embodiment)

In the semiconductor device 1 according to the second embodiment of the present invention, as shown in FIG. 13, not only the periphery of the well region 13, but also the LOCOS insulating film 60 is formed on the low-concentration source region 21 and the low-concentration drain region 31. The semiconductor device 1 shown in Fig. 1 is different. The gate electrode 50 shown in FIG. 13 is continuously spread over the gate insulating film 40 over the LOCOS insulating film 60 formed on the low-concentration source region 21 and the low-concentration drain region 31.

Fig. 14 is a plan view showing the semiconductor device 1 shown in Fig. 13. Fig. 13 is a view showing a cut surface of the central region of the gate electrode 50 in the XIII-XIII direction of Fig. 14, that is, along the gate length direction of the semiconductor device 1. In Fig. 14, the end portion of the LOCOS insulating film 60 under the gate electrode 50 is indicated by a broken line, and the gate insulating film 40 is omitted.

As shown in FIG. 14, the high-concentration source region 22 and the high-concentration drain region 32 are surrounded by the LOCOS insulating film 60. By forming the LOCOS insulating film 60 on the low-concentration drain region 31, the effect of increasing the withstand voltage between the gate electrode 50 and the drain region 30 can be achieved.

Fig. 15 is a view showing a cut surface of the channel region in the XV-XV direction of Fig. 14, that is, along the gate width direction of the semiconductor device 1. The cross-sectional view shown in Fig. 15 shows the same configuration as the cross-sectional view shown in Fig. 1.

In the semiconductor device 1 shown in FIGS. 13 to 15, the gate electrode 50 is in the vicinity of the boundary between the gate insulating film 40 and the LOCOS insulating film 60 formed on the low-concentration source region 21 and the low-concentration drain region 31. The n-type impurity concentration of the peripheral region S is formed to be lower than the n-type impurity concentration in the central region of the gate electrode 50. Therefore, in the end portion of the LOCOS insulating film 60 under the peripheral region S of the gate electrode 50, channel inversion is less likely to occur than in the central region of the gate electrode 50. That is, the threshold voltage locally rises in the peripheral region S of the gate electrode 50.

According to the semiconductor device 1 of the second embodiment of the present invention, the gate threshold voltage V(th) 2 in the peripheral region S of the gate electrode 50 is set to be the center gate of the central region of the gate electrode 50. The threshold voltage V(th)1 is high. As a result, according to the semiconductor device 1 of the second embodiment, even in the MOS transistor of the LOCOS bias structure, the occurrence of leakage current between the source region 20 and the drain region 30 can be suppressed. Others are substantially the same as those of the first embodiment, and the description thereof will be omitted.

Fig. 16 is a view showing another example of the semiconductor device 1 of the second embodiment. The semiconductor device 1 shown in FIGS. 13 to 15 is formed on the low-concentration source region 21 and the low-concentration drain region 31 on all boundary regions of the LOCOS insulating film 60 and the gate insulating film 40, and the gate electrode The n-type impurity concentration of 50 is lower than the n-type impurity concentration in the central region. However, as shown in FIG. 16, only the end portion of the gate electrode 50 in the channel width direction is spread from the boundary T of the gate insulating film 40 and the LOCOS insulating film 60 toward the central portion of the gate electrode 50 by a distance w, the gate The n-type impurity concentration of the electrode 50 may be lower than the n-type impurity concentration in the central region.

In order to manufacture the semiconductor device 1 shown in FIGS. 13 to 15, for example, the following manufacturing method can be employed. That is, as shown in FIG. 17, the low concentration source region 21 and the low concentration drain region 31 are formed in the well region 13. The low-concentration source region 21 and the low-concentration drain region 31 are formed by ion implantation using a photoresist film formed by, for example, photolithography.

Next, as shown in FIG. 18, in the case where the LOCOS insulating film 60 is formed, the LOCOS insulating film 60 is formed on the low-concentration source region 21 and the low-concentration drain region 31.

Thereafter, as shown in FIGS. 7 to 8, a gate insulating film 40 and a gate electrode 50 are formed. Next, as illustrated in FIGS. 10 to 11, the side wall 51, the high concentration source region 22, and the high concentration drain region 32 are formed.

Further, after the entire surface of the photoresist film 91 is applied, as shown in FIG. 19, the LOCOS insulating film 60 and the gate insulating film 40 are formed on the low-concentration source region 21 and the low-concentration drain region 31. The photoresist film 91 is patterned in such a manner that the gate electrode 50 is exposed above the boundary region. At this time, at the end portion in the channel width direction of the gate electrode 50, at least from the boundary T between the gate insulating film 40 and the LOCOS insulating film 60 toward the central portion of the gate electrode 50, the distance w is exposed to the gate electrode 50. The photoresist film 91 is patterned.

Next, the photoresist film 91 is used as a mask, and p-type impurity ions such as boron (B) are implanted into the gate electrode 50. Thereby, a p-type impurity is implanted in the peripheral region S of the gate electrode 50. As a result, the n-type impurity concentration in the peripheral region S of the gate electrode 50 is lower than the n-type impurity concentration in the central region of the gate electrode 50. The photoresist film 91 is removed, and the semiconductor device 1 shown in FIGS. 13 to 15 is completed.

According to the method of manufacturing the semiconductor device 1 of the second embodiment described above, the gate insulating film 40 of the semiconductor device 1 and the LOCOS insulating film formed on the low-concentration source region 21 and the low-concentration drain region 31 can be formed. The peripheral gate threshold voltage V(th)2 near the boundary region of 60 is set to be higher than the central gate threshold voltage V(th)1 in the central region of the gate electrode 50. Therefore, the semiconductor device 1 having the LOCOS bias structure for suppressing the occurrence of leakage current between the source region 20 and the drain region 30 can be provided.

(Other embodiments)

As described above, the present invention is described in the first and second embodiments, and the description and drawings which form a part of this disclosure are not to be construed as limiting the invention. Those skilled in the art to which the present invention pertains will be apparent from the disclosure that various alternative embodiments, embodiments, and operational techniques.

For example, as the semiconductor substrate 10, a germanium substrate in which the epitaxial layer 12 and the well region 13 are not formed is used, and the source region 20 or the drain region 30 may be formed on the germanium substrate.

As described above, the present invention naturally includes various embodiments and the like not described herein. Therefore, the technical scope of the present invention is determined by the above-described description only by the specific matters of the invention of the scope of the patent application.

1. . . Semiconductor device

10. . . Semiconductor substrate

11. . .矽 substrate

12. . . Epitaxial layer

13. . . Well area

20. . . Source area

twenty one. . . Low concentration source region

twenty two. . . High concentration source region

30. . . Bungee area

31. . . Low concentration bungee region

32. . . High concentration bungee area

40. . . Gate insulating film

50. . . Gate electrode

51. . . Side wall

60. . . LOCOS insulation film

1 is a schematic cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

Fig. 2 is a schematic plan view showing a structure of a semiconductor device according to a first embodiment of the present invention.

Figure 3 is a cross-sectional view taken along line III-III of Figure 2;

Fig. 4 is a graph showing current-voltage characteristics of a semiconductor device and a comparative example according to the first embodiment of the present invention.

5 (a) and (b) are cross-sectional views (1) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

6 (a) and (b) are cross-sectional views (2) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

7 (a) and (b) are cross-sectional views (3) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

8 (a) and (b) are cross-sectional views (4) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

9 (a) and (b) are cross-sectional views (5) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

10 (a) and (b) are cross-sectional views (6) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

11 (a) and (b) are cross-sectional views (7) of a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

12 (a) and (b) are cross-sectional views (8) of the steps of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

Fig. 13 is a schematic cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

Fig. 14 is a schematic plan view showing the structure of a semiconductor device according to a second embodiment of the present invention.

Figure 15 is a cross-sectional view taken along line XV-XV of Figure 14.

Fig. 16 is a schematic plan view showing a structure of a semiconductor device according to a modification of the second embodiment of the present invention.

Fig. 17 is a cross-sectional view (1) showing a step of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Fig. 18 is a cross-sectional view (2) showing a step of a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

19 is a cross-sectional view (3) of a step for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

10. . . Semiconductor substrate

11. . .矽 substrate

12. . . Epitaxial layer

13. . . Well area

40. . . Gate insulating film

50. . . Gate electrode

51. . . Side wall

60. . . LOCOS insulation film

S. . . Surrounding area

T. . . boundary

Claims (6)

A semiconductor device comprising: a semiconductor substrate; a first conductive type source region and a drain region formed apart from each other on a portion of the upper portion of the semiconductor substrate; and a gate insulating film including the source region and the drain region a region is disposed on the semiconductor substrate; a LOCOS insulating film surrounds the channel region formed between the source region and the drain region, and is disposed on the semiconductor substrate continuously with the gate insulating film, and the film thickness is relatively The gate insulating film is thick; and the gate electrode is composed of a polycrystalline germanium film, and the polycrystalline germanium film is continuously disposed over the gate insulating film in a region sandwiched between the source region and the drain region And a LOCOS insulating film around the gate insulating film; a gate threshold voltage at a terminal portion in a channel width direction of the gate electrode is higher than a gate threshold voltage in a central region of the gate electrode; From a boundary between the gate insulating film and the LOCOS insulating film toward a central portion of the gate electrode, a conductivity type impurity concentration of the gate electrode on the gate insulating film is at the gate The concentration of the conductive type impurity in the central region of the electrode is different; from the boundary to the certain distance, the conductivity type of the gate electrode on the gate insulating film is the second conductivity type, and the central region of the gate electrode The conductivity type is the first conductivity type. The semiconductor device of claim 1, wherein the source a region in which a first conductivity type low concentration source region formed in a region close to the gate electrode and a high concentration source region in which a first conductivity type impurity concentration is higher than the low concentration source region are connected; The region is a structure in which a first conductivity type low concentration drain region formed in a region close to the gate electrode is connected to a high concentration drain region in which a first conductivity type impurity concentration is higher than the low concentration drain region. The semiconductor device according to claim 2, wherein the LOCOS insulating film is disposed on the low concentration source region and the low concentration drain region. A method of fabricating a semiconductor device comprising: forming a LOCOS insulating film by a LOCOS method on a portion of a surface of a semiconductor substrate; and thinning the film thickness in a region other than a region where the LOCOS insulating film is formed a gate insulating film is formed on the surface of the semiconductor substrate in a continuous manner with the LOCOS insulating film; the polycrystalline oxide is continuously formed on the LOCOS insulating film over the gate insulating film and around the gate insulating film a step of forming a gate electrode of the ruthenium film; forming a first conductivity type source region and a drain region on an upper portion of the semiconductor substrate via a region where the gate electrode is formed; and making the gate electrode The gate threshold voltage of the end portion in the channel width direction, that is, the peripheral region is higher than the gate threshold voltage in the central region of the gate electrode, from the boundary between the gate insulating film and the LOCOS insulating film toward the central region of the gate electrode Injecting conductive impurities into the gate between certain distances a step of insulating the gate electrode on the insulating film; and implanting the second conductivity type impurity into the gate electrode to form the peripheral region of the gate electrode into a second conductivity type. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the source region includes a step of forming a first conductivity type low concentration source region in a region close to the gate electrode, and a first conductivity a step of forming a high-concentration source region having a higher impurity concentration than the low-concentration source region and the low-concentration source region; and forming the drain region includes forming a first conductivity type in a region close to the gate electrode a step of forming a low concentration drain region and a step of forming a high concentration drain region having a first conductivity type impurity concentration higher than the low concentration drain region and the low concentration drain region. The method of manufacturing a semiconductor device according to claim 5, wherein the LOCOS insulating film is formed on the low concentration source region and the low concentration drain region.