TWI291731B - Chip carrier and chip package structure thereof - Google Patents

Abstract

A chip carrier including a flexible substrate, a wiring layer and a set of dispensing alignment marks is provided. The flexible substrate has a rectangular dispensing region having a pair of long sides and a pair of short sides. The wiring layer having multiple inner leads located inside the rectangular dispensing region and suitable for electrically connected with the chip. The set of dispensing alignment marks is located at the opposite sides of the rectangular dispensing region on the flexible substrate. The dispensing alignment marks are arranged along a reference line parallel to and between the pair of the long sides. After the chip electrically connecting with the chip carrier, the set of the dispensing alignment marks is used for the identification of the relative positions of the flexible substrate and the chip.

Description

1291731 18749twf.doc/y IX. Description of the invention: [Technical field to which the invention pertains] This description relates to a wafer carrier (c^ip carrier) and the use of this day wafer carrier. A chip package structure, and in particular, a flexible chip carrier and a chip package using the wafer carrier. [Prior Art] In the current packaging technology, the wafer is mainly supported by a wire bonding technique, a flip chip technology or a tape automated bonding (TAB) technology. Electrical connection. In these joining techniques, the automatic tape joining technology has a monthly test of electrical properties on a flexible substrate, a three-dimensional assembly of electronic components by a flexible substrate, and a thin and capable production. The advantages of small chip packages and the like, and thus chip packages manufactured by tape automated bonding technology have been widely used in electronic products such as personal computers, liquid crystal televisions, hearing aids, and memory cards. 1A through 1C are schematic flow diagrams of conventional fabrication of a chip package via tape automated bonding techniques. Referring to Figure 1A, a flexible substrate 110 is first provided, and the material of the flexible substrate 110 is polyimide. Next, a copper foil is attached on a surface η of the flexible substrate 11 (3), and the copper foil is patterned by a lithography process to form a wiring layer 12, wherein the wiring layer 120 has A plurality of inner leads 122 are then provided with a wafer 130 and a plurality of bumps 140, and the bumps 6 1291731 18749 twf.doc/y 140 are disposed on the active surface 132 of the wafer 13A. Next, One or several of the inner leads 122 serve as alignment marks between the wafer 13 and the flexible substrate 110, and each of the two bumps 140 is disposed corresponding thereto via an image recognition system. Referring to FIG. 1B, the wafer 130 is placed on a carrying platform 2〇〇, and heat is applied to the flexible substrate ιι via the thermal head 21 of the hot press. Pressure is applied to the bumps 14 to the inner leads, and the electrical connection between the inner leads 122 and the wafer 130 is completed. Referring to FIG. 1c, via a dispensing machine (dispensing t〇〇1) Configuring the package on the flexible substrate 110 and arranging the wafer 13 to form a chip package 1 0〇, wherein the encapsulant 150 is used to prevent the moisture of the external environment from penetrating into the wafer 13 and thus the electrical characteristics of the sheet 130. ~曰h曰•ΤΓί, the technology will be connected within 13Gf It is reported that 122 will be covered by the wafer 13Q. Therefore, when the encapsulant 15G is applied to the flexible substrate 110, the internal (10) m is used as the alignment mark m before the relative position of the w13G. There is a lack of proper alignment marks to identify the relative position between the flexible substrates 110. /, otherwise, 'the heat and pressure on the flexible substrate can be touched by the heat _ 210 The substrate 11Q of the two ^ ^ = 1B and Figure 1C), is the 扃 搂 达 达 达 达 达 达 达 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 要 要 要 要 要 要 要 要 要 要Contact between substrates m 7 1291731 18749twf.doc / y - the lack of proper alignment marks in the known technology, and; 1 soil 0 produced plastic deformation after hot pressing, in the process of forming the encapsulant 150, It is easy to collide with the wafer 130 at the point of the ^^, Β ΰ ΛΑ4 to cause damage to the wafer 130. a & + The degree of _a_y) is lower, and the object of the present invention is to provide a wafer carrier to avoid the problem that the wafer is bumped by the dispenser. The object is to provide a chip package in which the package colloid has good reliability. The present invention provides a wafer carrier suitable for carrying a wafer and electrically connecting the wafer carrier. The wafer carrier comprises a flexible substrate, A line is marked with = group _ alignment. The flexible substrate has a rectangular dot film ΐ ' where the rectangular dispensing zone has - long sides and - short sides. Line: disposed on a flexible substrate, wherein the circuit layer has a plurality of (four) legs located in the rectangular dispensing area, and the (four) feet are adapted to be electrically connected to the crystal. The dispensing alignment marks are disposed on the flexible substrate and are distributed on both sides of the rectangular dispensing area. The dispensing alignment marks are arranged along the reference line, and the # test line is parallel to the long side and is located between the pair of long sides.

According to the wafer carrier of the present invention, the handleable substrate has a plurality of transmission holes 'on both sides of the flexible substrate, and the directions of the transmissions are parallel to the short sides. L According to the wafer carrier of the invention, the distance between the long sides of the reference line is equal. ^ 8 1291731 18749twf.doc/y 擗广: Only the wafer carrier described in the example, this set of dispensing pairs includes the "K" mark and the "Second" mark. The first-pair = ^ is disposed on the side of the rectangular dispensing zone, and the second alignment mark is disposed on the other side of the rubber zone. Further, the shortest distance between the first-alignment mark and the rectangular dispensing area = edge may be equal to the shortest distance between the second alignment mark and the short side of the rectangle. In accordance with the wafer carrier of the present invention, the circuit layer has a trace extending from the rectangular dot to the outside of the rectangular dispensing zone and a plurality of pins outside the rectangular county. These (four) feet are connected to these external pins via these traces. In addition, rectangular dispensing zones, the inner leads, the traces, and the outer leads are in the cutting area, the drive holes are located outside the cutting zone, and the set of dispensing alignment marks can be located; Inside or outside the cutting area. A wafer carrier according to an embodiment of the invention further includes a plurality of outer leads to be bonded to the alignment mark. These outer pin-bonded registration marks are placed on a flexible substrate. The wafer carrier according to an embodiment of the invention further includes a solder layer disposed on the flexible substrate to cover a portion of the wiring layer. The set of dispensing alignment marks is not soldered. Covered by a cover layer. In accordance with an embodiment of the wafer carrier of the present invention, the set of dispensing alignment marks are not covered by the solder mask layer. The present invention provides a chip package comprising a flexible substrate, a wiring layer, a wafer, and a set of dispensing alignment marks. The flexible substrate has a rectangular dispensing zone wherein the rectangular dispensing zone has a pair of long sides to a pair of 1291731 18749 twf.doc/y short sides. The wiring layer is disposed on the flexible substrate, wherein the wiring layer has a plurality of inner pins located in the rectangular dispensing region. The wafer is disposed on the circuit layer and corresponds to the rectangular dispensing area and is electrically connected to the (four) feet. The red _ alignment mark is disposed on the flexible (10) and distributed on the side of the rectangular rubber zone. The set of dispensing alignment marks are arranged along a reference line, and the reference line fish have parallel sides and are located between the long sides. According to the chip package of the embodiment of the invention, the reference line is equidistant from any of the long sides. In accordance with the wafer carrier of the present invention embodiment, the set of dispensing alignment marks includes a first alignment mark and a second alignment mark. The first alignment mark is disposed on one side of the rectangular dispensing area. The second alignment mark is disposed on the other side of the rectangular dispensing area. Further, the shortest distance between the first alignment mark and the short side of the rectangular dispensing area may be equal to the shortest distance between the second alignment mark and the short side of the rectangular dispensing area. According to the wafer carrier of the embodiment of the present invention, the circuit layer further includes a plurality of traces extending from the rectangular dispensing region to the outside of the rectangular dispensing region and a plurality of pins outside the rectangular dispensing region. Internal pins are connected to these external pins via these traces. A wafer carrier according to an embodiment of the invention further includes a plurality of outer lead-bonding alignment marks disposed on the flexible substrate. The wafer carrier according to an embodiment of the invention further includes a solder mask layer disposed on the flexible substrate to cover a portion of the circuit layer. In accordance with an embodiment of the wafer carrier of the present invention, the set of dispensing alignment marks are not covered by the solder mask layer. The wafer carrier according to an embodiment of the invention further includes an encapsulant disposed on the flexible substrate and coated with the wafer; further, the encapsulant may further have a The opening 'exposures the back side of the wafer relative to one of the active surfaces. Since the set of dispensing alignment marks of the present invention are located on the reference line, and since the set of dispensing alignment marks are located on opposite sides of the rectangular dispensing area, the present invention presses the wafer via a hot press. After the pins in the circuit layer, the set of dispensing alignment marks are not obscured by the wafer, and the alignment function is not easily reduced due to deformation of the flexible substrate. As such, the present invention can determine the relative position of the wafer to the flexible substrate via the set of dispensing alignment marks. Therefore, when the present invention forms the encapsulant on a predetermined position on the flexible substrate via the dispenser, the dispenser does not collide with the wafer' and no gap is easily formed between the encapsulant and the wafer. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. 2 is a schematic view of a wafer carrier according to an embodiment of the present invention. Referring to FIG. 2, the wafer carrier 3A mainly includes a flexible substrate 31A, a wiring layer 320, and a set of dispensing alignment marks 33A. In this embodiment, the material of the flexible substrate 310 may be polyacetamide, glass epoxy tree, and bismuth-sodium bisulphate-bisazabenzene (bismaleimide-taiazine). 0 resin & polyester film or other flexible material. As shown in Fig. 2, the flexible substrate 310 has a rectangular dispensing area 312, wherein the rectangular point 1291731 18749twf.doc/y glue area 312 There is a pair of long sides 312a and a pair of short sides 31. In addition, the flexible substrate 310 may further have a plurality of transmission holes 314, and the transmission holes 314 are located on both sides of the flexible substrate 31〇, and These transmission holes are arranged in parallel with these short sides 312b.

The circuit layer 320 is formed by, for example, directly pressing the copper box onto the flexible substrate 310, or attaching the copper foil to the flexible substrate 310 via an adhesive layer, and then patterning the copper box to The circuit layer 32 is formed and formed. The circuit layer 320 primarily includes a plurality of inner leads 322, a plurality of traces 324, and a plurality of outer bow legs 326. The inner pins 322 are located within the rectangular dispensing zone 312. The outer lead 326 is located outside of the rectangular dispensing zone 312. These traces 324 are outwardly extending from the rectangular dispensing region 312, and one end of the traces 324 is 2, the inner pins 322 are electrically connected, and the other ends of the traces 324 are 3 盥 = some external pins 326 electrical connection. In addition, in this embodiment, a tin layer, a full solder layer or a solder layer may be formed on the inner lead 322 and the outer lead 326 by way of == to increase bumps or solder balls in the subsequent packaging process (not ^ shows the effect of electrical connection with pins 322, 326. '曰

The set of dispensing alignment marks 330 are disposed on the flexible substrate 31, and the set of dispensing marks 330 are arranged along a reference line Ref and disposed on both sides of the rectangular dispensing area 312. The reference ruler # is an imaginary line of _ bars that is parallel to the pair of long sides 312a and is located between the pair of long sides 31%. Preferably, the reference line Ref can be as shown in this embodiment, and the distance between any long side 312a of the fish is equal. In addition, in the embodiment, the pair of dispensing alignment marks 33A include a pair of position marks 332 and a second alignment mark 334, wherein the first pair of bits 12 1291731] 8749twf.doc/y, 332 and The shape of the second alignment mark 334 is a cross. The first alignment mark 332 is disposed on one side of the rectangular dispensing area 312, and the second alignment mark 334 is disposed on the other side of the rectangular dispensing area 312. In the present invention, in other embodiments, the align mark 33 〇 may have a plurality of first-to-position 332 and a second second align mark 334, and these alignments The shape of the mark can be a circular mark, a square shape, an L line or an alignment mark of other shapes.

In the above, the first alignment mark 332 and the shortest η second alignment mark 334 of the pair of short sides 312b and the shortest distance of the pair of short sides 3i2b are replaced by the alignment mark M2 and the closest second pair. The distance of the bit mark 322 short side 312b is equal to the distance between the second bit mark 334 and the short side 312b closest to the first bit mark 322. Of course, in other embodiments of the present invention, the shortest distance between the first alignment mark 3D and the pair of short sides 312b is not equal to the second alignment mark 334: the shortest side 312b distance. /,. Leader

- The jujube target can be laid out on the flexible substrate 310 - the cutting region 34G, so that the embodiment can perform the wafer carrier 3 in accordance with the contour of the cutting region 340 in the subsequent sealing process Cutting, wherein the rectangular dispensing area 312, the inner pins 322, the traces 324, the two outer pins 326, and the set of dispensing alignment marks 33 are located in the =340, the transmission holes 314 are located The cutting area 34 is outside. The present embodiment is not intended to limit the present invention. In the other aspects of the present invention, the set of dispensing alignment marks 330 may also be considered as outside the cutting area 340 depending on the design requirements. Configuration 13 1291731 18749twf.doc/y Further, the wafer carrier 300 may further include a solder mask 350, wherein the solder mask layer 350 is disposed on the flexible substrate 310 to cover a portion Circuit layer 320. It is worth noting that the set of dispensing alignment marks 330 are not covered by the solder mask layer 35. In addition, the wafer carrier 300 can also have a plurality of outer lead-bonded alignment marks 360, wherein the outer-pin bonded alignment marks 360 are disposed on the flexible substrate 310. In this embodiment, in addition to the wafer carrier 300 described above, a wafer can be electrically connected to the wafer carrier 3 to form a chip package. 3 is a schematic view of a chip package in accordance with an embodiment of the present invention. Referring to Figure 3, a wafer 400 is first provided. Then, one or a plurality of inner leads 322 (FIG. 2) are used as the alignment mark between the flexible substrate 31 and the wafer 400. The wafer 400 is disposed on the rectangular point of the flexible substrate 310. On the glue zone 312, the active surface of the wafer 400 faces the rectangular dispensing zone 312, and the contour of the active surface is the same as the outline of the rectangular dispensing zone 312. Then, heat and pressure are applied to the flexible substrate 31 via a hot pressing process, so that the wafer 400 is electrically connected to the inner leads 322 (FIG. 2) to form a wafer package body 500, wherein the wafer 4 For example, the inner leads 322 are electrically connected to each other via a plurality of bumps. The set of dispensing alignment marks 33〇 is then utilized to identify the relative position between the wafer 4〇〇 and the flexible substrate 310. The sealing gel 410 is then placed on the flexible substrate 31A via a dispenser (not shown) and disposed on the periphery of the wafer 4 to seal the wafer 4 therein. In this way, the wafer 400 can be forked to the protection of the encapsulant 4 〇 without the external environment 14 1291731 18749 twf.doc / y such as moisture or other external factors. More preferably, in the present embodiment, the encapsulant 410 has an opening 412 in which the opening 412 exposes the back side 4〇2 of the opposite active surface of the wafer 400. In this way, the wafer 4 〇〇 = operation, the heat generated can be quickly removed to the outside environment directly through the back 4 〇 2 and the hot father of the outside world. The value is noted when the wafer 4 is connected to the inner pin via a hot press program.

After the 322 is electrically connected, the outer pin is bonded to the alignment mark 36, and the relative displacement of the wafer 4 is in the direction X and the direction Y, but the set of the alignment mark 330 is only in the direction of the wafer. 4〇〇 produces less relative displacement. Therefore, the set of dispensing alignment marks on the identification wafer 400 and the flexible substrate 31 compared to other alignment marks on the flexible machine 31 (such as the outer lead-bonded alignment mark 36A). The relative position of the relative position is better. In summary, since the present invention has a set of glue alignment marks disposed on the reference line, the present invention can be used to mark the alignment marks after the wafer is electrically connected to the inner leg via a hot pressing process. Accurately view the relative position of the flexible substrate. Therefore, it is possible to accurately arrange the sealing body on a predetermined position on the flexible substrate via the spotting machine without hitting the wafer compared to the conventional technique. So 'L's hair: The chip package made by the chip carrier can produce better yield and better reliability. - Although the present invention has been disclosed in the preferred embodiments as above, the iron basin defines the present invention. Anyone skilled in the art can make some changes and refinements without departing from the scope of the invention, and therefore the present invention; 15 1291731 The scope of 18749 twf.doc/y is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1C are schematic diagrams showing a conventional process for fabricating a chip package via a tape automated bonding technique. 2 is a schematic view of a wafer carrier in accordance with an embodiment of the present invention. 3 is a schematic view of a chip package in accordance with an embodiment of the present invention. [Main Component Symbol Description] 100 : Chip Package 110 : Flexible Substrate 112 : Surface 120 : Circuit Layer 122 : Inner Lead 130 : Wafer 132 : Active Surface 140 : Bump 150 : Package Colloid 200 : Bearing Platform 210 : Thermal head 300: Wafer carrier 310: Flexible substrate 312: Rectangular dispensing area 312a: Long side 16 1291731 18749twf.doc/y 312b: Short side 314: Transmission hole 320: Line layer 322: Inner pin 324: Trace 326: Outer Pin 330: Dispensing Alignment Mark 332: First Alignment Marker _334: Second Alignment Marker 340: Cutting Area 350: Solder Mask Layer 360: Outer Pin Bonding Alignment Mark 400 : Wafer 402 : Back surface 410 : Package colloid 412 · · Opening φ 500 : Chip package

Ref : Reference line X : Direction Y : Direction 17

Claims (1)

1291731 18749twf.doc/y X. Patent Application Range: 1. A wafer carrier adapted to carry a wafer and electrically connected to the wafer. The wafer carrier comprises: a flexible substrate having a rectangular dot a rubber zone, wherein the rectangular dispensing zone has a pair of long sides and a pair of short sides; a circuit layer disposed on the flexible substrate, wherein the circuit layer has a plurality of located within the rectangular dispensing zone a pin, wherein the inner pins are adapted to be electrically connected to the chip; and a set of dispensing alignment marks disposed on the flexible substrate and distributed on both sides of the rectangular dispensing area, wherein the The set of dispensing alignment marks are arranged along a reference line that is parallel to the pair of long sides and between the pair of long sides. The wafer carrier of claim 1, wherein the flexible substrate has a plurality of transmission holes on both sides of the flexible substrate, and the arrangement direction of the transmission holes is These short sides are parallel. 3. The wafer carrier of claim 1, wherein the reference line is equidistant from any of the long sides. 4. The wafer carrier of claim 1, wherein the set of dispensing alignment marks comprises: a first alignment mark disposed on one side of the rectangular dispensing area; and a second pair A bit mark is disposed on the other side of the rectangular dispensing area. The wafer carrier of claim 4, wherein the first alignment mark has a shortest distance from a short side of the rectangular dispensing area and the second alignment mark and the rectangular dispensing area The shortest distance of the short side is equal. 18 1291731 18749twf.doc/y 6. If you apply for a patent scope! The circuit board has a plurality of traces extending from the rectangular dot win area to outside the rectangular dispensing area and (4) outside the rectangular turn area (four), the feet passing through the Traces are connected to the outer pins. The wafer carrier of claim 6, wherein the flexible substrate has a -cutting region, wherein the rectangular dispensing region, the inner leads, the traces, and the outer portions The pins are located in the cutting area: the set of dispensing alignment marks and the drive holes are located outside the ribs. 8. The wafer carrier of claim 6, wherein the flexible substrate has a -cutting region, wherein the set of dispensing alignment marks, the rectangular dispensing region, the inner leads The legs, the traces, and the outer pins are located within the cutting area, and the drive holes are located outside the cutting area. 9. If you apply for a patent scope! The wafer carrier of the present invention further includes a plurality of outer lead-bonding alignment marks disposed on the flexible substrate. 10. The wafer carrier of claim i, further comprising a solder mask layer disposed on the flexible substrate to cover a portion of the via layer. 11. The wafer carrier of claim 10, wherein the set of dispensing alignment marks are not covered by the solder mask layer. 12) a chip package comprising: - a flexible substrate having a rectangular dispensing area, wherein the rectangular dispensing region has a pair of long sides and a pair of short sides; - a wiring layer disposed on the a flexible substrate, wherein the circuit layer has a plurality of inner pins located in the rectangular dispensing region; 19 1291731 18749 twf.doc/y a wafer disposed on the circuit layer and corresponding to the rectangular dispensing region And electrically connected to the inner leads; and '^ a set of dispensing alignment marks disposed on the flexible substrate and distributed on both sides of the rectangular dispensing area, wherein the set of dispensing pairs The bit marks are arranged along a line of reference which is parallel to the pair of long sides and is located between the pair of long sides. The chip package of claim 12, wherein the reference line is equidistant from any of the long sides. The chip package of claim 13, wherein the set of dispensing pairs includes: a first alignment mark disposed on one side of the rectangular dispensing area; and a first The two-position mark is disposed on the other side of the rectangular dispensing area. The chip package of claim 14, wherein the first alignment mark has a shortest distance from a short side of the rectangular dispensing area and the second alignment mark is shorter than the rectangular dispensing area. The shortest distance of the sides is equal. The chip package of claim 12, wherein the town layer further comprises a plurality of traces extending from the rectangular dispensing zone to the outside of the rectangular dispensing zone and a plurality of locations at the rectangular point Pins outside the glue zone, the inner pins being connected to the outer pins via the traces. The chip package of claim 12, further comprising a plurality of outer lead-bonding alignment marks disposed on the flexible substrate. The chip package of claim 12, further comprising a solder mask layer disposed on the flexible substrate to cover a portion of the circuit layer. The chip package of claim 18, wherein the set of dispensing alignment marks are not covered by the solder mask layer. 20. The chip package of claim 12, further comprising an encapsulant disposed on the flexible substrate and encasing the wafer therein. 21. The chip package of claim 20, wherein the encapsulant has an opening exposing a back side of the wafer relative to one of the active surfaces. twenty one