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讀 I • 九、發明說爾 ^ 【發明所屬之技術領域】 本發明係有關於一 有複數個半導體晶片之 種半導體封裝構造 半導體封裝構造。 ，特別是有關於具 【先前技術】 隨著微小化以及高運作祙疮 ^ ^ 速度鸹求的增加，具有複數個半 導體晶片之半導體封梦禮γ +READING I • Nine, Inventions [Technical Field] The present invention relates to a semiconductor package structure having a plurality of semiconductor wafers. , especially with [previous technology] With the increase in miniaturization and high operation of acne ^ ^ speed appeal, semiconductor wafer gamma with multiple semiconductor wafers γ +
hum 亦即多晶片封裝構造）在許多 電子裝置越來越吸引人。多晶月 ^ ^ ^ 夕日日月封裝構造可藉由將處理器、 §己憶體以及邏輯晶片組合在單—封裝構造中，來使長印刷電 路板連接線路所導致的系統運作速度限制最小化。此外，多 晶片封裝構造可減少晶片間上車技 曰曰乃间運接線路之長度而降低訊號延 遲以及存取時間。 然而’在某些應用中（例如用以監測汽車輪胎壓力的胎 麼監測糸統），會為了功能性、可靠性、安全性及/或可製造 性而想要將某一晶片（例如-感測晶片）與其他積體電路晶 片隔開。胎壓監測系統一般包含一用以感測壓力的感測晶片 以及-對溫度以及系統電池電壓做出反應的專用積體電路 (ASIC)。 胎壓監測系統曾以各種不同的方式封裝。 2005/03 8422 A1揭示將胎壓監測系統之元件封装在一共同 導線架上，其中八訂0係被完全覆蓋而使其不受局部環境之 影響，而感測晶片係設於一開放凹處，該凹處係以一具有壓 力傳遞開口的蓋子封住。然而，此習知胎壓監測系統的感測 5 1287865 « · 晶片係直接承載在導線架的晶片承座上。由於該感測晶片與 晶片承座的熱膨服係數差異相當大，因此該感測晶片與晶片 承座會p通者該感測晶片所暴露的環境的溫度變化’而產生不 同的膨脹或收縮量；而這會導致該感測晶片的結構彎翹 (warpage)，致使感測晶片無法偵測到胎壓。此外，該熱膨 服係數不相配（CTE mismatch)導致的熱應力也可能使得該 感測曰曰片與晶片承座間發生層裂（deiaminati〇n)或是導致晶 片破裂。此外，此種差異亦可能在該感測晶片與晶片承座之 • 間的機械與電性連接產生不利之應力。 【發明内容】 本發明之主要目的係提供一種用於胎壓監測系統之半 導體封裝構造’其可克服或至少改善前述先前技術之問題。 根據上述以及其他目的，本發明提供一種半導體晶片封 :構造：其主要包括-導線架、-包覆於-第-封膠體内的 半導體晶片（例如—專用積體電路（asic))(該第一封 -凹處用以容置一第二半導體晶片(.例如一壓力感 d曰音^以Λ—設於該第一封膠體之該凹處上的蓋件。值 ;體：片::亥第—封膠體至少有一部份係形成在該第二半 片承座之間，使得該第二半導體晶片不是設 於接設於該第一封膠體之該部份上。由 同，因此前述設計可有::二數：般，該第二晶片大致相 層裂或是晶片彎勉甚：° °亥—晶片與晶片承座間發生 4題甚至破裂的問題。 1287865 本發明另提供-種用以製造前述半導體封裝構造的製 矛王"亥製程包3下列步驟：⑷將一第一半導體晶片接合於 導線木之Ba片承座，（b)將該第—半導體晶片電性連接至該 導線架之該些第-與第二引腳；⑷將該第—半導體晶片、 該晶片S座以及每一個該些第一與第二引聊之至少一部份 包覆於-第-封膠體之内，該第一封膠體具有一凹處暴露出 每-個該些第二引腳的内腳部的上表面，其中該第一封膠體 至^有°卩伤係形成在該晶片承座之上表面；（d)將一第二 半導體晶片設於該第一封膠體之該凹處以及該晶片承座上 表面之該第一封膠體之該部分之上；（e)將該第二半導體晶 片電性連接至該些第二引腳之内腳部；及（f)將一蓋件設於 該第一封膠體之該凹處上。 【貫施方式】 雖然本發明可表現為不同形式之實施例，但附圖所示者 及於下文中說明者係為本發明之較佳實施例，並請了解本文 • 所揭示者係考量為本發明之一範例，且並非意圖用以將本發 明限制於圖示及/或所描述之特定實施例中。 第1 -3圖所示為根據本發明一實施例之半導體封裝構 造100。第1圖所示為該半導體封裝構造100之上視圖。第 2圖所示為沿第1圖2-2線之剖視圖。第3圖所示為沿第i 圖3-3線之剖視圖。如圖所示，該半導體封裝構造ι〇〇主要 包括一導線架110、一包覆於一第一封膠體13〇内的第一半 導體晶片120(該第一封膠體130具有一凹處132用以容置 7Hum, also known as multi-chip package construction, is becoming more attractive in many electronic devices. Polycrystalline Moon ^ ^ ^ The sun and the moon package structure can minimize the system operating speed limit caused by long printed circuit board connection lines by combining the processor, § memory and logic chip in a single-package configuration. . In addition, the multi-chip package construction reduces the length of the inter-wafer technology and reduces the length of the signal and reduces the signal delay and access time. However, 'in some applications (such as tires used to monitor tire pressure in cars), one would want to have a wafer for functionality, reliability, safety, and/or manufacturability (eg, The wafer is separated from other integrated circuit wafers. The tire pressure monitoring system typically includes a sensing wafer for sensing pressure and a dedicated integrated circuit (ASIC) that reacts to temperature and system battery voltage. Tire pressure monitoring systems have been packaged in a variety of different ways. 2005/03 8422 A1 discloses that the components of the tire pressure monitoring system are packaged on a common lead frame, wherein the eight-order 0 is completely covered so as not to be affected by the local environment, and the sensing chip is disposed in an open recess. The recess is sealed by a cover having a pressure transmitting opening. However, the sensing of this conventional tire pressure monitoring system 5 1287865 « The wafer system is directly carried on the wafer holder of the lead frame. Since the difference between the thermal expansion coefficient of the sensing wafer and the wafer holder is quite large, the sensing wafer and the wafer holder may have different expansion or contraction of the temperature change of the environment exposed by the sensing wafer. This causes the structure of the sensing wafer to warpage, rendering the sensing wafer unable to detect the tire pressure. In addition, the thermal stress caused by the CTE mismatch may also cause delamination or rupture of the wafer between the sensing cymbal and the wafer holder. Moreover, such differences may also create unfavorable stresses in the mechanical and electrical connection between the sensing wafer and the wafer holder. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a semiconductor package construction for a tire pressure monitoring system that overcomes or at least ameliorates the problems of the prior art described above. In accordance with the above and other objects, the present invention provides a semiconductor wafer package: a structure comprising: a lead frame, a semiconductor wafer coated in the body of the first sealant (for example, a dedicated integrated circuit (asic)) (this a recess-shaped portion for accommodating a second semiconductor wafer (for example, a pressure sensation), a cover member disposed on the recess of the first sealant. Value: Sheet:: At least a portion of the sealing body is formed between the second half of the socket, such that the second semiconductor wafer is not disposed on the portion of the first sealing body. There may be:: two numbers: generally, the second wafer is substantially laminar or the wafer is bent: ° °H - there is a problem of 4 problems or even cracks between the wafer and the wafer holder. 1287865 The present invention further provides The following steps of manufacturing the aforementioned semiconductor package structure: (4) bonding a first semiconductor wafer to a Ba wafer holder of a wire, and (b) electrically connecting the first semiconductor wafer to the wire The first and second pins of the frame; (4) the first semiconductor The chip, the S-seat of the wafer, and at least a portion of each of the first and second chats are covered in the -first sealant, the first sealant has a recess to expose each of the plurality of An upper surface of the inner leg of the second pin, wherein the first sealant is formed on the upper surface of the wafer holder; (d) a second semiconductor wafer is disposed on the first cover The recess of the colloid and the portion of the first encapsulant of the upper surface of the wafer holder; (e) electrically connecting the second semiconductor wafer to the inner leg of the second pins; and f) a cover member is provided on the recess of the first sealant. [Comprehensive manner] Although the invention may be embodied in different forms of embodiments, the figures and the following description are The preferred embodiments of the present invention are to be understood as being illustrative of the present invention and are not intended to limit the invention to the particular embodiments illustrated and/or described. Figure 3 shows a semiconductor package structure 100 in accordance with an embodiment of the present invention. Figure 1 shows the semiconductor package. The top view of the structure 100. Fig. 2 is a cross-sectional view taken along line 2-2 of Fig. 1. Fig. 3 is a cross-sectional view taken along line 3-3 of Fig. i. As shown, the semiconductor package structure ι The first sealing body 110 includes a lead frame 110 and a first semiconductor wafer 120 covered in a first sealing body 13 (the first sealing body 130 has a recess 132 for receiving 7)