TWI283465B - Structure of flip chip package - Google Patents

Abstract

A structure of a flip chip package comprises at least a carrier, a die, a plurality of bumps, and a protective film. The carrier has a top surface and a plurality of bump pads, wherein the bump pads are located on the top surface of the carrier. The die has an active surface and a relative back surface. The die further has a plurality of die pads that are located on the active surface of the die. Besides, each of the bumps is deposed between one of the die pads and a relative one of the bump pads. Finally, the protective film is located on the back surface of the die to prevent the die from being damaged.

Description

1283465

The present invention relates to a flip chip type chip package structure, and more particularly to a flip chip type chip package structure having a protective film, wherein a protective film is disposed on the back surface of the wafer to prevent external force on the back side of the wafer. Destruction while providing better thermal conductivity to the wafer. Flip Chip Interconnect Technology (fc) is mainly used to arrange a plurality of die pads on the active surface of a die by means of an area array. A bump is formed on each of the pads, and after the wafer is flipped (f Up ), the bumps on the wafer are respectively connected to the contacts (c〇ntact - ) on the carrier, so that the wafer can be passed through The bump is electrically connected to the carrier, and is electrically connected to the external electronic device via the internal circuit of the carrier. It is worth noting that 'the flip chip bonding technology can be applied to the high pin count chip package structure, and at the same time has the advantages of reducing the chip package area and shortening the signal transmission path, so that the flip chip bonding technology has been widely used. In the field of chip packaging, the chip package structure commonly used in flip chip bonding technology is, for example, a flip chip array (F 1 ip C hip / ba 1 1

Grid Array, FC/BGA) and flip chip array (Flip chip /

Pin Grid Array, FC/PGA) and other types of chip package structures. Please refer to FIG. 1 for a schematic cross-sectional view showing the first flip-chip array type crystal winning package structure. The chip package structure 1 〇〇 mainly includes an f wafer 110, a plurality of bumps 120 and a carrier 130 and the like. Wherein, the wafer η 〇 has an active surface 112 and a corresponding back surface 114 ′ wherein the active surface 112 of the wafer 110 generally refers to the main body of the wafer

9726twf.ptd Page 5 1283465 1. Invention Description (2)~""""""""""""""""""""""""""""""""" The active surface i丨2 disposed on the wafer u is used as a medium for inputting and outputting signals of the wafer 110. In addition, the carrier 13 is, for example, a substrate having a built-in line, and has a top surface 132 and a corresponding bottom surface 134, and the carrier 130 further has a plurality of bump pads 136. Their positions correspond to the positions of these pads 1 16 respectively. In addition, 'the bumps 1 2 〇 are respectively disposed between one of the pads 1 丨 6 and one of the bumps 136 1 corresponding thereto for electrically connecting one of the fresh pads 116 and Corresponding to one of these bump pads 136. Referring to FIG. 1 again, a primer (underf i 11 ) 140 is filled in the space formed by the active surface 112 of the wafer 110 and the top surface 132 of the carrier 130 to protect the pad 11 6 and the bump 1 2 0 And the exposed portion of the bump pad 136, and at the same time buffering the difference in thermal strain between the wafer 11 〇 and the carrier 丨3 因 due to heat. In addition, the carrier 130 further has a plurality of solder ball pads (ba 1 1 pad ) 138, which are also arranged in a planar array on the bottom surface 134 of the carrier 130, and each of the balls 150 is disposed on each of the balls 130. A solder ball pad 1 3 8 on. Therefore, the solder pads 11 of the wafer 11 can be wound via the bumps 120 and electrically and mechanically connected to the bump pads 136 ′ of the carrier 13 再 and then routed downward via the internal lines of the carrier 130 (routing) ) to the solder ball pad 138 of the bottom surface 134 of the carrier 130, the last benefit

The solder ball 150 on the solder ball pad 138 is electrically and mechanically connected to the next level of electronic device, such as a printed circuit board (see also Figures 1 and 2, Figure 2) Drawing the second type of conventional

^726twf.ptd Page 6 1283465

A schematic cross-sectional view of a crystal ball 袼 array type chip package structure. First, as shown in the figure, the chip package structure 100 is a space formed by filling the primer 14 于 on the active surface 11 2 of the wafer and the top surface 丨 32 of the carrier 13 3 to protect the pad. 116. The exposed portion of the bump 120 and the bump pad 136. In addition, the underfill 14 of the chip package structure 丨00 of FIG. 1 can protect the exposed portions of the pad 116, the bump 120, and the bump pad 136, but cannot effectively protect the back surface of the wafer 11 4. The back surface j 1 4 of the wafer jj is easily damaged by the external force, because the south leaves a slight crack (not shown) on the back surface of the wafer cassette. It is worth noting that after applying the high heat to the wafer 110 in a cyclical manner, the size and depth of the crack must gradually increase.

The internal circuitry of the wafer 110 will eventually be affected by the crack and lose its original function. Next, as shown in FIG. 2, the chip package structure 1 〇 2 is formed by molding a capping compound 142 on the wafer 110 and the carrier 130, and sealing the package. 1 4 2 is filled in the space formed by the active surface 112 of the wafer 11 and the top surface 132 of the carrier 130, and is covered to the side edges and the back surface 114 of the wafer 110. Therefore, the surface of the wafer (including the back surface 1 14) can be protected by the sealant 1 42 . It is worth noting that since the material of the sealant 142 has a poor Coefficient of Therma 1 Expansion (CTE), the heat generated by the wafer 11 during operation is not easily dissipated to the outside through the sealant 142. In view of the above, an object of the present invention is to provide a flip chip type package structure for preventing the back surface of a wafer from being damaged by an external force and providing a better heat conduction effect to the wafer, thereby improving the power of the chip package structure.

9726twf.ptd Page 7 1283465 V. INSTRUCTIONS (4) Gas performance 'and can improve the service life of the chip package structure ^ Based on the above object of the present invention, the present invention proposes a kind of magnetic θ ^ ^ The flip chip type wafer sealing structure, # has at least a carrier, a wafer, a plurality of bumps, a protection film and a primer. The 14 bump pads are disposed on the top surface of the carrier. In addition, the wafer has an active surface and a corresponding-back :: and the wafer has a plurality of solder bumps disposed on the active surface of the wafer. = Ϊ 块 = block 」 is configured between these pads - and their corresponding hair two. Moreover, the protective film is disposed on the back surface of the wafer, and is mounted on the active surface of the wafer and the top surface of the carrier to have good heat resistance and heat dissipation: the material of the film is flexible, and the privacy is good. ^ A material In addition, the protective film can have a plurality of political particles, which are doped in the protective film. Also based on the present invention, the present invention further proposes a flip chip = chip package, and "冓, which has at least one carrier, one wafer, and more The embossing Ξ Γ ! 及! and a glue. In the carrier, the carrier has a top surface and a plurality of ridges, and the bump pads are disposed on the top surface of the carrier. In addition, the I f has an active surface and corresponding One of the back sides, and the wafer has a plurality of knowledge points, which are disposed on the active surface of the wafer. In addition, the bumps are respectively disposed between one of the pads and one of the bump pads corresponding thereto. The protective film is disposed on the back surface of the wafer, and the sealing material is filled in the space formed by the surface of the crystal κ 及 and the top surface of the carrier, and covers the side edge of the film and is exposed. The same protective film of the protective film away from the wafer is made of elastic material, heat resistance and dispersion.

1283465 V. Description of invention (5) Material with good heat. In addition, the protective film may further have a plurality of heat dissipating particles which are doped within the protective film. The above described objects, features, and advantages of the present invention will be apparent from the description of the preferred embodiments of the present invention. Wafer 112 Active Surface 114 Back 116 Solder Pad 120 Bump 130 Carrier 132 Top Surface 134 Bottom Surface 136 Bump Pad 138 Fresh Ball 塾 140 Primer 142 Sealing 150 Solder Ball 200, "2 0 2 : Chip Package Structure 210 Wafer 212 Active surface 214 Back 216 Pad 218 Protective film 220 Bump 230 Carrier 232 Top surface 234 Bottom surface 236 Bump pad 238 Solder ball pad 240 Primer 242 Sealing paste 250 Solder ball 300 Wafer 300 a • Wafer 301 Flip chip Wafer structure 302: active surface 304 back surface 306 : : fresh 塾 310 protective film

9726twf.ptd Page 9 1283465

320: Bumps 丨 丨 曰 & ' > 考 3 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图The chip package structure 20 is mainly a 3-chip 210, a plurality of bumps 22A, a carrier 23, and the like. The wafer 21, an active surface 212 and a corresponding back surface 214, it is noted that the active surface 2 1 2 of the wafer generally refers to the surface of the wafer 2 1 having the active component and the wafer 21 0 There are a plurality of pole mats 21 6 which are arranged in an array of planes on the active surface 212 of the wafer 21 to serve as a medium for the wafer 21 to be output. In addition, the carrier 23 is, for example, a substrate having an inner line, and the carrier 230 has a top surface 232 and a corresponding bottom surface 234, and the carrier 230 further has a plurality of bump pads 236, the positions of which are respectively Corresponding to the position of these pads 216. In addition, the protrusions & 22 分别 are respectively disposed; one of the 塾 216 and one of the bumps 236 corresponding thereto are electrically connected to one of the pads 216 and their corresponding One of these bump pads 236. Referring to FIG. 3, the primer 240 is filled in the space formed by the active surface 212 of the wafer 21 and the top surface 232 of the carrier 230 for protecting the solder pads 216, the bumps 220, and the bump pads 236. The resulting portion, and at the same time, buffers the difference in thermal strain between the wafer 210 and the carrier 230 due to heat. In addition, when the chip package structure 200 is applied to a flip chip array type Qin (FC/BGA) chip package structure, the carrier 23 〇 will have a plurality of solder ball pads 238, which are also arranged in an area array manner. The bottom surface 234 of the carrier 23 is disposed on the solder ball pad 238. because

1283465 V. Inventive Description (7) Thus, the solder pads 2 16 of the wafer 210 can be electrically and mechanically connected to the bumps 236 of the carrier 23 0 via the bumps 220, and then passed through the inside of the carrier 23 The line is wound down to the solder ball pad 238 of the bottom surface 234 of the carrier 23, and finally the solder ball 2 5 上 on the red ball pad 2 3 8 is electrically and mechanically connected to a level (next level). An electronic device, such as a printed circuit board (PCB). In addition, the chip package structure 2() can also be applied to the chip package structure of the flip chip, =^FC/PGA), or other flip chip type package structure 2 is notable; the chip package structure 2〇〇 The carrier 23 can be other than a substrate having a built-in line, and can be other types of load-bearing structures, such as a lead frame (Uad-frame) or a flexible circuit board that can carry the chip 21〇. Please refer to FIG. 3 as well. In order to prevent the back surface 214 of the wafer 21 from being damaged by external force and providing a better thermal conductivity to the wafer 2, the chip package structure 20 will have a protective film 218. It is disposed on the back surface of the wafer 2 1 2 2 1 4 . It is worth noting that the material of the protective film 2丨8 must be elastic and tough, so when the external pressure is applied to the protective film 21 8 , the protective film 218 with elasticity and toughness will be correspondingly shaped. ^, and the external pressure is dispersed on the back surface 214 of the wafer 21 to prevent the excessive pressure from the outside leaving a crack on the back surface 214 of the wafer 21. Therefore, the back surface 214 of the second: 21 将 will be less susceptible to cracks caused by external pressure, and after the heat is applied to the wafer 210 cyclically, the back surface 214 of the wafer 21 has a crack to increase the size and depth thereof. Therefore, the inner path of the chip 210 will not be affected by the crack and lose its original function, so the service life of the chip package structure 200 can be made private.

9726twf.Ptd 11 1283465 V. INSTRUCTIONS (8) Assembling = Fig. 3 of the tea ceremony of the sample, in the process of the chip package structure 200 and the subsequent 匕 = the protective film 218 is likely to need to be warmed up to the photo With::: The material of the protective film m must correspond to... After that, the pot too I 2 protective film 218 is subjected to high heat treatment, such as (oxidation) or embrittlement. This kind of agglomerate has a good thermal conduction effect and the wafer 2 1 〇, the protective film 2 1 8 # 〃, has good heat dissipation characteristics, so that the wafer 21 is operated by a heat of 1 ,, and can pass the protective glue. The film 2 18 is dissipated to the outside, and the electrical efficiency of the chip package structure 200 is improved. The same reference to Figure 3, because of the polyimine resin (p〇iy_imide, /, has good elasticity, boer, heat resistance and heat dissipation, so the choice of polyimide resin as a protective film 2 18 material In addition, in addition to selecting a material having better heat dissipation characteristics as the material of the protective film 2 18 , in the preferred embodiment of the present invention, a plurality of heat dissipating particles/Pfrticle can be doped and distributed on the protective film. Within 218, the heat dissipation characteristics of the structure of the anti-adhesive film 218 are improved, and the materials of the heat dissipating particles are, for example, cerium oxide (Si〇2), aluminum oxide (Al2〇3), copper, and other heat dissipation properties. Good material. Referring to Figures 3 and 4, FIG. 4 is a cross-sectional view showing the first flip chip type package structure of the preferred embodiment of the present invention. The chip package structure 200 and the chip package structure 02 are similar in structure, so please refer to the chip package structure 200 of FIG. 3 and related descriptions, and no further description is made herein. Different places to explain. First, the underfill 240 of the chip package structure 2 of FIG. 3 is filled with the active of the wafer 210.

Page 12 1283465 V. Description of the Invention (9) The space formed by the surface 212 and the top surface 232 of the carrier 2 30, in addition, the encapsulant 242 of the chip package structure 202 of FIG. 4 is filled on the active surface of the wafer 21 In addition to the space formed by the top surface 2 3 2 of the carrier 2 3 0 , the side edges of the wafer 210 and the protective adhesive film 218 are further covered, and the side of the protective adhesive film 218 away from the wafer 210 is exposed. In order to increase the heat dissipation area of the protective film 218, this is the largest difference between the chip package structure 200 and the chip package structure 2 〇2. In addition, the surface of the protective film 21 8 away from the wafer 21 can be used to directly contact the external heat sink (not shown), thereby improving the heat dissipation efficiency of the protective film 218 to the wafer 210. The preferred embodiment of the present invention further provides a process for processing a wafer having a protective film. Referring to FIGS. 5A to 5C, the process flow of a wafer having a protective film according to a preferred embodiment of the present invention is illustrated. Figure. First, as shown in FIG. 5A, a wafer 300 is provided having an active surface 302 and a corresponding back surface 304. The active surface 302 of the wafer 300 has a plurality of integrated circuits (Integration Circuit, 1C). (not shown), then, as shown in FIG. 5B, a protective film 31 is formed on the back surface 304 of the wafer 3, and the method of forming the protective film 310 is (fil, taping) (roller c〇) LngV; spin coating or other kinds of coating, etc. Further, as shown in Fig. 5C, the wafer 300 is cut according to the distribution area of each integrated circuit (1C). The wafer 3〇〇a is such that the protective film 310 is also cut into a plurality of portions, and is respectively left on the back surface 304 of the wafers 300a, so that the back surface 3〇4 of each wafer 3〇〇a has a protective film. 31 0.

1283465 V. DESCRIPTION OF THE INVENTION (10) Please also refer to FIGS. 5A-5B. As shown in FIG. 5C, in order to form the bump 320 on the pad 306 of the active surface 302 of the wafer 300a, as shown in FIG. 5A, The bumps 32 are pre-formed on the pads 306 of the active surface 302 of the wafer 300, or as shown in FIG. 5B, after the protective film 31 is formed on the back surface 304 of the wafer 300, the bumps 32 are formed. It is placed on the pad 3 〇6 of the active surface 3 0 2 of the wafer. In any case, the same flip chip structure 301 is finally obtained, which includes at least a wafer 3A, a protective layer 31, and a protrusion 306, wherein the protective film 310 is disposed on the back surface of the wafer 30A. 〇4, ^^7 blocks 320 are respectively disposed on the pads of the active surface 3〇2 of the wafer 3〇〇a, and the flip chip type package structure of the present invention is a protective film, wherein The protective film can be used to prevent the back of the wafer from being damaged, and the protective film can be applied to the protective film by the break of the ancient force::::? The property is used to tolerate the external heat dissipation and is used for shaking. This flip-chip film can also have a good invention. The flip chip type package structure can be used in the crystal; In order to prevent the wafer from providing a better thermal conductivity, the damage of the external force can be improved, and the electrical performance can be improved, and the package structure can be improved. Although the present invention has been used as a =\The life of the structure. God and scope"? The subject matter of the present invention is defined by the scope of the patents of the present invention, and is not limited to the scope of the invention. 9726twf.ptd Page 14 1283465 Brief Description of the Drawings FIG. 1 is a cross-sectional view showing a first type of flip chip array type chip package structure, and FIG. 2 is a second type of flip chip array. FIG. 3 is a cross-sectional view showing a first flip chip type package structure according to a preferred embodiment of the present invention; and FIG. 4 is a second view showing a preferred embodiment of the present invention. A schematic cross-sectional view of a flip chip type package structure; and 5A to 5C illustrate a process flow diagram of a wafer having a protective film according to a preferred embodiment of the present invention.

9726twf.ptd Page 15

Claims (1)

1283465 VI. Patent application scope 1 · A flip chip type chip package structure, comprising at least: a carrier having a top surface and a plurality of bump pads, wherein the bump pads are disposed on the top surface; Having an active surface and a corresponding back surface, and the wafer further has a plurality of pads, wherein the pads are disposed on the active surface; a plurality of bumps respectively disposed between one of the pads and Corresponding to one of the bump pads; and a protective film disposed on the back surface of the wafer. 2. The flip chip type package structure as described in claim 1 further comprising a primer filled in a space formed by the active surface of the wafer and the top surface of the carrier. 3. The flip chip type package structure as described in claim 1 further includes a glue which is filled in the active surface of the wafer and the space formed by the top surface of the carrier. The wafer and the side edge of the protective film are covered and the side of the protective film away from the wafer is exposed. The flip chip type package package of claim 1, wherein the carrier comprises a substrate. The flip chip type package according to the first aspect of the invention, wherein the material of the protective film comprises a material having elasticity. The structure of the flip-chip type wafer according to the first aspect of the invention, wherein the material of the protective film comprises a heat-resistant material. 7. The flip-chip type according to claim 1 of the scope of the patent application. The wafer sealing junction 'where the material of the protective film comprises a heat dissipating material 8 · The flip chip type package encapsulation as described in claim 1 9726twf.ptd Page 16 1283465 VI. Patent application scope, wherein the material of the protective film comprises polyimine resin. 9. The flip chip type wafer package structure of claim 1, wherein the protective film further comprises a plurality of heat dissipating particles doped within the protective film. The flip-chip type package structure according to claim 9, wherein the heat dissipating particles are made of a material selected from the group consisting of cerium oxide, aluminum oxide and copper. 11) A process for a wafer having a protective film, comprising the steps of: one providing a wafer, wherein the wafer has an active surface and a corresponding lean surface, and (b) forming a protective film on the wafer The back side; and (c) cutting the wafer into a plurality of wafers. μ w, as claimed in claim 11 of the invention, has a protective film, a process for forming the protective film, and the method for forming the protective film is a tape with a protective film as described in item 11 of the range of the film. Crystal method. The process, wherein the method for forming the protective film is a rolling process comprising a protective film, such as the method of claim 11, wherein the method of forming the protective film is by spin coating. 15·If the process of the piece of film described in the scope of claim 1 is the case, the material of the protective film is made of a crystal with a protective film. 1283465 17. For example, the process of the film, quality. The material of the protective film is the shoe made of the heat-dissipating material sheet, and the protective film is described in Item 11 of the patent scope of Ganming b. The wafer has a plurality of bumps, and the wafer has a plurality of bumps disposed on the surface of the crystal net to be the surface of the crystal lattice. After step (a) and before step (b), further comprising forming a plurality of bumps on the active surface of the wafer. 2〇* having a protective film as described in claim 11 The process of the wafer 'after the step (b) and before the step (c) further includes forming a plurality of bumps on the active surface of the wafer. 21. A flip chip type wafer structure comprising at least: a wafer An active surface and a corresponding back surface, and the wafer further has a plurality of pads disposed on the active surface of the wafer; a protective film disposed on the back surface of the wafer; and a plurality of bumps, respectively Disposed on the pads of the wafer. 2 2. The flip chip type wafer structure as described in claim 2, wherein the material of the protective film comprises a material having elasticity. 2 3. The flip chip type according to claim 21 structure, 9726twf.Ptd Page 18 1283465 VI. Scope of Application The material of the protective film includes heat-resistant materials. 24. The flip chip type wafer structure of claim 21, wherein the material of the protective film comprises a heat dissipating material. 2. The flip chip type wafer structure according to claim 2, wherein the material of the protective film comprises a polyimide resin. 2. The flip chip type wafer structure of claim 21, wherein the protective film further comprises a plurality of heat dissipating particles doped within the protective film. 2. The flip chip type wafer structure according to claim 26, wherein the heat dissipating particles are selected from the group consisting of a group consisting of ceria, alumina and copper. 9726twf.ptd Page 19