1281636 九、發明說明： 【發明所屬之技術領域】 本發明係有關於電腦系統，尤指具有多個用來進行緣圖運算 之整合型繪圖處理單元（integrated graphics process〇r，IGp )的主機 板與電腦系統及其相關方法。 【先前技術】1281636 IX. Description of the Invention: [Technical Field] The present invention relates to a computer system, and more particularly to a motherboard having a plurality of integrated graphics process units (IGp) for performing edge map operations. And computer systems and related methods. [Prior Art]
在現今的電腦系統當甲，用來進行高階繪圖運算的圖形處理 系統所扮演的肖色愈來愈職要。f知的_處理祕通常係以 擴充卡的形絲實現。這·充卡-般又稱為顯示卡（graphics card)係插4於—電腦系統之主機板上的擴充槽。—般而言，顯 ’、卡置有個或多個專屬的圖形處理單元（〇ρυ)，以及專 屬的繪圖記憶體。 為了喊升賴運算的品f與速度，有部分硬體製造商推出 靜ft算能力及更複雜_處理單元的顯示卡。除此之外， ===_增_記鐘的容量，峨藉由降似統匯流排 貝枓抓里的方式來改善繪圖運算的效能。 硬==_升_㈣纖㈣—蝴，係採用 的顯示卡，μ平以奴兩張或兩張以上 將每張顯示卡每祕n 休时仃處理的方式此 卞母L進仃的綠圖運算量加總，故能提升圖形處 5 1281636 ^統的效能。然而，Μ歸卡的賴需要使 * 進仃不_示卡間的資料聯繫。由於 而要4猶的喊橋射’故會造成整縣本㈣加。除此之 外’夕顯示卡的架構還需要有足夠的空間來裝設這些顯示卡。對 於些糸統整體體積相當有限的應用（例如筆記型電腦）而言， 可能無法提供裝設多張顯示卡所f的空I換言之，多； 架構有其實際應用上的限制。 、、不卡、 【發明内容】 因此本發明之目的之—在於提供具有多健合圖處理單 ^ (integrated graphics processor,IGP) , 相關的方法，以解決上述問題。 /、 在本發明之實施例中，揭露了一種主機板，其包含有.一第 —整合型_處料元，設置於社顺，該第—整 理單元具有—第—北橋電路與—第—騎處理電路；―第二^ 會圖處理單it，絡於該第__整合崎圖處理單元，讀第= 合型緣圖處理單元具有—第二北橋電路與_第二圖形處理電路了 以及一南橋電路，耦合於該第一北橋電路。 ， 本發明之實施例中另揭露一種電腦系統，其包含有：一主記 憶體模組，·-中央處理單元（CPU)，具有為合於該主記憶體模組 之-記憶體控制器南橋電路；—第—整合型_處理單元， 6 I28l636 整合型侧處理單元；以及利用該第一圖形處理電路透過該匯流 ' 排介面，與包含—第二圖形處理電路及-第二北橋電路之另一整 :合型繪圖處理單s中的該第二圖形處理電路搭配運作，以進行圖 形處理運算。 【實施方式】 明參考第1圖，其所緣示為本發明一第一實施例之一電腦系 等、统100簡化後之方塊圖。電腦系、統100包含有-主記憶體模組 (mam memory module) 110、一 中央處理單元（Cj>u) 12〇、一南 橋電路130主要整合型緣圖處理單元(master integrated graphics proceSsor，IGP，以下簡稱為主要；^^) 14〇、一輔助整合型繪圖處 理單元（以下簡稱為辅助IGp) 15〇、以及一顯示裝置16〇。請注 意，本說明書中所指稱之「整合型繪圖處理單元」係包含任何至 少整合北橋與_處理兩種魏在内的單⑼或處理$。主記憶 體模組110係設置於電腦系統1〇〇之一主機板1〇2上的至少一記 • 憶體插槽（memory slot)中。中央處理單元12〇則通常係設置於 主機板102之一中央處理單元插座（cpu s〇cket)上。在本實施例 中’南橋電路130、主要igp 140、以及辅助igp 150皆係設置於 主機板102上。如第1圖所示，辅助IGp 15〇係透過直接設置在主 機板102上的一匯流排12麵合於主要igp 140。 在電腦系統100中，主要IGP 14〇會控制顯示裝置160來進行 影像顯示運作。實作上，顯示裝置16〇可以是一 CRT螢幕、一 lcd 1281636 螢幕，或其他任何類型的影像輸出裝置。In today's computer systems, the graphics processing system used for high-level graphics operations is becoming more and more important. The knowledge of _ processing is usually achieved by the shape of the expansion card. This card is also known as the expansion card of the graphics card on the motherboard of the computer system. In general, the display has one or more dedicated graphics processing units (〇ρυ) and dedicated graphics memory. In order to spur the product and speed of the upgrade, some hardware manufacturers have introduced static ft calculation capabilities and more complex _ processing unit graphics cards. In addition, the ===_ increase _ the capacity of the clock, 峨 by improving the efficiency of the drawing operation. Hard == _ liter _ (four) fiber (four) - butterfly, is the use of the display card, μ Pingnu slave two or more will each display card per secret n 仃 的 processing this way the mother L into the green The amount of graph operations is increased, so that the performance of the graph is improved. However, it is necessary to make the data link between the card and the card. Because of the 4th of the shouting bridge shot, it will cause the entire county (four) plus. In addition, the architecture of the eve display card needs to have enough space to install these display cards. For applications where the overall size of the system is quite limited (such as a notebook computer), it may not be possible to provide an empty space for installing multiple display cards, in other words, the architecture has its practical application limitations. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for multi-integrated graphics processor (IGP) to solve the above problems. In the embodiment of the present invention, a motherboard is disclosed, which includes a first-integrated type of material, which is disposed in the social order, and the first-organizing unit has a first-north bridge circuit and a first- Ride the processing circuit; "the second ^ map processing unit it, in the first __ integrated map processing unit, the read = type edge map processing unit has - the second north bridge circuit and the _ second graphics processing circuit and A south bridge circuit coupled to the first north bridge circuit. In another embodiment of the present invention, a computer system includes: a main memory module, a central processing unit (CPU), and a memory controller south bridge corresponding to the main memory module. a circuit; a first-integrated type processing unit, 6 I28l636 an integrated side processing unit; and a first graphics processing circuit for transmitting the same through the sinking interface, and including a second graphics processing circuit and a second north bridge circuit A whole: the second graphics processing circuit in the combined drawing processing single s works in conjunction with the graphics processing operation. [Embodiment] Referring to Fig. 1, there is shown a simplified block diagram of a computer system, etc., of a first embodiment of the present invention. The computer system 100 includes a main memory module 110, a central processing unit (Cj>u) 12〇, and a south bridge circuit 130. The main integrated graphics proceSsor (IGP) , hereinafter referred to as main; ^^) 14〇, an auxiliary integrated type drawing processing unit (hereinafter referred to as auxiliary IGp) 15〇, and a display device 16〇. Please note that the “integrated graphics processing unit” referred to in this manual contains any single (9) or processing $ that integrates at least North Bridge and _ processing. The main memory module 110 is disposed in at least one memory slot of one of the motherboards 1 〇 2 of the computer system 1 . The central processing unit 12 is typically disposed on a central processing unit socket of the motherboard 102. In the present embodiment, the 'Southbridge circuit 130, the main igp 140, and the auxiliary igp 150 are disposed on the motherboard 102. As shown in Fig. 1, the auxiliary IGp 15 is fused to the main igp 140 through a bus bar 12 disposed directly on the main board 102. In computer system 100, primary IGP 14 controls display device 160 for image display operations. In practice, the display device 16 can be a CRT screen, a lcd 1281636 screen, or any other type of image output device.
第2圖所繪示為電腦系統1〇〇之主機板1〇2之一實施例簡化 後的方塊圖。如圖所示，主要IGP 140包含有一北橋電路（north bridge circuit) 242，用來橋接中央處理單元120與南橋電路130 ; 一圖形處理電路（graphicsprocessing circuit) 244，|馬合於北橋電 路242 ’用來進行圖形處理運异；以及一匯流排介面（bus interface) 246，耦合於北橋電路242與圖形處理電路244。與主要IGP 140 類似’辅助IGP 150包含有一北橋電路252北橋電路252、一圖形 處理電路254、以及一匯流排介面256。 圆形慝理電路乃4係用來辅助主要IGpi4〇中之圖形處理電路 244之圖形處理運算。例如，圖形處理電路254可用來辅助圖形處 理電路244的三維賴（3Drendering)運算。實作上，圖形處理 電路244及254可同時平行處理同一圖框的不同部分，亦可分別 處理不同賴框資料。另外’圖形處理電路244射彻任何已 知或後續開發完成的負載平衡演算法〇〇ad balandng alg〇ri細） 來平衡其本身與圖形處理電路254兩者間的繪圖運算負荷量。換 言之，主要IGP 140與辅助IGp 15〇兩者的搭配運作，可作腦 系統卿之-圖形處理系統。就一角度而言，圖形處理電路⑸ (或辅助聊150)、可視為是用來加魅要iGp 14〇之圖形處理電 路244的二維繪圖運算的額外go引擎。 9 1281636 為了能順利地結合圖形處理電路244及254兩者的繪圖處理 月b力’主要IGP 140中的圖形處理電路244係設計成具有能與圖形 處理電路254相容的指令集。在-較佳實施例中，可將圖形處理 : 構244設計成與圖形處理電路254實質上相同。此外，匯流排 12係為能溝通圖形處理電路244與254之高速匯流排。例如，匯 流排12可以是- PCI_E匯流排，而匯流排介面246與256可以是 PCI-E匯流排介面。或者，匯流排12可以是一 AGp匯流排，而匯 等流排介面246與256可用AGP匯流排介面來實現。實作上，亦可 利用其他適當的高速匯流排與匯流排介面來進行圖形處理電路 244及254之間的資料聯繫。 一在本實酬中，巾央處理單元12G包含有—記紐控制器（未 顯示），用來控制主記憶體模組110的資料存取，❿主要iGp⑽ 與輔助IGP 150則係透過一共享記憶體架構㈤脇職卿 architecture，UMA)來存取主記憶體模組11〇。 等 依據前述的制’賴賴巾具魏常知識者應可理解，電 腦系統100有可能不會使用到辅助IGp 150中的北橋電路252，故 #北橋電路252不需使用時，則可停止（disable)北橋電路252 之運作或將其關閉（turn 〇£〇。舉例而言，可利用圖形處理電路⑽ -.或主機板102上的其他控制單元，例如基本輸入/輸出系統⑽s， 未顯示）所產生之-控制訊號，來控制北橋電路M2停止運作。 在-實施例中’當-個IGP不是設置在主要咖所應安裝的位置 1281636 才主機板ι〇2便會產生並傳送一控制訊號至該iGp，以停止該 -IGP中之北橋電路的運作。 •在實_用上，可將辅助IGP W與主要IGp⑽設計成完全 彳目同的規格，以透過大量生產而進—步降低每―個聊的製造成 本另外，亦可將辅助IGP150設置於一擴充卡上，並將該擴充卡 插叹在主機板i 〇2之一適當插槽中，例如一 插槽或是一八⑶ 插槽。 m 第3圖所繪示為本發明一第二實施例之一電腦系統300簡化 後之方塊圖。與前述的電腦系統100類似，電腦系統300包含有 一主讀、體模組310、-中央處理單元320、一南橋電路33〇、一 主要IGP340、一辅助IGP350、以及一顯示裝置36〇。辅助IGp35〇 係透過直接设置在電腦系統3〇〇之一主機板3〇2上的一匯流排％ (例如一 PCI-E匯流排或一 AGP匯流排）來耦合至主要IGp 34〇。 _本例之電腦系統300與前述之電腦系統1〇〇的不同點之一，在於 電腦系統300的主要IGP 340具有一用來控制主記憶體模組3 J〇 之資料存取的記憶體控制器（未顯示）。在這樣的設計下，電腦系 統300的主要聊340不僅橋接中央處理單元32〇與南橋電路 330,還會橋接主記憶體模組31〇。以下將進一步說明電腦系統3〇〇。 請參考第4圖，其所繪示為電腦系統300之主機板3〇2之一 實施例簡化後的方塊圖。主要IGP 340包含有一北橋電路442，用 11 1281636 來橋接主記憶體模組310、中央處理單元320與南橋電路330 ; — 圖形處理電路444,耦合於北橋電路442,用來進行圖形處理運算； 以及一匯流排介面446，耦合於北橋電路442與圖形處理電路 444。如前所述，主要〗GP340包含有一記憶體控制器，該記憶體 控制器通常係設置於北橋電路442之内。辅助IGP 350包含有一北 橋電路452、一圖形處理電路454、以及一匯流排介面456。圖形 處理電路454係用來輔助圖形處理電路444之圖形處理運算，例 ^ 如，辅助其三維繪圖運算。與前面的實施例類似，辅助IGP350 中的圖形處理電路454係設計成具有能與主要1(^> 34〇之圖形處理 電路444相容的指令集，以利與圖形處理電路444進行資料或指 令的溝通。圖形處理電路444及454的搭配運作方式係實質上與 前述圖形處理電路244及254相同，為簡潔起見，在此不再贅述。 較佳者，圖形處理電路444與圖形處理電路454兩者係實質上相 同。 用來聯繫匯流排介面446與456的匯流排32，係一具有可溝 通圖形處理電路444及454之足夠頻寬的高速匯流排，實作上， 其可用一 PCI-E匯流排或一 AGP匯流排來實現。在電腦系統3〇〇 中，主要IGP 340與輔助IGP 350兩者皆係利用共享記憶體架構 (UMA)，透過北橋電路442來存取主記憶體模組31〇。運作上， 主要IGP 340與輔助IGP 350可透過主記憶體模組31〇來分享圖 形處理運异的參數’例如圖形材質（texture)與頂點（νεΓ|^χ)資 料等等。 ' 12 1281636 在具際應肖上，可將辅助IGp 35〇與主要iGp遍輯成完全 相同的規格，以進-步降低每一個IGp的製造成本。 由如述A $可知’本發明所提出具有多個整合型緣圖處理單 元（IGP)之主機板，適用於英特爾（以⑻的n平台、超微（从叫 + σ CPU^m另請注意，設置於一單 主機板上的輔助IGP的數目不並侷限於一個。前揭的多iGp架 構可拓展成包含兩個或兩個以上的輔助IGP。主機板上所能安裝 之辅助IGP的最大個數，係取決於主要IGp之匯流排介面所能支 援的最大頻寬。實作上，不同的辅助IGp可透過同一匯流排介面 電連接於主要IGP，亦可分別透過不同的匯流排介面來電連接於 該主要IGP。例如，假設主要IGp包含有一 ρα_Ε匯流排介面與 - AGP匯流排介面，則該主要IGp可透過該pCKE匯流排介面來 溝通部分的辅助IGP，並透過該AGp介面來與其他的辅助IGp進 行溝通。 相較於習知技術，本發明所提出的電腦系統不需使用額外的 南速橋接卡，故可降低硬體的成本。此外，可將所有的主要IGp 與輔助IGP皆直接設置於主機板上，以使所需的裝設空間降至最 低’進而縮小系統的體積。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 13 1281636 【圖式簡單說明】 第1圖為本發明之電腦系統之一第一實施例簡化後的方塊圖。 第2圖為第1圖之電腦系統中之主機板之一實施例簡化後的方塊Fig. 2 is a simplified block diagram showing an embodiment of a motherboard 1〇2 of a computer system. As shown, the primary IGP 140 includes a north bridge circuit 242 for bridging the central processing unit 120 and the south bridge circuit 130; a graphics processing circuit 244,|the horse is used in the north bridge circuit 242' The graphics processing is performed separately; and a bus interface 246 is coupled to the north bridge circuit 242 and the graphics processing circuit 244. Similar to the primary IGP 140, the secondary IGP 150 includes a north bridge circuit 252 north bridge circuit 252, a graphics processing circuit 254, and a bus interface 256. The circular processing circuit is used to assist the graphics processing operations of the graphics processing circuit 244 in the main IGpi4. For example, graphics processing circuitry 254 can be used to assist in the three-dimensional rendering operation of graphics processing circuitry 244. In practice, the graphics processing circuits 244 and 254 can simultaneously process different portions of the same frame in parallel, and can also process different frame data separately. In addition, the graphics processing circuit 244 is traversed by any known or subsequently developed load balancing algorithm to balance the amount of graphics computational load between itself and the graphics processing circuitry 254. In other words, the combination of the main IGP 140 and the auxiliary IGp 15〇 can be used as a brain system-graphic processing system. In one aspect, the graphics processing circuit (5) (or auxiliary chat 150) can be viewed as an additional go engine for adding two-dimensional graphics operations to the graphics processing circuitry 244 of the iGp 14 。. 9 1281636 Graphic processing circuit 244 in the main IGP 140 is designed to have a set of instructions compatible with graphics processing circuitry 254 in order to smoothly integrate graphics processing of both graphics processing circuits 244 and 254. In a preferred embodiment, graphics processing 244 can be designed to be substantially identical to graphics processing circuitry 254. In addition, bus bar 12 is a high speed bus that can communicate graphics processing circuits 244 and 254. For example, bus 12 can be a - PCI_E bus, and bus interfaces 246 and 256 can be PCI-E bus interfaces. Alternatively, the bus bar 12 can be an AGp bus, and the bus channels 246 and 256 can be implemented using an AGP bus interface. In practice, other suitable high speed bus and bus interface can also be used to communicate data between graphics processing circuits 244 and 254. In the present payment, the towel processing unit 12G includes a button controller (not shown) for controlling data access of the main memory module 110, and the main iGp (10) and the auxiliary IGP 150 are shared by one. Memory Architecture (5) The Secretary of State Architecture (UMA) accesses the main memory module 11〇. According to the above-mentioned system, it should be understood that the computer system 100 may not use the north bridge circuit 252 in the auxiliary IGp 150, so the #北桥电路252 can be stopped when it is not needed ( Disable) operation of the north bridge circuit 252 or turn it off (for example, a graphics processing circuit (10) - or other control unit on the motherboard 102, such as a basic input/output system (10) s, not shown) The generated control signal controls the north bridge circuit M2 to stop operating. In the embodiment, when the IGP is not set at the location where the main coffee shop should be installed, 1281636, the motherboard ι〇2 generates and transmits a control signal to the iGp to stop the operation of the north bridge circuit in the -IGP. . • In the real use, the auxiliary IGP W and the main IGp (10) can be designed to be completely different specifications, so as to reduce the manufacturing cost of each chat through mass production, and the auxiliary IGP 150 can also be set to one. On the expansion card, and sigh the expansion card in one of the appropriate slots on the motherboard i 〇 2, such as a slot or an eight (3) slot. m is a block diagram of a computer system 300 in accordance with a second embodiment of the present invention. Similar to the aforementioned computer system 100, the computer system 300 includes a main read, body module 310, a central processing unit 320, a south bridge circuit 33, a primary IGP 340, an auxiliary IGP 350, and a display device 36. The auxiliary IGp35 system is coupled to the primary IGp 34A through a bus % (e.g., a PCI-E bus or an AGP bus) that is directly disposed on one of the motherboards 3 〇 2 of the computer system. One of the differences between the computer system 300 of the present example and the aforementioned computer system is that the main IGP 340 of the computer system 300 has a memory control for controlling the data access of the main memory module 3 J. (not shown). Under such a design, the main chat 340 of the computer system 300 not only bridges the central processing unit 32 and the south bridge circuit 330, but also bridges the main memory module 31. The computer system 3〇〇 will be further explained below. Please refer to FIG. 4, which is a simplified block diagram of one embodiment of the motherboard 3〇2 of the computer system 300. The primary IGP 340 includes a north bridge circuit 442 that bridges the main memory module 310, the central processing unit 320, and the south bridge circuit 330 with 11 1281636; a graphics processing circuit 444 coupled to the north bridge circuit 442 for graphics processing operations; A bus interface 446 is coupled to the north bridge circuit 442 and the graphics processing circuit 444. As previously mentioned, the primary GP 340 includes a memory controller that is typically disposed within the north bridge circuit 442. The auxiliary IGP 350 includes a north bridge circuit 452, a graphics processing circuit 454, and a bus interface 456. The graphics processing circuit 454 is used to assist in the graphics processing operations of the graphics processing circuitry 444, such as assisting its three-dimensional graphics operations. Similar to the previous embodiment, the graphics processing circuit 454 in the auxiliary IGP 350 is designed to have a set of instructions that are compatible with the main 1 (^> 34 graphics processing circuitry 444 to facilitate data or graphics processing circuitry 444. The operation of the instructions. The operation of the graphics processing circuits 444 and 454 is substantially the same as the graphics processing circuits 244 and 254. For the sake of brevity, details are not described herein. Preferably, the graphics processing circuit 444 and the graphics processing circuit The 454 is substantially the same. The bus bar 32 for contacting the bus interface 446 and 456 is a high speed bus having a sufficient bandwidth to communicate with the graphics processing circuits 444 and 454. In practice, a PCI can be used. -E bus or an AGP bus. In the computer system, both the main IGP 340 and the auxiliary IGP 350 use the shared memory architecture (UMA) to access the main memory through the north bridge circuit 442. The module 31〇. In operation, the main IGP 340 and the auxiliary IGP 350 can share the parameters of the graphics processing and the transmission through the main memory module 31〇, such as graphic texture and vertices (νεΓ|^χ) data. Etc. ' 12 1281636 On the basis of the difference, the auxiliary IGp 35〇 can be integrated into the same specifications as the main iGp, in order to further reduce the manufacturing cost of each IGp. As can be seen from the description of A $ A motherboard with multiple integrated edge map processing units (IGPs) is proposed for Intel (with (8) n platform, AMD (from + σ CPU^m, please note that it is set on a single motherboard) The number of auxiliary IGPs is not limited to one. The previously disclosed multi-iGp architecture can be extended to include two or more auxiliary IGPs. The maximum number of auxiliary IGPs that can be installed on the motherboard depends on the main IGp. The maximum bandwidth that the bus interface can support. In practice, different auxiliary IGps can be electrically connected to the main IGP through the same bus interface, or can be connected to the main IGP through different bus interfaces. For example, suppose The main IGp includes a ρα_Ε bus interface and an AGP bus interface, and the main IGp can communicate part of the auxiliary IGP through the pCKE bus interface, and communicate with other auxiliary IGps through the AGp interface. According to the prior art, the computer system proposed by the present invention does not need to use an additional south speed bridge card, thereby reducing the cost of the hardware. In addition, all the main IGp and the auxiliary IGP can be directly disposed on the motherboard, Minimizing the required installation space to further reduce the volume of the system. The above description is only a preferred embodiment of the present invention, and all the equivalent changes and modifications made according to the scope of the present invention should belong to the present invention. 13 1281636 [Simple Description of the Drawings] Fig. 1 is a simplified block diagram of a first embodiment of a computer system of the present invention. Figure 2 is a simplified block diagram of one embodiment of a motherboard in the computer system of Figure 1.
圖。 第3圖為本發明之電腦系統之一第二實施例簡化後的方塊圖。 第4圖為第3圖之電腦系統中之主機板之一實施例簡化後的方塊Figure. Figure 3 is a simplified block diagram of a second embodiment of a computer system of the present invention. Figure 4 is a simplified block diagram of one embodiment of a motherboard in the computer system of Figure 3.
圖。 【主要元件符號說明】 12、32 匯流排 100、300 電腦糸統 102、302 主機板 110、310 主記憶體模組 120 、 320 中央處理單元 130 、 330 南橋電路 140、150、340、350 整合型繪圖處理單元 160 、 360 顯示裝置 242、252、442、452 北橋電路 244、254、444、454 圖形處理電路 246、256、446、456 匯流排介面 14Figure. [Main component symbol description] 12, 32 bus bar 100, 300 computer system 102, 302 motherboard 110, 310 main memory module 120, 320 central processing unit 130, 330 south bridge circuit 140, 150, 340, 350 integrated type Drawing processing unit 160, 360 display device 242, 252, 442, 452 Northbridge circuit 244, 254, 444, 454 graphics processing circuit 246, 256, 446, 456 bus interface 14