TWI279081B - Voltage level shifter - Google Patents

Abstract

A voltage level shifter is disclosed, which comprises an inverter, a first NMOS transistor coupled with a fist PMOS transistor through a second gating device, and a second NMOS transistor coupled to a second PMOS transistor through a first gating device. Gates of the first and second NMOS transistors are coupled with the input signal and an output terminal of the inverter individually, and gates of the first and second PMOS transistors are coupled with sources of the second and first NMOS transistor, with the source of the second NMOS transistor as an output terminal of the voltage level shifter. The first/second gating device is capable of restricting a leakage current from the second/first PMOS transistor to the second/first NMOS transistor when logic state of the input signal is changing, and therefore the voltage level shifter has a larger output/put voltage ratio.

Description

1279081 Yes, invention says ^^ — ----— [fam::, technical field] Especially the right bs system has a kind of potential converter (1 eve 1 shif seven er ), and if = one can improve the conduction moment A potential converter that produces a leakage current ratio of the output/input voltage. L no technology] work ^ ^ years two & CM0S transistor-based digital logic integrated circuit of the 06 4 ί is shrinking 'this system because of the lower operating voltage can have more CMOS ^ f loss and faster Signal conversion time. Now available ^»^,, the supply voltage source of the logic integrated circuit includes m, 2.^, 1. person = and h 5V and so on. However, it is often necessary to use a different CMOS technology to cause a potential converter (v〇ltage shifter) to convert signals generated by the _ ^ voltage source to signals with different voltage levels. In the past 4 years, many different types of CM〇s potential have been developed to convert a low voltage amplitude digital signal to a higher voltage amplitude signal. Figure 1 shows a conventional potential converter comprising an inverter 1 consisting of a PMOS transistor P3 and an NMOS transistor N3 disposed between a voltage source VCC1 and a reference voltage (for example, a quasi-position) Used to convert an input VIN to its inverted signal. The inverting signal is coupled to the gate of a PM0S transistor P2 through a NM〇s transistor N1 and directly coupled to the gate of an NM0S transistor N2, wherein the source of the transistor p2 is connected to a voltage source VCC2 'The source of the transistor N2 is connected to the reference voltage (shown as the position in the figure), and the drain of the transistor P2 is connected to the drain of the transistor N2 to be the output of the potential converter. And output an output signal ν 〇υ τ;

Γ 279081 暴, invention description (2) ' ' The potential converter further includes a PMOS transistor pi disposed between the voltage source VCC2 and the gate of the transistor P 2 , and the gate of the transistor p 1 is coupled to the output signal VOUT. Preferably, the voltage source VCC1 and the reference voltage are substantially equal to the high logic level and the low logic bear level of the input signal V I N , respectively. In addition, the voltage source VCC2 is generally higher than the high logic state of the input signal y I n in use, so that the high logic state of the output signal VOUT is higher than the high logic state of the input signal VI N . When the potential converter starts to start, if the voltage source is turned on, VCC1 is turned on first and then the voltage source VCC2 is turned on. Therefore, there is a short time when the power source # is turned on and the voltage source VCC2 has not been turned on. However, at the moment when the conventional potential converter starts to operate, the input signal remains at the low level ^, and since the voltage source VCC1 is turned on and the voltage source VCC2 is not turned on, the transistors Ρ3, Ν1 and Ρ1 are both turned on, and there is a leak. The current I (in the direction of the % arrow as shown) flows from the voltage source VCC1 to the voltage source VCC2 via the transistors Ρ3, Ν1 and Pi. This is a malfunction and adds unnecessary power loss. In view of the above-mentioned shortcomings of the prior art, the inventor of the present invention has proposed an improved potential converter in the patent application (positive and validated) of the invention entitled "potential converter" in the case number 9 2 1 3 9 1 0 1. It modifies the coupling relationship of the transistors in the conventional potential converter, and does not generate the path of the bubble leakage when the voltage source is sequentially turned on. Therefore, the leakage current can be eliminated and the power consumption can be changed. ° Fig. 2 is a circuit diagram showing the potential converter provided in the patent application No. 9 2 1 3 9 1 0 1 'including a PIO transistor P3 ° ^; M〇s transistor

1279081 Each invention description (3) The inverter 20 composed of N3 is disposed between the voltage source VCC1 and a reference voltage (for example, the position in the figure); a PMOS transistor P1 and an NMOS transistor N1 are disposed at a voltage Between the source VCC2 and the reference voltage; and a PMOS transistor P2 and an NMOS transistor N2 are disposed between the voltage source VCC2 and the reference voltage. The inverter 20 is configured to convert the input signal VIN of the potential converter to the inverted signal VINI, and the gates of the transistors N1 and N2 respectively receive the input signal VIN and the inverted signal VINI. The drains of the crystals N1 and N2 are respectively coupled to the gates of the PMOS transistors P2 and P1, and the drain level of the transistor N2 serves as the output signal VOUT of the potential converter. Similar to the conventional potential converter shown in FIG. 101, the voltage source VCC1 and the reference voltage are preferably equal to the high logic state level and the low logic state level of the input signal VN, respectively; The voltage source VCC2 is generally higher than the level of the high logic state of the input signal VIN, so that the high logic state of the output signal νουτ is higher than the high logic state level of the input signal V丨N. Moreover, when the potentiometer is turned on, the voltage source VCC1 is turned on first and then VCC2 is turned on. As can be seen from Fig. 2, the potential converter differs from the conventional potential converter in the manner in which the transistor N1 is coupled. Due to the change of the coupling mode of the transistor N1, when the input of the potential converter is turned on at the moment when the potential converter of the embodiment starts to be turned on, even if the voltage source VCC1 is turned on, the voltage source vcc2 is not turned on. The path does not exist and the leakage current will not be generated. The operation of the potential converter in Fig. 2 will be described in detail below to illustrate its improvements. First, assume that the logic state of the input signal VIN changes from high to low, that is, to the status, which causes the transistor to be turned off.

0697-A40440TWF(η1);Ρ2005-〇〇2; (3⁄4 ιν〇ΥΕΝ.ptd Page 9 Ϊ279081 each, invention description (4) Since the output signal VOUT was originally at the high level of VCC2, the transistor P1 is also at this moment. In the off state, the node 22, that is, the gate of the transistor P2, does not drive to any particular voltage and floats. At the same time, due to the input, the number VIN is in a low logic state, so the inverter 2 In the crystal of the crucible, P3 is turned on and the transistor N3 is turned off, and the voltage level of the inverting signal VINI is pulled up to VCC1', which causes the transistor N2 to start conducting, so the output signal VOUT starts to approach the low logic state of the position. However, since the VCC1 of the inverted signal VINI is lower than VCC2, and the gate voltage of the transistor P2 is floating and is not cut off, the output signal can not be pulled down to a level close enough to the ground I. After ten, As the output signal VOUT drops, the transistor P1 starts to conduct and the voltage of the node 22 approaches VCC2, which cuts off the transistor P2. The cutting of the transistor P2 causes the current from the voltage source VCC2 to flow through the transistor P2 to the transistor N2. More reduced, The output signal V0UT can be closer to the position. The 3A, 3B and 3C diagrams show that the potential converter provided by the present invention inputs the signal viN and the output signal when the voltage source VCC1 is 1·8V and the voltage source VCC2 is 2.5V. The waveform comparison diagram of the V 0 UT variation relationship, wherein the 3a, 3B, and 3 C diagrams respectively compare waveforms using three different transistor type combinations, and the combinations of the three transistor types are respectively? 7(1^1)1(:^1^〇3, typical NMOS, 25C), PFNS (fast PMOS, slow NM0S, 125C), and PSNF (slow PMOS, fast NMOS, -40C). It is obvious that when When the level of the input signal VIN changes from high to low, the position of the output signal νουτ using the PFNS type combination potential converter in Fig. 3B will drift and there will be a timing delay problem compared to the input signal. 0697-A40440TWF(nl) ; P2005-002 ; CHINGYEN. ptd Page 10 Ϊ 279081 Lost, invention description (5) The 4A, 4β and 4C diagrams show that the potential source VCC1 provided by the present invention is 1>8V and the electric number #VCC2 is increased to 3 3v When comparing the waveform of the relationship between the electric VIN and the output signal V0UT, and enter the signal PTNT, PFNS And the waveform circle of the PSNF transistor combination type. It can be seen that when the level of the input signal VIN changes from high to low, the output of the potential drag of the SPFNS type is combined in the figure. The level of the signal V 0 UT will drift more severely and has a more pronounced timing delay problem than ==. ^ The reason for the reason is as described above, because when the input signal VIN level is changed, only the transistor N2 is turned on but the electro-crystal body P2 connected to the voltage source VCC2 is not cut off, and the inverted signal ^!^ bit is added. Quasi-VCC1 is less than VCC2, because = has a leakage current flowing from voltage source VCC2 through transistor P2 to the transistor, so the output signal VOUT can not be quickly pulled to a low enough level, and must wait for the output signal VOUT to be returned to the power When the crystal P1 cuts off the transistor P2 and the 'leakage 2 flow decreases, the output signal VOUT can be reduced to a level close enough. When the voltage source VCC2 increases, the leakage current rises to cause the output voltage vqut to shift and the timing delay is more pronounced. Therefore, the potentiometer cannot operate at a large output/input voltage ratio. i Next, the logic state of the input signal VIN changes from low to high, that is, the level shifts to VCC1. Therefore, the transistor N2 starts to conduct and the voltage of the node 22 decreases toward the position, which causes the transistor P2 to be turned on and outputs the signal ν〇ϋτ. The position is ascending in the direction of VCC 2; however, since the output signal ν 〇υ τ is originally a standard, the transistor Ρ 1 is also in a conducting state at this moment. When the transistors P1 and ^ are both turned on, and the level of the input signal VIN VCC1 is lower than VCC2, therefore

0697 - A40440TWF (η 1); Ρ2005 - 002; CHINGYEN. Page 11 1279081 Swallow, invention description (6) One: 3⁄4 leakage current flows from voltage source VCC2 through transistor Ρ1 to Ν1, the voltage of section 22 cannot be reduced to Close enough to the status. At the same time, since the input signal VIN is in the high logic state of VCC1, the transistor P3 in the inverter 2 is turned off and the transistor N3 is turned on, and the position of the inverted signal viNI is also leveled. Drop 'This causes the transistor N 2 to cut off. Since the voltage source % c 1 is substantially the same as the high logic state level of the input signal VIN, the reverse signal and VI NI can be close enough to the ground to make the transistor N2 cut off sufficiently, even if the node The position of 22 can't be pulled down enough to make the transistor P2 turn on enough, but because the transistor!^2 is cut enough, the output ►V0UT can still be close enough to KC2. ° In Figures 3A, 3B, 3C and 4A, 4B, 4C, it can be seen that when the level of the input signal VIN changes from low to high, the waveform of the output signal ν〇υτ is not as obvious as the position of the round signal VIΝ. Problems such as the occurrence of quasi-horizontal delay and delay in the case of high turn-down. After 曰, since the output signal V0UT is substantially pulled up to a high level, the transistor pi starts to be cut, which causes the voltage leakage from the voltage source VCC2 flowing through the transistor P1 to the transistor 更为1 to be further reduced, so that the node 2 2 is closer. The status is accurate, and the position of the round-off signal is closer to VCC2. • In summary, one can improve the leakage current at the time of input signal switching to increase the output/input voltage ratio, and does not generate when the voltage source is turned on sequentially: the potential converter of the leakage current has a person skilled in the art. Going to technology. [Description of the Invention] The present invention provides a potential converter, which is characterized in that it can improve the output signal level shifting by the logic energy of the input signal by using the gate control page 12 Ϊ 279081 i and the invention description (7). Limiting the leakage current, and thus the result, the timing can be operated at the timing of the larger round/out wheel input signal, and the ratio of the electric/input voltage is improved; and the electric current can improve the power consumption sequence. The moment of opening does not produce line leakage - the potential converter consists of - inversion $, set in the reverse signal; between the two reference voltages '帛 to convert - input signal to its second axis: R NM〇S electricity, body With the first - PM0S transistor set in a nightmare coupled with people: flute! Wherein the first NMOS transistor is connected to the second voltage source via a second gated two PMOsi day e-PM〇S transistor; and a second NM〇S transistor and a first: PM0Sf body are disposed between the second voltage source, wherein The second _s^ thyristor is coupled to the second PM 〇S transistor. The gates of the first and second S transistors respectively receive the input signal and the inverted signal; the gates of the first and second PMOS transistors are respectively coupled to the second and first .os transistors The drain is poled, and the drain of the second NMOS transistor serves as the wheel terminal of the potential converter. The first gate control device is turned off when the input signal is low, and the high level is turned on. Therefore, when the input signal is switched from the south to the low level, the second voltage source is restricted from flowing through the second PMOS transistor to the first The leakage current of the 〇s transistor is such that the level of the output signal drifts and the timing delay relative to the input signal is improved. Similarly, the input signal of the second gate device is turned on at a low level and turned on at a high level. When the input signal is switched from a low level to a high level, the second voltage source is restricted from flowing through the first PM0 transistor to the first Leakage current of two NM0S transistors, due to

1279081 Department, invention description (8) can make the transmission = signal level shift and payment relative to the input signal, and second, because when the input signal changes logic state, turn out the 'section 5 faster record change logic state Thus, the present invention has an output/input voltage ratio. The above and other objects, features, and advantages of the present invention are set forth in the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Small Port [Embodiment] FIG. 5 shows the first example of the potential converter proposed by the present invention. It is noted that FIG. 5 is in addition to the first gate device G1 for the electro-crystal and the transistor N2. And the second gate device G2 is added between the transistor μ and the transistor ,1, and the rest is identical to the second figure. In the present embodiment, the first gate control device G1 is a PM0S transistor ρ4, the gate of which is coupled to the inverted signal VINI of the potential converter input signal Vi ,, and the second gate control device is PM0S The crystal Ρ5 has its gate _ coupled to the input signal VIN of the potential converter. In order to clarify the advantages of the potential converter provided by the present invention, the operation thereof will be analyzed in detail below. First, suppose that the logic state of the input signal V Ν is turned from low to low, that is, the state of the transistor 切断1 is turned off and the transistor Ρ5 is turned on; and since the output signal v〇UT is originally at the high level of VCC2 Therefore, the transistor Ρ1 is in a state of being cut off, and as a result, the nodes 54 and 5 are floating. At the same time, since the input signal V I Ν is at a low level, the transistor Ρ 3 in the inverter 50 is turned on and the transistor Ν 3 is turned off, and the voltage level of the inverted signal V IN I is pulled up to VCC1, which makes the electricity Crystal N2 starts to conduct and electricity

0697-A40440TWF(nl);P2005-002;CHINGYEN.ptd Page 14 1279081 Swallow, invention description (9) &quot;&quot;&quot; --- Crystal P4 starts to cut off, so the output signal drops to the low level. It is noted that the voltage level VCC1 of the inverting signal VINI is lower than VCC2, so in the case of the transistor P4, since only the transistor N2 is turned on, the electric body P 2 connected to the voltage source vc = is not turned off. There will be a leakage current flowing from the voltage source yc C 2 through the transistors P 2 to N 2 , which prevents the output signal from being pulled down sufficiently close to the positional potential, which is the disadvantage of the potential converter in Figure 2 described above. However, in the present invention, the added transistor P4 is turned off at this time, so that the leakage current flowing from the voltage source VCC2 through the transistor P2 to the transistor N2 can be limited, so that the output signal can be closer to the position. As a result, compared with the potential converter 1 of FIG. 2, when the input signal of the present invention is converted from a high logic state to a low logic state, the level of the output terminal can be converted from a high logic state to a low logic more quickly. state. After that, since the turn-off signal V0UT starts to fall, the transistor P1 starts to conduct, the position of the node 54 rises to VCC2, and since the transistor is in the on state, the node 52 is pulled to VCC2 to make the transistor p2. The cutting of the transistor P2 causes the leakage current flowing from the voltage source VCC2 through the transistor p2 to the transistor to be further reduced, so that the output signal "" is closer to the position. Next, the logic state of the input signal V IN From low to high, that is, level, to vcci 'so transistor N1 is turned on and transistor p5 is turned off, which causes the voltage of node 52 to pull down to the position, so transistor p2 starts to conduct and the signal starts to VCC2 The direction is rising; and since the output signal νουτ is originally in the state of 'the transistor Ρ1 is in the on state. Note that since the level VCC1 of the input signal VIN is lower than ¥(:(:2 is low, if there is no transistor P5) In the case of 'only transistor N1 is turned on and connected to the voltage source redundantly

〇 697-A40440TWF(nl); P2005-002; CHINGYEN.ptd Page 15 1279081 Swallow, invention description (10) The transistor P1 is not cut, there will be - bubble current from the voltage source vc crystal P1 to N1, the result The voltage at node 52 cannot be pulled down to the foot ς = standard, which is the disadvantage of the potential converter of Figure 2. However, in the present invention, the transistor Ρ5 is cut off at this time, thereby limiting the leakage current flowing from the voltage source VCC2 through the transistors P1 to N1, so that the voltage of the node 52 is closer to the ground: the result of the quasi-09 is associated with the transistor P2. The conduction level is increased and the output signal..." is further connected to VCC2. At the same time, since the input signal VIN is in the high logic state of vcn', the transistor P3 in the inverter 50 is turned off and the transistor N3 is turned off. Pass, the voltage level of the inverted signal VINI drops to ground, which causes the transistor to turn on ► and the transistor N 2 is turned off. As described in the potential converter shown in Figure 2, since the voltage source VCC1 is approximately close to the input The low logic state level of the signal v I n , so the inverted signal VIN I can be close enough to the positional standard, which makes the electro-crystal "body N2 cut off to a sufficient extent, even if no transistor p5 is added to make the voltage of the node 52 Closer to the status and increase the degree of conduction of the transistor p2, the turn-off signal can still approach VCC2. However, due to the addition of the transistor p5, the voltage of the node 52 can be closer to the position, and as a result, the transistor P2 is turned on more and the output signal V0UT is further connected to VCC2. Compared with the potential converter of FIG. 2, when the input signal of the present invention is converted from a low logic state to a high logic state, the node 5 2 can be converted from a high logic state to a low logic state more quickly, thus The level of the output signal VOUT can be converted from a low logic state to a high logic state more quickly. After that, since the output signal V0UT rises, the transistor P1 starts to be cut off, which causes the voltage source VCC2 to flow through the transistors PI, P5 to N1 to be further reduced, so that the voltage of the node 52 is closer to the position, which makes the electricity Crystal P2 conduction

0697-A40440TWF(nl);P2005-002;CHINGYEN.ptd Page 16 1279081 Swallowing, invention description (Π) The degree is increased, and the output of the 6A, 6B, and 6C diagrams provides the potential converter for electricity 2·5V and 3· At 3V, and in the case of PSNF, the waveform of the input is compared. When the output voltage is low, the output signal V〇UT 7 C can be quickly moved to the level of the figure and the timing I level is changed from low to high, that is, the output signal V0UT is not clearly comparable. 3B and 6B, V0UT The timing is closer to the VCC1 level of the signal V0UT. The 7A, 7B, and 7C diagrams respectively show that the voltage source VCC1 of the present invention is 1 · 8V, and the voltage source VCC2 and the transistor combination type are PTNT and PFNS, and the relationship between the input signal VIN and the output signal V0UT is obvious. When the level of the input signal V in is shifted from the high level to the 6A, 6B, 6C and 7A, 7B, from high to low, the delay phenomenon such as 36, 4A and 4] 8 does not occur. In addition, when the input signal V0UT causes the 3A, 3B, 3C and 4A, 4B, 4C pictures to show the level shift or timing backward problem, but the 4B and 7B still observe the output signal of the present invention VIN . In the embodiment shown in Fig. 5, when the potential converter starts to conduct, the two voltage sources VCC1 and VCC2 are also sequentially turned on. Since the fifth technique is the same as the conventional technique of FIG. 2, the transistor Ni has one end coupled to the ground, so that when the potential converter is initially turned on and the input signal is still low, even if the voltage source VCC1 is turned on. However, the voltage iVCC2 is not turned on, and there is no path that causes leakage current, that is, leakage current does not occur. In summary, the potential converter proposed by the present invention does not generate a bubble leakage current when the voltage sources VCC1 and VCC2 are sequentially turned on, thereby improving power consumption; and inputting a logic state of the signal during operation. When changing, it can reduce the leakage current and improve the output signal level drift and timing delay with respect to the input signal, so it can operate on a larger output.

1279081 4. Invention description (12) / input voltage ratio. Figure 8 is a view showing a second embodiment of the potential converter of the present invention. Note that Figure 8 is in addition to the first gate control device G1 2PM〇s transistor p4 and the pM〇S transistor of the second gate device. P5 is changed to NM0S transistor N4 and Nf ' respectively, and the gate of transistor N4 is changed to be coupled to input signal η n , and the gate of transistor N5 is changed to be coupled to the inverted signal VINI, and the remaining components are coupled with the mode Both are identical to the circuit of Figure 5. The reason for this change is that the purpose of the first gate control device G1 is to turn off the input signal v N when the low level is on, and to turn on the south level on time. The logic state of the input signal VIN is limited to the voltage source VCC2 flow from the high to the low temple. The current through the transistors p2 to N2, so that the first gate device G1 can be replaced by the PMOS transistor P4 to the NMOS transistor N4 and the bean gate is coupled to the input signal VIN for the same purpose; a The purpose of the first gate control device G2 is that the input signal VIN is low and the time is on, and the 1st position is closed on time. The logic state of the input signal vin is limited by the low voltage = when the voltage source VCC2 flows through the transistor {^ The current to ..., so S: Ϊ ί G G2 is replaced by _ transistor P5 to _S transistor N5 and 8.3 poles coupled to δ to the inverted signal v 丨 N to achieve the same purpose. Since the detailed operating principle of apricot = is related to the 50th *_, it is no longer only commented here. While the invention has been described in terms of the preferred embodiments of the present invention, it is understood that the invention may be濩 濩 0697-A40440TWF(nl); P20〇5-002; CHINGYEN.ptd Page 18 1279081 Diagram, simple description [Simplified illustration] Figure 1 shows the circuit diagram of the conventional potential converter; Figure 2 shows A circuit diagram of an embodiment of a potential converter of the present invention; FIGS. 3A, 3B and 3C show waveform diagrams of 'input and output signals' of a potential converter of FIG. 2 in different combinations of transistor types; 4A, 4B And the 4C diagram shows the potential converter of Fig. 2 using another voltage source and combining the different transistor types, the waveform of the input and output signals; &gt; Figure 5 shows the potential converter of the present invention A circuit diagram; μ aw The sixth, sixth, and sixth diagrams show the waveforms of the input and output signals of the first embodiment of the potential converter of the present invention under different combinations of transistor types: Fig. 7A, 7B, and 7C A waveform diagram showing the wheeled-in and output signals of a first embodiment of the potential converter of the present invention using another voltage source and combining different transistor types; &amp; Figure 8 shows the potential converter of the present invention Second implementation | Road map. [Main component symbol description] 1 0, 2 0, 5 0, 8 0 to inverter 22, 52, 54 to node G1 to first gate device G2 to second gate device

T279081 Brief description of the group type I ~ Leakage current Ν: 1-N5 ~ NMOS transistor P1-P5 ~ PMOS transistor VCC1, VCC2 ~ voltage source V I N ~ input signal VINI ~ VIN inverted signal VOUT ~ output signal Φ

0697 - A40440TWF( η 1); P2005 - 002; CHINGYEN. p t d Page 20

Claims (1)

I279D81 And, the scope of patent application 1 · A potential converter, including to convert between: the first voltage source and - reference voltage, with 锝? The Wu wheel input signal is an inverted signal; the second transistor has a second source/drain connected to a second source of lightning, and the pole is connected to the output of the potential converter; Two crystals ', / first source / drain is coupled to the first - transistor = source / and pole 'the other two source / drain connected to the pole connected to the input signal; ^ Wan Electric & eight gate: third a crystal, the second source/drain connection source 'its source is connected to the first source of the second transistor /=; the first (two) two of the electricity: * body 2 its first-source &quot; and polar coupling a source/drain to the third transistor and as a non-polarization of the potential converter; to the reference voltage, a gate connected to the original signal of the inverted signal is connected to the third The crystal and the fourth transistor=the first one-position is closed on time, and when the input signal is the first and second electro-crystalline systems, the second and fourth electro-crystalline systems are second. Type Yang ^ crystal. The potential converter of claim 1, wherein the first gate control device is configured to limit the flow from the second voltage source when the input signal is switched from the second level to the first level. Current through the third to fourth transistors. 3. The potential converter of claim 1, further comprising a second gate control device coupled to the first transistor and the second transistor 0697-A40440TWF(nl);P2005-002;CHINGYEN.ptd Page 21 1279081 $, between the scope of the patent application 'When the input is missing, i was the second time when the K is the standard when the 'on the input signal' a 4:2°]: the potential converter according to the third aspect of the patent, wherein the time limit input is switched from the first level to the electricity of the two transistors; and the voltage source flows through the first power The crystal to the inverting 5 device 专% special! The potential converter, wherein the phase is connected in series - complementary side and - the second side 3 electro-crystal Zhao Zhao mutual first 6 door 3:; The potential converter, wherein the first type of MOS transistor has a gate connected to the Γ 第: 1/1 ΐ connected to the fourth source of the fourth transistor &quot; A source/drain is connected to the first source/drain of the third transistor. 7. The potential converter according to claim 2, wherein the first gate device is a second type M〇 a s transistor having a gate connected to the input signal, a first source/drain connected to the first source of the third transistor, and a second source/drain connected to the fourth The first source of the crystal/drainage/8. The potential converter of claim 4, wherein the second gate device of the age is a first type MOS transistor, the gate of which is connected to the input The first source/drain is connected to the first source/drain of the second transistor, and the second source/drain is connected to the first source/drain of the first transistor. The potential converter according to claim 4, wherein the second gate device is a second type M 〇S transistor whose gate is connected to the reverse signal, and the first source/drain connection To the first source of the first transistor / 汲〇 697-A40440TWF (nl); P2005-002; CHINGYEN.ptd page 22 1279081 0697-A40440IW(nl);P2005-002;CHINGYEN.ptd第23页