1278639 九、發明說明： 【發明所屬之技術領域】 更詳而言之，本發明 之測試治具。 本發明係有關於一種測試治具， 係有關於一種應用於記憶體電性測量 【先前技術】 南速電路和電 的基準，而更快的 能力和空間的問題 因此，隨著電路工 乎所有設計都遇到 問題。一般來說 之完整性。 路板的佈線密度已成為今日數位產品 晶片組和多層電路板設計可以解決處理 ’但是也更容易受到電路異常的影響。 作頻率的提高，不管信號週期如何，幾 了信號完整性（叫㈣integrity ;SI) 係使用示波器觀察電路設計並評估信號 當使用者利用示波器對例如雙排直插式記憶體（_ ^LnlM"〇r"Modules;DIMM) t整性測1時，通㈣先參照職圖以制待測 二=精路圖，找出該待測信號線對應該咖 :性輪而上的導電片（俗稱“金手指”），在記憶體上 ^出所找導電片直接電性連接的且便於焊接的元 1=:)，將引線焊上。最後，利用示波器之測量探頭 ^觸该引線，以對該記憶體中之待測信號線的信號完整性 進订測量。完成測量後，去該引線並重複上述步驟， 以對下一條信號線進行測量。 ’首先，將引線焊接至電 點為一通孔（v i a )時，則 唯，此種做法存在諸多缺失 路板上十分困難，尤其是若焊接 18788(修正本） 5 1278639 ㈣通孔上的絕緣漆才能進行焊接操作。而且，到絕 .接=必須十分小心，若絕緣漆到不乾淨，將無法完 .接，但’若過度刮除絕緣漆又會破壞通孔結構甚至 路、，以致於影響電路板之性能；又，更嚴重的情況為找不 到通孔，則只能焊接於電性連接 須除…… 同時，測量完後亦必 用、：應用此種習知技術除了不利於重複使 卜，更美尚了成本，而且浪費大量時間。 此外’為了方料接操作以及受限焊接技術之極限， 2往往不能太短’因為引線太短所焊上之引線較細會令 7點相對很小，易造成引線脫落，過長的引線則不利於 2傳輸’而勢必會令測量結果受到外界干擾，造成測量 =差亦相對增大。而且，由於需要焊接之引線數量比較多， 热法-次將所有引線都焊接到電路板上，必須多次開機、 關2、、=及插、拔該記憶體，而這些動作不僅容易對記憶 :4成損狄更使得測試操作繁瑣，故勢必需要浪費更多 時間，且更嚴重影響測量效率。 、 因此，如何提供一種有助於快速、準確、安全方便且 可重複使用之記憶體測量技術，藉此提高測量效率、減少 干I節省成本並k供使用便利性，以解決習知技術之種 種缺失，實為目前業界亟待探討之課題。 【發明内容】 為解決上述習知技術之缺點，本發明之主要目的在於 提t、種可快速、準確地進行測量之記憶體測試治具。 本發明之另一目的在於提供一種安全方便之記憶體 6 18788(修正本) 1278639 測試治具。 本發明之再一目的在於提供 .體測試治具。 種』董禝使用之此憶 本發明之又一目的在於提供一 記憶體測試治具。 《可“測1效率之 .憶體又另-目的在於提供-種可節省成本之記 .·性之=::具1的在於提供-種可提供使用便利 為達成上述目的及並袖曰 m 〇β,| ^ 八 々，本發明即提供一種記f咅1278639 IX. Description of the invention: [Technical field to which the invention pertains] In more detail, the test fixture of the present invention. The present invention relates to a test fixture, relating to a method for measuring electrical properties of a memory [prior art] a south speed circuit and an electric power, and a problem of faster capability and space, therefore, with the circuit work Design has encountered problems. Generally the integrity. The wiring density of the board has become a digital product today. The chipset and multilayer board design can solve the problem' but is also more susceptible to circuit anomalies. The frequency is improved, regardless of the signal period, several signal integrity (called (four) integrity; SI) is to use the oscilloscope to observe the circuit design and evaluate the signal when the user uses the oscilloscope to, for example, double-in-line memory (_ ^LnlM"r"Modules; DIMM) t When the integrity test is 1, pass (four) first refer to the job map to make the test 2 = fine road map, find out the signal line to be tested corresponding to the coffee: the conductive film on the sex wheel (commonly known as " Gold finger "), on the memory to find the conductive piece directly connected to the conductive piece and easy to solder element 1 =:), the wire is welded. Finally, the oscilloscope's measuring probe is used to touch the lead to make a predetermined measurement of the signal integrity of the signal line to be tested in the memory. After the measurement is completed, the lead is removed and the above steps are repeated to measure the next signal line. 'Firstly, when the lead wire is soldered to a via (via), it is very difficult to do so in many ways, especially if soldering 18788 (Revised) 5 1278639 (4) Insulating varnish on the via hole The welding operation can be carried out. Moreover, it must be very careful to the absolute connection. If the insulating paint is not clean, it will not be completed, but 'if excessively scraping the insulating paint will damage the through-hole structure or even the road, so as to affect the performance of the circuit board; Moreover, in a more serious case, if the through hole is not found, it can only be soldered to the electrical connection. In addition, it must be used after the measurement, and the application of this conventional technique is not conducive to repeated repetition. The cost and waste a lot of time. In addition, 'for the connection of the material and the limit of the limited welding technology, 2 is often not too short' because the lead wire is too short, the thinner the lead wire will make the 7 point relatively small, and the lead wire will fall off easily. The transmission at 2 is bound to cause the measurement results to be disturbed by the outside world, resulting in a relatively large increase in measurement = difference. Moreover, since the number of leads to be soldered is relatively large, all the leads are soldered to the circuit board by thermal method, and it is necessary to turn on, off, and/or insert and unplug the memory multiple times, and these actions are not only easy to remember. : 4 damage Di Di makes the test operation cumbersome, so it is necessary to waste more time, and more seriously affect the measurement efficiency. Therefore, how to provide a memory measurement technology that is fast, accurate, safe, convenient, and reusable, thereby improving measurement efficiency, reducing dry I cost, and convenience for use, to solve various kinds of conventional technologies. The lack of it is a topic that needs to be discussed in the industry. SUMMARY OF THE INVENTION In order to solve the above disadvantages of the prior art, the main object of the present invention is to provide a memory test fixture capable of performing measurement quickly and accurately. Another object of the present invention is to provide a safe and convenient memory 6 18788 (Revised) 1278639 test fixture. Still another object of the present invention is to provide a body test fixture. A further object of the present invention is to provide a memory test fixture. "Can be measured 1 efficiency. Recalling the body and another - the purpose is to provide - a kind of cost-saving record. · Sex =:: 1 is provided - can provide ease of use in order to achieve the above objectives and 〇β,| ^ gossip, the present invention provides a kind of record f咅
版測忒治具，係應用於且 U 量，哕圮产辦、a^+ 連接鳊的記憶體之電性測 電性連接端電性連接之第一^处連接和具有用以與該 治該第一連接邻日士 ^ v电、、、口構，以在該記憶體藕接 電性連接二:第體=記，試治具形成 春第二導電姓構^ -山 /、有舁外部裝置電性連接之 )與外;裝置藕憶體測試治 二，第二連接部二= 罘一導電結構電性i表技廿已A 命包、、、口構及 豆中，n # ^ W。σ卩外露於該記憶體測試治且。 二：Γ可例如為雙排直插式記憶錄The version of the test fixture is applied to the first connection of the electrical connection of the electrical measuring connection of the memory of the U, the production, and the a^+ connection, and has the same The first connection is adjacent to the Japanese ge, ^, electric, and mouth structure, in order to connect the electrical connection in the memory: the first body = record, the test fixture forms the second conductivity name of the spring ^ - mountain /, there are The external device is electrically connected to the outside; the device is tested and the second connection is connected to the second device. The second connection is divided into two. 罘 导电 导电 导电 导电 导电 导电 导电 导电 廿 廿 廿 廿 廿 廿 廿 廿 廿 廿 廿 廿 A A 命 命 命 命 命 命 命 命 命 命 命W. σ卩 is exposed to the memory test. Two: Γ can be, for example, a double-row in-line memory recording
Line Memory Modules · nTMun ^ 電路板或主機板。 ，该外部裝置為印刷 =地’該第-連接部係為一 弟一導電結構由複數個 插^之、、、。構。该 守私月所構成，而該第二導電 18788(修正本） 7 1278639 、、、。構則由硬數個金屬導電片所構成。於 中，該測量部係具有複數個測量只m 以成列方式佈設置於該測量部之：:上且=測量單元乃 5 人歷 < 本體上，同時該測量單元 可為至屬引腳，該等金屬引腳復可設有編號。 ，體知技術，本發明提供可作為諸如轉接頭之記 具，該記憶體測試治具係設計第—連接部盘第 lit 別f性連接至記憶體之電性連接端以及電路 电性連接端插槽並將二者進行電 準確__電性進行測量。而:電:=可= 技t限於¥接操作以及焊接技術之極限所造成之干擾及 測量誤差等缺點，不對記憶㉘ 一 爻 接技術，提供—種安全方便之記憶體測試治^ =::開機、關機、以及插、拔該記憶體等動作， 古拉Γ時’藉由測量部將記憶體内部之線路導出，因此可 直接猎由例如示波器等儀器進行記憶體電性之測量，而且 引線極短’更可將外界對信號之干擾降到最低。此外，本 發明之記憶體賴治具係可插拔，因此可多次重複使用， 亦降低了習知技術測量記憶體電性之成本，相對節省 並提供較佳之使用便利性。 【實施方式】 、以下係藉由特定的具體實施例說明本發明之實施方 式，所屬技術領域中具有通常知識者可由本說明書所揭示 之内谷輕易地瞭解本發明之其他優點與功效。纟發明亦可 18788(修正本) 8 1278639 “他不同的具體實施例加以施行或應用，本說明壹中 、項細節亦可基於不同觀點與： 精神下進行各種修飾與變更。 在不W本發明之 =外，須注意的-點是’該些圖式均為簡化之示咅 二本sr示意方式說明本發明之基本架構，因此僅顯示 數目關之構成，且所顯示之構成並非以實際實施時 丈目、形狀、及尺寸比例繪製，其實際實施時之數目、 可例為一種選擇性之設計’且其構成佈局形態 請參閲第1圖，係顯示本發明之較 ::治具及所應用之記憶體之分解示意圖。如圖所;Γ 憶體測試治具W應用於輔助例如示波器之測量 !: 2示記憶體2之電性測量，該記憶體測試 1匕括.弟一連接部u、第二連接部12以及測量部 二。=的是，雖於本實施例中該記憶體2係可為例如Line Memory Modules · nTMun ^ Board or motherboard. The external device is printed = ground. The first connecting portion is a plurality of conductive structures, and the plurality of conductive structures are inserted. Structure. The smuggling month consists of the second conductive 18788 (amendment) 7 1278639 , , , . The structure consists of a hard number of metal conductive sheets. In the measurement unit, the measurement unit has a plurality of measurements, and the m is arranged in a row in the measurement unit:: and the measurement unit is 5 humans < on the body, and the measurement unit can be a dependent pin. These metal pins can be numbered. The invention provides a memorable device such as a connector, and the memory test fixture is designed to be connected to the electrical connection end of the memory and the electrical connection of the memory. The end slots and the two are electrically accurate __ electrical measurements. And: electricity: = can = technology t is limited to the shortcomings of the joint operation and the welding technology caused by the interference and measurement errors, etc., not a memory 28 a connection technology, provide a safe and convenient memory test ^ =:: Power-on, power-off, and plugging and unplugging the memory, etc., when the Gula is in use, the measurement unit exports the internal lines of the memory, so it is possible to directly measure the electrical properties of the memory, such as an oscilloscope, and lead. Extremely short 'to minimize external interference with the signal. In addition, the memory device of the present invention is pluggable and can be reused many times, which also reduces the cost of measuring the electrical properties of the memory by the prior art, and provides relative convenience and provides better usability. The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure of the present disclosure.纟 发明 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 In addition, it should be noted that the points are 'simplified'. The two schematics illustrate the basic structure of the present invention, so only the number of components is shown, and the displayed composition is not actually implemented. When the size, shape, and size ratio are drawn, the number of actual implementations can be exemplified by a selective design, and the layout of the structure is shown in Fig. 1, which shows the comparison of the present invention: A schematic diagram of the decomposition of the applied memory. As shown in the figure; Γ The memory test fixture W is used to assist the measurement of, for example, an oscilloscope!: 2 shows the electrical measurement of the memory 2, the memory test 1 The portion u, the second connecting portion 12, and the measuring portion 2. If the memory 2 in the present embodiment can be, for example,
In-Line Mem〇ryM〇dules；DIMM) 之4體，亚且具有由複數個金屬導電片所構成之雷㈣ 接端2卜但所屬技術領域中具有通常知識者皆可了解二 其他實施例中，該記憶體2亦可為其它類型之記 、 並非=此限制本發明之應用範圍。同時，由於例^示波哭 之測量儀器以及記憶體等之結構與作用原理均屬習知者， 故於此不再多作說明。 該第-連接部11具有用以與待測之記憶體2的電性 連接端21電性連接之第—導電結構lu。於本實施例中， 18788(修正本) 9 1278639 j弟一連接部11係為形成有一插槽之結構，且該插槽係可 k擇地與習知電路板上對應於記憶體2之插槽（均未圖示） ^結構相同’而該插槽之開口尺寸則係略大於該電性連接 = 之厚度，以便令該電性連接端21插入例如為插槽之 弟一連接部u，而使該記憶體2與該記憶體測試治具工電 \連接該第一導電結構lu係可由複數金屬導電片所構 =，以設於該第一連接部u之插槽内，俾於測量時與該記 L體2之電性連接端21對應地電性連接，以傳導進出 憶體2之電性信號。 立應/主思的是，雖本實施例中係對可設於電路板上之記 憶體進行測量，但並非以此限制本發明之記憶體測試治° 具’且由於電路板之結構與作用原理均屬習知者，故於此 不再為文贅述。 此外，習知之記憶體2可於設有該電性連接端21之 -=置具有防止記憶體插反之凹部22，為配合該記憶體 =有之'凹部22,該第一連接部11復可選擇設有對應該凹 :…之：隔架112。該分隔架112係將該第-導電結構111 :為兩‘刀’以避免記憶體2插反，藉此而達到防 用0 以士 連接部12係具有與該第—連接部11之第一導 =籌u電性連接之第二導電結構121，用 電路板3之外部裝置上所設之插槽3〇。於本實施中 ::=121係可由對應於該第一導電結構iu之複數 個孟屬¥電片所構成’且該第二導電結構⑵可與電路板 18788(修正本) 10 1278639 ^之插槽内的線路（未圖示）相對應，以於測量時藉之使本 -發明之記憶體測試治具丨與電路板3電性連接。同時，★亥 第二導電結構121與前述第一導電結構之電性連接可 使電流信號經由該第二連接部丨2以及該第—連接部11而 在該記憶體2與該電路板3之間傳遞。應注意的是，於其 他貫施例中，該第一連接部11以及第二連接部12間之電 .性連接亦可透過諸如導線連接或其他等效元件，而非以本 實施例中所述之由該第一導電結構U1以及第二 Ί21狀電性連接者為限。 、焉 該測量部13係與該第一連接部u及第二連接部12 結合’並與該第一連接部n之第一導電結構以及該第 ,連接部12之第二導電結構121對應電性連接，以與例如 不波益之測量儀器之測量探頭（未圖示）電性連接，俾在 記憶體2插置於該記憶體測試治具i之第一連接部u上 後，藉之對該記憶體2進行例如信號完整性（^抑^ 籲加e g r i t y ;⑴之測量。於本實施射，該測量部13係包 .括複數個金屬引腳以作為測試單元，該等金屬引腳之一端 可分別與該第一導電結構⑴以及該第二導電結構121電 性連接，另一端則外露於該記憶體測試治具1;換古之， 該等金屬引腳（即，該测量部13)係為雙面設置者，分別 可對應該記憶體2之電性連接端21之各金屬導電片，以供 如示波器之測量儀器進行電性測量，藉此便可輕易地完 成對該記憶體2之信號完整性測量。 應了解的是，雖本實施例中之測量部13為單列金屬 18788(修正本) 11 1278639 丨列方式’但所屬技術領域中具有通常知識者皆 虽本發日㈣期於記憶體之電 電片）分佈較爲宓隹去,士十 接而IP至屬¥ 屬引腳之間距增大，以在測量時 示、古更地t出需要測量之線路，並藉此避免測量時例如 二量儀器的測量探頭不慎與其它金屬 造成測量結果的錯誤。 叩 第3^:-设可令該測量部13之金屬引腳設有編號（如 =戶:不)、’如此即可更快速地根據編號進行測量，而 干性找、’於第3圖中所示之編號方式係為例 月者’亚非以此限制本發明，而可加以修改及變化， i 術領域中具有通常知識者易於思及者，故不 再針對其他修改及變化例進行說明。 波哭㈣可採用較硬之材質製成，以便於例如示 於本實施例心:一接附加的引腳’而㈣限 測=於:知” ’本發明係設計諸如轉接頭之記憶體 端，第%技用弟一連接部連接待測記憶體之電性連揍 二連接習知電路板上之用於配合待測記憶體 == 藉由包括例如複數金屬引腳之測量部與 该弟-連接部之第一導電結構以及該第二連接 — 導電結構進行電性連接，並且使該 一 揞驊、、目I丨4 ▲曰 里I局°卩外路於該記 L、體物口具，即可透過例如示波器之測量儀器直接測量 18788(修正本) 12 1278639 玄/貝】里4對^己體進行測量，而不需如習知技術逐一找出 •，待測信號線、對應之金屬引腳與金手指、及適當之焊接點。 故’應用本發明可快速、準確地對記憶體進行電性測量。 同時’由於本發明之設計係對應該記憶體之電性連結 而口又置該第一連接部，因此一次就可以測量所有記憶體信 號不必重複插拔，不僅相對於習知技術節省大量時間， ，藉此k同工作效率，並可避免習知技術中之記憶體因多次 ，鲁^複插拔或重複開關機所造成的損壞，提供安全方便之記 體測试治具。而且，由於該測量部（即，金屬引腳）可 以很短，相對可避免習知技術因焊接較長之金屬引腳所引 起的測量誤差。 it匕外 、L過對該測量部之分排及綱現寻設計，可方便 !·夬，地找到待測之金屬引腳，進而亦可節省時間。而且， =明之記憶體測試治具係可重複使用，俾大幅減少測量 i:::性之成本。另外’應用本發明無需對記憶體或者 電路板進料接可省略焊接之㈣及成本， e己憶體損壞、以及避免進行繁續 L 、麵作，更可確保記 匕體女全、大幅地提高工作效率、且使用上 *上述實施例僅為例示性說明本發明之原理及3。 而非用於限制本發明。任何所屬技術領域^ 知識者均可在不違f本發明之精神及範 ，、有^ 例進行修飾與變化。因此，本發明之權二:二述實施 後述之申請專利範圍所列。 …已圍，應如 【圖式簡單說明】 18788(修正本） 13 1278639 第1圖係為本發明之較佳實施例的記憶體測試治具及 所應用之記憶體之分解不意圖， 第2圖係為第1圖之記憶體測試治具之變化例之示意 圖；以及 第3圖係為第2圖之測量部之變化例之示意圖。 【主要元件符號說明】 1 記憶體測試治具 11 第一連接部 111 第一導電結構 112 分隔架 12 第二連接部 121 第二導電結構 13 測量部 2 記憶體 21 電性連接端 22 凹部 3 電路板 30 插槽 14 18788(修正本)In-Line Mem〇ryM〇dules; DIMM) 4 body, and has a plurality of metal conductive sheets formed by a thirteen (four) terminal 2, but those of ordinary skill in the art can understand that in other embodiments The memory 2 can also be of other types, and is not intended to limit the scope of application of the present invention. At the same time, since the structure and function principle of the measuring instrument and the memory of the crying crying are all well-known, no further explanation will be given here. The first connecting portion 11 has a first conductive structure lu for electrically connecting to the electrical connection end 21 of the memory 2 to be tested. In the present embodiment, 18788 (Revised) 9 1278639, a connecting portion 11 is formed into a structure having a slot, and the slot is selectively associated with the insertion of the memory 2 on the conventional circuit board. The slot (none of which is shown) has the same structure and the opening size of the slot is slightly larger than the thickness of the electrical connection, so that the electrical connector 21 is inserted into the connector u, for example, a slot. And the memory 2 is connected to the memory test fixture. The first conductive structure lu can be configured by a plurality of metal conductive sheets to be disposed in the slot of the first connecting portion u. It is electrically connected to the electrical connection end 21 of the L-body 2 to conduct electrical signals into and out of the memory 2. It should be noted that although the memory of the memory that can be disposed on the circuit board is measured in this embodiment, it does not limit the memory test device of the present invention and because of the structure and function of the circuit board. The principles are all well-known, so this is no longer a text. In addition, the conventional memory 2 can be provided with the electrical connection end 21 and has a memory block for preventing the insertion of the recess 22, in order to cooperate with the memory=there is a recess 22, the first connection portion 11 can be reconfigured. The selection has a corresponding concave: ...: the partition 112. The spacer 112 is a first conductive structure 111: two 'knife' to prevent the memory 2 from being inserted backward, thereby achieving the anti-use 0. The connection portion 12 of the taxi has the first connection with the first connection portion 11. The second conductive structure 121 electrically connected is connected to the slot 3 provided on the external device of the circuit board 3. In the present embodiment::=121 may be formed by a plurality of singularity pieces corresponding to the first conductive structure iu' and the second conductive structure (2) may be interposed with the circuit board 18788 (Revised) 10 1278639 ^ The lines (not shown) in the slots correspond to each other for electrically connecting the memory test fixture of the present invention to the circuit board 3 during measurement. At the same time, the electrical connection between the second conductive structure 121 and the first conductive structure allows the current signal to pass through the second connecting portion 以及2 and the first connecting portion 11 in the memory 2 and the circuit board 3. Pass between. It should be noted that in other embodiments, the electrical connection between the first connecting portion 11 and the second connecting portion 12 may also be through a wire connection or other equivalent component instead of the present embodiment. It is limited to the first conductive structure U1 and the second 21-shaped electrical connector. The measuring unit 13 is coupled to the first connecting portion u and the second connecting portion 12 and corresponds to the first conductive structure of the first connecting portion n and the second conductive structure 121 of the first connecting portion 12 The connection is electrically connected to a measuring probe (not shown) of a measuring instrument such as a non-boom, and after the memory 2 is inserted into the first connecting portion u of the memory test fixture i, The memory 2 is subjected to, for example, signal integrity (^), and the measurement of (1). In the present embodiment, the measuring unit 13 includes a plurality of metal pins as test cells, and the metal pins are included. One end is electrically connected to the first conductive structure (1) and the second conductive structure 121, and the other end is exposed to the memory test fixture 1; in other words, the metal pins (ie, the measuring part) 13) The two-sided setter can respectively correspond to the metal conductive sheets of the electrical connection end 21 of the memory 2 for electrical measurement by an oscilloscope measuring instrument, thereby easily completing the memory. Signal integrity measurement of body 2. It should be understood that although this implementation In the example, the measuring unit 13 is a single row of metal 18788 (amendment) 11 1278639 丨 方式 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The tenth connection and the IP to the genus are increased in the distance between the pins, so as to show the line to be measured during the measurement, and to avoid the measurement probes such as the two instruments inadvertently with other metals during the measurement. Causes errors in measurement results.叩3^:- setting allows the metal lead of the measuring unit 13 to be numbered (eg = household: no), 'so that it can be measured more quickly according to the number, and dry looking, 'in Figure 3 The numbering method shown in the figure is for the example of the month, and the invention is limited to the present invention, and can be modified and changed. Those who have ordinary knowledge in the field of i can easily think about it, and therefore no longer carry out other modifications and variations. Description. Wave crying (4) can be made of a harder material, so as to be shown, for example, in the center of the present embodiment: an additional pin 'and (4) limit measurement =: know" 'The invention is designed to be a memory such as a connector The first part of the connection is connected to the electrical connection of the memory to be tested. The second connection is connected to the memory on the conventional circuit board for matching the memory to be tested == by a measuring unit including, for example, a plurality of metal pins. The first conductive structure of the connection portion and the second connection-conductive structure are electrically connected, and the one-way, the target I 丨 4 ▲ 曰 I I 卩 卩 于 于 、 、 For the mouthpiece, you can directly measure the measurement of the 18788 (Revised) 12 1278639 Xuan/Bai by means of an oscilloscope measuring instrument, without having to find out one by one as in the conventional technology. Corresponding metal pins and gold fingers, and appropriate solder joints. Therefore, the application of the present invention can quickly and accurately measure the electrical properties of the memory. Meanwhile, the design of the present invention corresponds to the electrical connection of the memory. The first connection is placed again, so that the measurement can be performed at one time. There is no need to repeatedly insert and remove the memory signal, which not only saves a lot of time compared with the prior art, thereby taking advantage of the work efficiency, and avoiding the memory in the prior art due to multiple times, the plugging or repeating switching machine The damage is provided, and the safe and convenient recording test fixture is provided. Moreover, since the measuring part (ie, the metal pin) can be short, the measurement caused by the soldering of the long metal pin can be avoided. Error. It is outside, L is the design and layout of the measurement department, it is convenient! · 夬, find the metal pin to be tested, which can save time. Moreover, = memory test The system can be reused, which greatly reduces the cost of measuring i:::. In addition, the application of the invention does not require the feeding of the memory or the circuit board to omit the welding (4) and the cost, the damage of the e-memory, and avoidance The continuation of the L, the face, and more to ensure the integrity of the work, greatly improve the work efficiency, and the use of the above embodiments are merely illustrative of the principles and principles of the present invention. Technology Fields ^ Knowledge can be modified and changed without departing from the spirit and scope of the present invention. Therefore, the second aspect of the present invention is described in the scope of the patent application described below. [Brief Description] 18788 (Revised) 13 1278639 FIG. 1 is a schematic diagram of the memory test fixture and the memory of the applied memory of the preferred embodiment of the present invention, and FIG. 2 is the first A schematic diagram of a variation of the memory test fixture of the figure; and Fig. 3 is a schematic diagram of a variation of the measurement section of Fig. 2. [Explanation of main component symbols] 1 Memory test fixture 11 First connection part 111 A conductive structure 112 spacer 12 second connection portion 121 second conductive structure 13 measurement portion 2 memory 21 electrical connection end 22 recess 3 circuit board 30 slot 14 18788 (amendment)