TWI277191B - Method for manufacturing leadless package substrate - Google Patents

Abstract

A method for manufacturing a leadless package substrate is disclosed. The disclosed method applies a conductive layer of the top surface of a substrate, that of the bottom surface of a substrate, and that of the inner surface of through holes as an electrically conductive path and forms electrical pads on the top surface, and the bottom surface of the substrate individually through plating. The method is proceeded by forming patterned circuit on the top surface of a substrate; plating to form electrical pads on both the top surface, and the bottom surface of the substrate, and forming patterned circuit on the bottom substrate through lithography. The disclosed method can increase the layout area of the circuit, improving the electrical quality of the connection between the chip and the package substrate, or between the circuit board and the package substrate, simplify the manufacturing steps, and further reduce the manufacturing cost.

Description

1277191 〜 * Λ « , ninth invention, the invention relates to a method for fabricating a package substrate, and more particularly to a method for fabricating a package substrate suitable for an electroless plating. [Prior Art] -

10 15

As electronic products become lighter, thinner, smaller, more versatile, etc., and at the same time, the development of integrated circuit chip packaging technology has been promoted, which has led to the wafer package being multi-legged, thinned, and miniaturized, even Technology such as leadless mounting. In order to respond to the trend of thinness and shortness and to pursue high density of packaging, current Ball Array Array, cMp Scale Package, and Flip Chip technology have become mainstream technologies for packaging. Therefore, the demand for small area, 1/0 pin improvement, wiring densification, low noise, product reliability, and even manufacturing cost has become an important issue in the manufacture of package substrates. The manufacturing process of the package substrate generally requires forming a dense road pattern on the surface of the substrate for transmitting an electronic signal or a power source. At present, the copper wire is used as the circuit wiring in the industry. Therefore, the (10) contact of the circuit wiring is ^=recording/gold layer, which can prevent the copper wire from being oxidized, in order to maintain the electrical quality of the 1/〇 connection. The metallurgical property between the package substrate and the wafer can be improved. In addition, the substrate surface material - solder resist layer (W delete k) to protect the circuit pattern formed on the surface of the substrate. The traditional package substrate process is preceded by the substrate on which the circuit has been formed. | 20 1277191 Covered with: solder resist material and then electroplated to form a nickel/gold layer. Therefore, the area not covered by the solder resist material (usually: [/〇 contact point) needs to extend to the periphery of the substrate by the surface lead circuit to form a current conduction path, so that nickel plating can be performed at the 1/0 contact point. The process of gold. 5 is a schematic cross-sectional view of a conventional package substrate having an electroplated wire. In order to form the nickel/gold layer 13 at the I/O contact 12 on the surface of the substrate 1, the circuit layer 10 on the upper surface needs to be provided with a plurality of electroplated wires u to transfer current to the I/O contact 12 for performing. Electroplating process of nickel/gold layer 13. However, the plated wire u extended by the electroplated nickel/gold layer 13 occupies the space of the wiring 10 on the surface of the substrate, and thus the wiring density of the substrate circuit cannot be improved. In addition, signal interference between adjacent electric boat wires can cause problems with noise. In order to solve the shortcomings of the above-mentioned electroplated wires, many research teams have developed electroplated nickel/gold processes for electroless wires. Referring to FIG. 2a to FIG. 2d, FIG. 2 is a schematic diagram of a process of a conventional electroless-plated wire package substrate, which is generally referred to as a GPP (g〇ld pattern plating) plating process. As shown in FIG. 2a, a complete conductive layer 21 is formed on the upper surface of the substrate 2, and then a patterned photoresist layer 22 is covered on the surface of the conductive layer 21 to expose the circuit wiring to be formed on the surface of the substrate 2. Next, as shown in Fig. ,, a nickel/gold layer 23 is electroplated on the surface of the exposed conductive layer 21. Finally, referring to FIG. 2c and FIG. 2d, after the photoresist layer 22 is patterned and etched, the conductive layer 21 under the protective layer 23 is protected by the metal protective layer 23 to complete the patterned circuit on the upper and lower surfaces of the substrate 2. To form a wiring layer 24. Although the GPP plating process does not require an additional plating wire, the wiring layer 24 on the surface of the substrate 2 is entirely covered with a nickel/gold layer 23. This process 1277111 not only consumes too much nickel/gold material, but only the surface circuit layer 24 is covered with a nickel/gold layer 23'. The sides of the circuit layer 24 are still exposed and are not protected, so that it is prone to line oxidation or wire bonding. A situation in which the electrical coupling between the wafer and the substrate is poor. Furthermore, due to the difference in material properties, it is easy to cause the surface of the substrate to be covered. The 5 solder layer is not easily adhered to the nickel/gold material on the surface of the circuit, which will affect the reliability and service life of the product. In addition, the electroplated nickel/gold process of the electroless plating wire utilizes a copper layer on the surface of the substrate and the surface of the plated via hole as a current conduction path, and is plated to form a nickel/gold layer on the upper surface of the substrate. However, in such a process, the nickel/gold layer on the upper surface 10 and the lower surface of the substrate is not formed at the same time, and is mainly formed by first plating a nickel/gold layer on the patterned circuit on the upper surface, and then forming on the lower surface of the substrate. The circuit layer is then covered with a solder mask, and finally the nickel/gold layer of the lower substrate is formed by electroless plating. Although this method does not consume too much nickel/gold material, and the substrate surface does not need to be separately provided with a plating wire, the complicated and complicated process step 15 not only increases the manufacturing cost but also prolongs the process time. Therefore, there is a need for a method for fabricating an electroless-plated wire package substrate, which can increase the wiring area of the circuit wires, and can provide a good electrical connection quality between the wafer and the package substrate, or between the package substrate and the circuit board; The key nickel/gold process is used to shorten the process time and reduce the production to 20 copies. SUMMARY OF THE INVENTION The present invention relates to a method for fabricating an electroless-plated wire package substrate, which mainly utilizes a metal layer formed on the upper surface and the lower surface of the substrate and electroplated to turn on the inner surface of the hole 1271191 as a current conduction path. An electroplating process is performed and an electrical connection pad is simultaneously formed on the lower surface of the substrate. Wherein, the method for fabricating the electroless wire-bonding substrate of the present invention is to form an upper surface circuit, and then to form an electrical connection between the upper and lower surfaces by the electric money, and finally to form a lower surface circuit by using a patterning process 5 x etching method, that is, complete The process of the electroless wire-bonding substrate of the invention. The present invention provides a method for fabricating an electroless-plated wire package substrate, comprising: step (a) providing a substrate having an upper surface and a lower surface, and the substrate includes a plurality of conductive layers extending through the upper surface and the lower surface of the substrate 10 holes; (b) forming a continuous metal layer on the upper surface and the lower surface of the substrate, and the inner surface of the via; (4) patterning the metal layer on the upper surface of the substrate to form a circuit layer on the upper surface; (4) forming a pattern The first layer is formed on the upper surface and the lower surface of the substrate to reveal a metal layer of a portion of the upper surface and a portion of the metal layer of the lower surface; (4) a metal layer of the tantalum or a metal layer of the metal protective layer exposed on the upper surface a surface of the metal layer exposed on the surface and the lower surface; (1) removing the first resist layer, (g) forming a patterned second resist layer on the upper surface and the lower surface of the substrate '(9) patterning the metal exposed on the lower surface a layer to form a circuit layer of the lower surface = a second barrier layer is removed; and (1) a patterned solder resist layer, a metal protective layer on the upper surface of the chrome and a metal protective layer on the lower surface. 2〇θ In the manufacturing method of the electroless-plated wire package substrate of the present invention, the second resist layer completely covers the metal layer of the upper surface and the metal protective layer, and completely covers the electrical connection layer of the lower surface, and exposes the lower surface. Part of the metal layer is used to process the subsequent lower surface patterned circuit. Therefore, the method for fabricating the electroless-plated wire package substrate of the present invention can increase the number of 1271191 pieces and the package substrate, and the quality can also simplify the circuit wiring area of the surface of the substrate, and can provide good electrical power between the chip g-seal substrate and the circuit board. Sexual connection quality

Process to shorten process time and reduce production costs. Therefore, the electroless wire package substrate can have a good product life of five. The method for fabricating the electroless wire-bonding substrate of the present invention can mainly provide a current required for forming the electrical connection layer of the upper and lower surfaces by the upper surface and the lower surface of the substrate, and the metal layer and the second conductive path of the inner surface of the plated via hole. At the same time, the electroplating process is performed on the upper and lower surfaces. Therefore, the manufacturing method of the package 10 substrate of the present invention does not need to additionally provide a plating wire on the surface of the substrate, which not only can greatly increase the wiring area of the substrate circuit, but also can effectively avoid the noise interference caused by the plating of the conventional substrate. In addition, the electrical connection layer of the present invention can be mainly used to transmit an electronic signal or a power source. Therefore, the metal protection layer is a plurality of electrical connection pads for electrically coupling the crystal 15 and the package substrate, or the package substrate and the circuit board. For electrical coupling. The type of the electrical connection pad described herein is not limited, and is preferably a wire bonding pad (Finger), a package substrate and a circuit for electrically bonding the wire-type semiconductor package substrate and the wafer. Contact pad or land for electrical coupling, or a combination thereof. Further, the material suitable for the electrical connection layer of the present invention is not limited, and is preferably a metal material which is resistant to environmental influences and is not easily oxidized, and more preferably may be gold, nickel, handle, silver, tin, nickel/ , chrome / niobium, nickel / gold, handle / gold, nickel / handle / gold, or a combination thereof, preferably nickel / gold (first nickel and then gold). Therefore, in addition to facilitating the electrical connection between the electrical connection of the wire-bonding package substrate and the gold 1271191 line, the electrical connection pad of the present invention can also reduce the problem of oxidation of the electrical connection pad caused by the external environment, thereby improving the bump and the pre-preg. The electrical quality of conductive components such as solder, solder balls, or gold wires implanted in electrical pads. Further, the material used for the metal layer of the present invention may preferably be a copper metal material. In the method for fabricating the electroless plating package substrate, the process for forming the conductive layer is not limited, and preferably electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, sputtering, or a combination thereof is preferably used. Electroplating can be used. In the method for fabricating the electroless wire-bonding substrate of the present invention, the substrate provided in the step (a) 10 may be a surface to form a substrate of a seed layer (not shown) to facilitate formation of a subsequent metal layer. The seed layer may be a conductive material, and the conductive material may be at least one material selected from the group consisting of copper, tin, nickel, chromium, and titanium. The method for fabricating the electroless wire-bonding substrate of the present invention can be applied to any of 15 kinds of package substrates, preferably a wire bonding package substrate. The substrate structure to which the present invention is applicable may be a single-layer circuit board, or may be a two-layer board or a multi-layer circuit board that has completed the front-end line process. In addition, the insulating material to which the substrate of the present invention is applied is not limited, and preferably one of 20 groups of organic thin film dielectric materials or liquid organic resin materials; the above material may be selected from ABF (Ajinomoto Build-up Film) ), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), Pl (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine) ), fragrant nylon (Aramide), etc., or non-1277191 (photosensitive organic resin, or may be mixed with epoxy resin and glass fiber, etc.), and the resist layer used in the present invention may be a conventional lithography process. Preferably, the resist material is a photo-sensitive material, and the photo-sensitive material may be selected from the group consisting of a dry film and a liquid photoresist. The formation of the intermediate resist layer is not limited, and may preferably be printed, spin coated, bonded, chemically deposited, physically deposited, or the like. • The method for fabricating the electroless wire-bonding substrate of the present invention is formed after the upper surface wiring layer is formed. The upper surface and the entire copper surface of the inner surface of the plated via are used as a current conduction path, and the electrical connection pads of the upper and lower surfaces are simultaneously formed by electroplating, and finally the lower surface circuit is formed by etching by a patterning process, that is, The process of the electroless-plated wire package substrate is completed. Thus, the fabrication method of the present invention can meet the requirements of the "fine pitch package" (finepitchb〇nding 2) to fabricate a package substrate for the deuterated circuit wiring. The manufacturing method of the package substrate not only simplifies the manufacturing process and the process of shortening the process time, but also reduces the manufacturing cost and improves the yield of the π port to increase the market competitiveness of the product. [Embodiment] Referring to FIG. 3, FIG. 3(a) to FIG. 3(1) are the first embodiment of the present invention-preferred embodiment of the present invention without a key conductor (the fourth), and the second substrate, as shown in FIG. And the lower surface of the substrate 3 is white C copper 4 31 ' to form a core substrate structure. Next, using Ray 20 1277191

: A shot or mechanical drilling technique forms a plurality of vias 32 in the substrate 3 to provide a substrate structure as shown in Figure 3(b). Before electroplating to form a metal layer 33 on the lower surface of the substrate 3 and the inner surface of the via hole 32, a thin thin seed crystal 5 layer (not shown) is formed on the upper surface of the substrate and the via hole by electroless plating. The inner surface of 32 is used to facilitate subsequent deposition of a structurally complete copper metal layer 33. As shown in Fig. 3(c), an electroplated copper metal layer 33 is formed on the surface of the substrate 3 and the inner surface of the via hole 32, and the metal layer 33 serves as a current conduction path required for the subsequent plating of the metal protective layer 33. Next, an insulating resin is filled in the plating via 334 to provide a substrate structure as shown in Fig. 3(d). As shown in FIG. 3(e), a patterned etching process is used to form a patterned metal layer 33 on the upper surface of the substrate to provide a line layout on the upper surface; and in the circuit layer formed on the upper surface, The surface of the surface to be formed with a metal protective layer needs to be electrically connected to the electric ore via 334 for the subsequent electro-mineral 15 / gold process.

After the top surface of the substrate 3 is finished, the first and second resistive layers 34 are formed on the upper surface and the lower surface of the substrate, and the first resist layer 34 is patterned by a patterning process to reveal A portion of the upper surface of the metal layer is straight φ / the metal layer 33 of the lower surface of the knife. The above substrate structure is shown in Fig. 3 (1), and the metal layer exposed on the lower surface is moved as a subsequent electro-suspension protection shoulder 35. As shown in Fig. 3(g), the metal protective layer on the upper and lower surfaces of the upper and lower surfaces is formed by electroplating at the same time as the conductive layer 33 which is electrically exposed on the lower surface of the substrate 3 and the plated via 32. The metal formed on the upper and lower surfaces of this example 12 1277191

The ruthenium layer 35 is a recording/gold material. The substrate structure shown in Fig. 3(h).

Subsequently, the first resist layer 34 is removed, that is, the second resist layer is then covered, and then the upper surface and the lower surface of the substrate 3 are covered, and a patterning process is used to form a second resist layer 35 having a pattern. . Referring to the structure shown in the circle 3 (1), the second resist layer % completely covers the metal layer 33 of the upper surface and the metal protective layer 35, and the second resist layer % completely covers the metal protective layer 35 of the lower surface, and is revealed. The metal layer 33 of the lower surface portion is taken out. Finally, as shown in Fig. 3(1) and Fig. 3, the metal layer 33 exposed on the lower surface is patterned and the second resist layer 36 is removed, that is, the wiring of the lower surface of the substrate 3 is completed. As shown in FIG. 3 (1), in the route of the upper surface of the substrate 3 of the present embodiment, the metal protection layer 35 covers a plurality of first electrical connection pads 331 electrically conductive with the plating vias, and The electrical connection pads are used as pads for electrically coupling the wafer (not shown) and the package substrate 3 when they are wired. In the way of the lower surface of the substrate 3 of the embodiment of the present invention, the metal protective layer is covered by the second plating. The second electrical connection pad electrically conductive, for example, and the surface of the third electrical connection pad 333, which is not electrically conductive, and the electrical connection pads are used as the package substrate 3 and the circuit board (not shown) Solder ball mat for electrical coupling. The third electrical connection pad 333 can be an electrically independent electrical connection pad. In order to protect the copper wire circuit on the upper and lower surfaces of the substrate 3, the final step of the manufacturing method of the present embodiment is to apply a solder resist layer 37 such as green paint or black lacquer material to the surface of the substrate on which the circuit wiring has been completed, and then proceed. The material solder resist layer 37 is patterned to expose the metal protective layer 35 on the upper surface and the metal protective layer 35 on the lower surface. </ RTI> 13 25 1277191 In addition to the electrical contact pads described in this embodiment, the substrate 3 is subjected to an electro-mineral nickel/gold process portion, and the structure of the electroplated nickel/gold can be formed by the method disclosed in the present invention. In summary, the method for fabricating the electroless wire-bonding substrate of the present invention does not simplify the process steps, that is, shortens the time required for the process, reduces the manufacturing cost, and improves the product yield, thereby increasing the market competitiveness of the product. Furthermore, in addition to increasing the wiring area of the circuit traces of the substrate, the method of the present invention does not need to be plated with a nickel/gold layer on the surface of the entire circuit layer, which can greatly reduce the cost of electroplating nickel/gold, and can also provide a wafer. Good electrical connection quality with the package substrate, or the package substrate 1 and the board, eliminating the need for wire oxidation. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited to the scope of the claims. 15 20 1277191 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a package substrate having a plated wire. 2(a) to 2(d) are schematic views showing the process of a conventional package substrate of an electroless plating wire. 5 (Fig. 3 (1) is a schematic diagram of a process for a package substrate of an electroless wire according to a preferred embodiment of the present invention. 1 〇 [Main component symbol description] 1 substrate 12 17 〇 contact 21 conductive layer 24 circuit layer 32 via hole 35 electrical connection layer 334 plating via hole 333 third electrical connection pad

10 circuit layer 11 electric ore wire 2 substrate 23 nickel/gold layer 31 copper foil 13 recording / gold layer 22 photoresist layer 3 substrate 33 metal layer 34 first resistance layer 36 second resistance layer 37 solder mask layer ^ electrical connection 332 second electrical connection 塾 15

Claims (1)

1277191 X. Patent application scope: 1. A method for manufacturing a package substrate without an electroplated wire, comprising the following steps: () ki, a substrate having an upper surface and a lower surface, and the substrate includes a plurality of upper surfaces penetrating the substrate and a via hole on the lower surface; (b) forming a continuous metal layer on the upper surface and the lower surface of the substrate, and inner surfaces of the via holes; (4) patterning a metal layer on the upper surface of the substrate to form an upper surface line 10 (d) forming a patterned first and lower surface to expose a portion of the upper surface of the metal layer; a resist layer on the surface of the upper substrate and a portion of the lower surface 15 (4) of the ore formation - a metal protective layer on the surface of the upper surface and the surface of the metal layer exposed by the lower surface; (0 removing the first resistive layer; exposed metal layer 第 patterning the 20th and lower surfaces, wherein the second resistive layer is completely;; and the metal protective layer, the second resistive layer is completely; the metal clad layer of the surface and revealing a portion of the lower surface of the gold layer: The surface of the gold eyebrow line Γ patterning the metal layer exposed on the lower surface to form the lower core (1) to remove the first resist layer; and 16 1277191 15 20 " 2. The method of claim i, Wherein the step (4) is to conduct electricity by the metal layer of the inner face plate, the cloth surface of the electric mine, and the metal surface of the underarm surface to carry out electric money. 3. As described in claim 1 The method includes a plurality of electrical connection pads. 4. The method of claim 2, wherein the interface is a wire bonding pad. - 5 · The method of claim 2 The pad is a solder ball pad. 6. As described in the scope of the patent application, the first layer is a metal material, and the metal material is gold, nickel, Syrian, silver, her, chromium / Titanium, record / gold, he / gold, / gold, or a combination thereof. 7 · If the scope of the patent application is passed ^ ^ ^ The method of β迩, wherein the substrate of the step (a) is a substrate having a seed layer on the surface. 8· The method of the reindeer® Tingjiang method according to item 7 of the patent application scope, wherein the seed layer The ceremony, the piece, the η ^ ^ , and the tenth line are at least one material selected from the group consisting of copper, tin, nickel, and titanium. 9. The method of the second aspect of the patent application is - the method of copper metal I, Wherein the metal layer ίο. is a single-layer circuit board according to the scope of the patent application. The method of the substrate is 11. The multilayer circuit board according to the scope of the patent application. The method of claim i, wherein the resist layer is wherein the electrical connection is electrically connected to the metal protection 17 1277191 as a photosensitive material, and the photosensitive material is The method is at least one selected from the group consisting of a dry film and a liquid photoresist. The method of claim 1, wherein the formation of the resist layer is by printing, spin coating, and pasting. Combination, chemical deposition, or physical sinking 18