TWI276105B - P channel non-volatile memory and operating method thereof - Google Patents

Abstract

A P channel non-volatile memory is described. The P channel non-volatile memory includes a substrate, a first memory cell, and a second memory cell. An N-well is disposed on the substrate, and the first cell and the second cell are disposed on the N-well. The first cell includes a first gate, a first charge storage structure, a first doped region, and a second doped region. The first gate is disposed on the substrate. The first charge storage structure is disposed between the first gate and the substrate. The first doped region and the second doped region are disposed in the substrate on the both sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The second gate is disposed on the substrate. The second charge storage structure is disposed between the second gate and the substrate. The third doped region and the second doped region are disposed in the substrate on the both sides of the second gate. The second cell and the first cell share the second doped region.

Description

1276105 17870twf.doc/r IX. Description of the Invention: [Technical Field] The present invention relates to a brother and a method of operating the same, and particularly to a P-channel non-volatile memory and method of operating the same . [Prior Art]

The electrically erasable and programmable read-only memory (EEPROM) in non-volatile memory can perform multiple data storage, reading, erasing, etc., and the stored data is not after power-off. The function that will disappear, and the advantages of fast access speed, high light weight capacity, small access device size, etc., has become a memory component widely used in personal computers and electronic devices. A typical electrically erasable and programmable read-only memory system fabricates a floating gate and a control gate with doped polysilicon. Later, in order to avoid the typical erasable and programmable read-only memory, when erasing, the over-erased county appears, leading to misjudgment of data. Therefore, in the control gate and floating _ sidewall, the base is additionally provided with a selective gate (4) (10) (3) made of doped polycrystalline stone, that is, the side of the control gate and the floating side wall are set _ Select the transistor. Conventional technology also uses a ctoge trapping layer instead of a polycrystalline material to place a gate. The material of the charge storage structure is, for example, a nitride nitride; the nitrogen-cut charge storage structure usually has a layer-oxidation Shi Xi' and the formation of oxidized stone eve / nitrite eve / oxidized stone eve (〇秦咖咖·^ ΟΝΟ) #夂5 layer. Such components are commonly referred to as Shi Xi/Oxide/Strontium (S0N0S) components. ^. And: lx SQNQS memory components are mostly N-channel non-wing 1276105 17870twf.doc / r Memory channel current is small, energy utilization is very poor, only one electron, only one electron injection. Therefore, in the field of low-consumption tweezers, such _channel non-volatile two; =; is quite limited. In addition, if the element "22 crystal" in the memory cell is bound to increase the size of the component, and the obstacle is developed toward the mtegragrity [invention] 7 (four) ^, the purpose of the present invention is to provide - Volatile memory and its operation method, ^ ^ ^ fast, and the difficulty of tree height, Wei _ consumption, operating speed body and Ρ type channel non-volatile memory over-wipe problem. It can be avoided that the P=明 proposed-type P-type channel non-volatile memory, the memory and the second memory cell are formed. The silk is provided with N two and = ^ ^ the first memory cell and the second memory cell are set in The '-type well 3 'the first memory cell includes a first-idle pole, a first charge storage junction 2: a doped region and a second doped region. The _th gate is disposed on the substrate... Between the first pole and the substrate; the first mate = the doped region is disposed in the substrate on both sides of the first drain. The second:: 刼 includes the second enzyme, the second charge storage structure, and the third doping The second region is placed on the substrate; the second charge storage structure is mixed with the second closed electrode and the substrate; The doped region and the second doped region are in the substrate on both sides of the first-idle pole, wherein the second memory cell and the first-sense cell = 1276105 17870 twf.doc/r use the second doped region. _ implementation of the introduction of P-type material _ moon beans, the above first charge storage structure and the second X ° k ' nitrogen cut. %_ storage structure of the material package according to the tree _ implementation outline P _ axis suppression 上述 above p The non-volatile memory of the type channel includes a dielectric layer disposed on the second/storage structure and the substrate, and a second tunneling dielectric layer between the storage structure and the substrate. According to the embodiment of the present invention, the p-type channel is non-swept, and the material of the first tunneling thunder-sounding disk-tunneling device is used, for example, according to the material of the transparent layer. In the p-type channel non-volatile body according to the embodiment of the present invention, the memory may further be provided with a first blocking dielectric layer between the first gate and the first charge storage structure. According to the P-channel non-volatile memory of the embodiment of the invention, the memory further includes a second blocking dielectric layer disposed between the second gate and the second charge storage structure. According to the P-channel non-volatile memory of the embodiment of the invention, the first doping region is coupled to a bit line, and the third doping i is coupled to another bit line. In accordance with an embodiment of the present invention, the P-channel non-volatile stimuli 'the first-gate (10) 妾 to a word line, and the second gate such as 妾 to the other two-character line. The above-mentioned P-type channel non-volatile memory has the advantages of low voltage, low power consumption, 1276105 17870 twf.doc/r, and high speed. In addition, there is no need to additionally provide a MOS transistor that cannot store data as a selection transistor, so that the size of the memory cell can be greatly reduced, and the integration of components can be improved. The invention provides a method for operating a P-type channel non-volatile memory. The P-type channel non-volatile memory comprises a substrate, an N-type well region disposed in the substrate, and a first connection in the N-type well region. The memory cell and the second memory cell, wherein the drain of the first memory cell is connected to the source electrode of the second memory cell. Each of the memory cells includes: a gate disposed on the substrate, a charge storage structure disposed between the substrate and the gate, and a source and a drain respectively disposed in the substrate on both sides of the gate; the operation method includes: When the first memory cell of the P-type channel non-volatile memory is used, a first voltage is applied to the source of the first memory cell, and a gate voltage is applied to the gate of the first memory cell. The second voltage is applied to the second memory cell. Applying a third voltage to the gate, opening a channel below the second memory cell, applying a fourth voltage to the drain of the second memory cell, and applying a fifth voltage to the N-type well region, the fourth voltage being greater than the first voltage, fourth The voltage is greater than the second voltage to induce a thermoelectric injection into the first memory cell using a channel thermoelectric hole. According to the method for operating a P-channel non-volatile memory according to an embodiment of the invention, the method further includes: when the second memory cell of the P-type non-volatile memory is programmed, the source of the first memory cell Applying a fourth voltage, applying a third voltage to the gate of the first memory cell, opening a channel below the first memory cell, applying a second voltage to the gate of the second memory cell, and applying a second voltage to the drain of the second memory cell A voltage is applied to the N-well region to apply a fifth voltage to program the second memory 1276105 17870twf.doc/r using a channel thermoelectron-induced hot electron injection mechanism. According to the method for operating a p-type channel non-volatile memory according to an embodiment of the invention, the method further includes applying a first gate of the first memory cell when erasing the P-channel non-volatile memory. The sixth voltage is applied to the N-type well region, wherein the seventh voltage is greater than the sixth voltage and is sufficient to induce the tunneling effect of the FN tunneling effect to erase the first memory cell. . Embodiment p-channel non-volatile memory according to the embodiment of the present invention

Known method, the above operation method further comprises erasing the p-channel non-volatile memory, the gate of the second memory cell applies the first person voltage, in the n^ well

The seventh voltage is applied to the region, wherein the seventh voltage is greater than the eighth voltage sufficient to induce an F_N tunneling effect to erase the second memory cell. The P-channel non-volatile memory/tl乍2 described in the X embodiment is further included in the first-memory cell _ pole-applying the younger $$« is the floating ―-memory cell source immersed material The electric station is the entangled product of the floating second memory cell =, the p-channel non-volatile memory described in the embodiment is a method of adding money to the P-channel non-volatile ϊΐΊΓ The source applies the eleventh five-remembered cell to apply the twelfth voltage, and the second memory is the tenth tenth, and the tenth of the second memory cell applies the tenth wideth. If it is greater than the eleventh voltage. , the operation of the four treasures (7)! 2761〇5 37870twf.doc/r (10) The second memory cell voltage of the body, the tenth between the fourteenth cell of the first source of the first memory cell The second electric heart force, in the second memory-voltage, the tenth is applied in the N-type well region;;, _ the operation unit of the tenth P-channel non-volatile memory is applied == t-memory unit, and one of them is operated Record a cell as the selection transistor, and control the channel below it: 夕': pay to avoid excessive erasure of the memory cells being operated. This is because the stylized operation channel channel thermoelectric hole induces the 蓺 electron mechanism, = division = by F_N wear _ should be carried out, and can enhance the operational efficiency of this non-volatile memory. The P-type channel non-volatile memory and the operation method thereof provided by the invention have the advantages of low voltage, low power consumption and fast writing/, and can be prevented from being excessively erased without separately selecting a selection transistor. In addition, the structure of the single-layer polysilicon can be integrated with the current system-on-chip (SOC) CMOS process. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. [Embodiment] Fig. 1 is a cross-sectional view showing the structure of a 通道-type channel non-volatile memory according to an embodiment of the present invention. Referring to Fig. 1, the Ρ type non-volatile memory of the present invention is composed of, for example, a substrate 100, a well region 101, a memory cell and a memory cell 105. The substrate 1 is, for example, a crucible substrate. Well area

11 1276105 17870twf.doc/r 101 is, for example, an N-type well region disposed in the substrate 100. The memory cell 1〇3, the memory cell 105 is disposed, for example, on the well region 101, and the two memory cells 1〇3, 105 are, for example, connected in series. The memory cell 1〇3 includes a tunneling dielectric layer 10a, a charge storage structure 110b, a blocking dielectric layer 110c, a gate 120, a doping region i5〇b (a source of the memory cell 103), and a doping region 150c (memory) The bungee of the cell 103). The tunneling dielectric layer 11a, the charge storage structure ii〇b, the blocking dielectric layer n〇c and the gate 120 are sequentially disposed on the substrate 1 from bottom to top. The impurity-changing region 150b (the source of the memory cell 103) and the doping region i5〇c (the drain of the memory cell) are, for example, disposed in the substrate 1〇〇 on both sides of the gate 120. The material for tunneling the dielectric layer 11a and the blocking dielectric layer is, for example, cerium oxide. The material of the charge storage structure 11b is, for example, a material in which charges can be trapped, such as nitrite, oxynitride, surface oxide, titanate, and lanthanum oxide. The material of the gate 120 is, for example, a conductive material such as doped polysilicon, metal or metal oxide. The doped region 15〇b and the doped region 15 are, for example, p-type doped regions containing a P-type dopant such as boron. It is to be noted that the above-mentioned blocking dielectric layer 11 can be selectively disposed depending on the setting of the element. In one embodiment, the gate and the substrate are, for example, only disposed through the dielectric layer 11A and the charge storage structure. The memory cell 1〇5 includes a pass-through dielectric layer 130a, a charge storage structure 130b, a blocking dielectric layer 13〇e, an inter-pole 14(), a doped region 15 plus a source of the sigmoid 105, and a doped region. 15〇b (the memory cell (10) is not very good). And, the tunneling dielectric layer 130a, the charge storage structure b, the blocking dielectric layer, and the sigh and the closing electrode 140 are sequentially disposed on the substrate (10) from bottom to top. Mixed

12 1276105 17870twf.doc/r The area 150a (the source of the memory cell 〇5) and the doped region 15 (the drain of the memory cell) are, for example, disposed in the substrate 1 两侧 on both sides of the gate 140. The memory cell 105 shares the doped region 150b with the memory cell 1〇3, and the two memory cells are connected in series. The tunneling dielectric layer 13A, the charge storage structure 13B, the blocking dielectric layer 130c and the gate 140 are, for example, the tunneling dielectric layer 11A, the charge storage structure 11 Ob, and the blocking dielectric layer 110c. The gate 120 has the same material. Likewise, the blocking dielectric layer 130c can also be selectively disposed as needed. For example, spacers 145 are further provided on both sides of the gates 120 and 140, and the material of the spacers 145 is, for example, ruthenium oxide. A shallow doped region 160 is provided, for example, in the substrate 1 下方 below the spacer 145 to mitigate the short channel effect. In one embodiment, the doped region 150a (the source of the memory cell 105) is coupled to, for example, a bit line, and the doped region 150c (the drain of the memory cell 103) is coupled to another bit line, for example. The gate 140 of the memory cell 105 is, for example, coupled to a word line, and the gate 120 of the memory cell 1〇3 is, for example, surfaced to another word line. When operating the p-type channel non-volatile memory, for example, the serially connected memory cell 103 and the memory cell 105 are regarded as one memory cell. When the memory cell 103 writes data, the memory cell 105 is used as the selection transistor; when the memory cell 105 writes the data, the memory cell 1〇3 is selected as the selection transistor to avoid writing, reading and erasing operations. Problems such as misjudgment or over-erasing of data occur. It is worth mentioning that, although the P-type substrate 1〇〇 is matched with the p-type channel non-volatile memory of the N-type well region 1〇1 as an example, the memory proposed by the present invention is of course also It can be that the N-type well region is not set, but 13 1276105 17870twf.doc/r is forced to non-volatile memory. 105 constitutes a note, two memory cells 103 connected in series, then another = two 2, read one of the memory cells, another set - can not be used to select the transistor. That is to say, there is no need for a body, so that the M0S transistor of the Bay I4 can be greatly reduced as the selection of the crystal, and the size of the bit cell is increased to increase the degree of integration of the element. It has a single-material crystal memory only (SOQ: Logic process with CMOS = MW, system-level wafer Figure 2 ^ 1 loading volatile memory operation method, Figure 2A to Hua, Xinji J-type pass this Schematic diagram of the stylization, = fetching and erasing operation modes of non-volatile memory cells. Daofei! Yes, in the present invention, the type 1fK ^ U version of the red-handed system is connected in series by two memories. When the cell 103, the partial 'write data to the memory cell 105, use the record "L", select the transistor; when writing data to the memory cell 103, then J j10! is to select the transistor, to avoid writing, reading Take the problem of misjudgment or over-erasing of the wooden narration material. The monthly success of the maiden picture 2A, when the memory cell of the stylized memory unit is 1〇5, the voltage is applied to the source of the memory cell 1G5, It is, for example, about Q volts; 105 ^ Vgp^^H〇^ 5 ; 2: hex f: the gate applied voltage of the cell 103 & it is, for example, about volts volts; , for example, about 6 volts;

14 1276105 17870twf.doc / r = type well application voltage Viip, which is for example about 6 volts. Among them, it is used for the selection of the transistor to open the channel below the gate of the memory cell 103; the Guangbao 'dp of the memory cell 103 (10) is greater than the source voltage Vsp of the memory cell 105, the memory cell, the, and the extreme voltage The vdp is larger than the gate voltage Vgp of the memory cell 1〇5, in order to induce the hot electron injection effect by the channel thermoelectric hole, stylize the memory cell 105, and write data in the memory cell 105. On the other hand, when another memory cell of the stylized memory unit is 1〇3, the localized memory cell 105th temple is originally applied to the memory cell 1〇5 ", β, voltage VSp, and is applied to the memory cell 1〇 The ^^ cell gate of the ^^ is changed to be applied to the memory; ^, Qiaoji, the voltage Vdp originally applied to the drain of the memory cell 103 is changed to the source of the 2fe, cell 105; The electric I Vgp originally applied to the gate of the memory cell 1〇3 is changed to the gate applied to the memory cell 1〇5, and the underside of the memory cell 1〇5 is used, and the source and the memory cell of the memory cell 105 are utilized. The pressure difference between the gates of the 1G3 cell of 1〇3 induces the attractive effect of the channel thermoelectric hole, stylized memory cell 1G3, and in the memory cell 103, the lens is read in Figure 2B, and the memory cell is read at 1〇5 In the source of the memory cell 1〇5, the voltage is applied, which is, for example, about 1.5 volts; the voltage applied to the idle electrode of the memory cell 105 is, for example, about 3.3 volts; in the memory cell, 1 〇 3 scoops] It is known to apply a voltage V0, which is, for example, about volts; in the memory cell 3 and = applied voltage V&, for example, about 3 volts 丨 in the N-well region, the voltage is applied Vnr For example, it is about 3.3 volts. Among them, memory cells (10) 1276105 17870twf.d〇c/r

For the use of St crystals, apply electricity house tMV to the interpole of memory running (10); ^3

Vnr is the same 'and Ji;; 1:: and, the pressure source voltage of the nine and N wells v \ = voltage 4 is greater than the memory cell m of the Taoist 乂 κ, the wrong channel Switch / pass 〇 〇 5 1 〇 5 remember (four) 103 m of electric repeatedly Vsr ' changed to apply. The immersion of 〇u〇1〇3; originally applied to the memory cell 〇5 pole, changed to the voltage vdr applied to the 马 忆 忆1〇3, and changed to the memory cell 1 〇Guangkou: ^ cell 103 汲 忆 胞 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 103 Use the channel switch under the memory cell 103 to determine whether the information is "1" or "〇". If the number of τ is 爹=2C 'When the memory cells 105, 103 of the memory cell are erased, 'or the source of the memory cell 105' is applied with a voltage Vse, for example, 6 aristocrats and scholars w, two disgusting V, For example, it is 6 jobs, and the gate of the (4) cell 105 is applied with a sweetness of about 1 volt; the gate of the memory cell 1〇3 is applied by the pressure======================= The drain is applied with a voltage V, which is, for example, about volts;:: the well region is applied with a voltage Vne, which is an example of the right. The voltage Vne of the well region is, for example, larger than the memory cell 1 1616 Ϊ 276105 17870 twf.doc/r ge The gate voltage vg, e of the memory cell 103 is different from the (4) difference of the other cells 105, 1 () 3 1 , and the F_N tunneling effect is generated in the N-type well region and recorded in the memory cell 1 〇5, the middle 3 pulls out 'to erase the memory cells 105 and 103. The volatile base is matched with the P-type channel non-type of the well area, but the invention can also be applied to the unset N if _ (four) way Forwarding remarks. Of course, if it is repeated, it will be changed: on ^=, "the electrical connection applied to the 井-type well area = the editing method, when the adjacent string is used, the memory unit is used as the middle two." A memory cell, the bottom of which channel switching system, and to avoid excessive grain == erase phenomenon. In addition, it is carried out by the polar cells of == 乍, and the TM is the same as the effect. In summary, the present invention has the operational efficiency of the military. And the operation method thereof, the two memory cells which are connected by the adjacent string m to the non-volatile memory unit i Φ-b 4 are commensurate with the size of the small component, thereby improving the step of the body, In addition, the present invention has a fast operating speed and low power loss non-volatile memory, and has a portable electronic product, which is quite suitable for the current application of the shield operation system using channel thermoelectricity: Due to the process, private money system, erasing operation system

1276105 17870twf.doc/r Carrying out 'more can strengthen this. Type Channel Non-Volatile Although the present invention has been disclosed above by way of example, it is not the present invention, and anyone skilled in the art can make some changes and refinements in the present invention. The definition of the scope of the patent application attached to the review is subject to change. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing the structure of a household memory according to an embodiment of the present invention. 1 Passive Non-Volatile Figure 2A is a schematic diagram showing the stylized operation mode of a p, and memory according to an embodiment of the present invention. Non-volatile Non-volatile Figure 2B is a schematic diagram showing the read operation mode of a $-sex memory according to an embodiment of the present invention. FIG. 2C is a schematic diagram showing the erasing operation mode of a p-type memory according to an embodiment of the present invention.孓 遑 遑 遑 【 主要 主要 主要 主要 主要 主要 【 遑 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 Layers 120, 140 · Gate 145: spacers 150a, 150b, 150c · Doped region 160: shallow doped region

18

Claims (1)

1276105 17870twf.doc/r X. Patent application scope: 1. A P-type channel non-volatile memory, comprising a substrate, wherein an N-type well region is disposed in the substrate; a first memory cell is disposed in the N-type well The first memory layer includes: a first gate disposed on the substrate; a first charge storage structure disposed between the first gate and the substrate; and a first doping a second doped region disposed in the substrate on both sides of the first gate; and a second memory cell disposed on the N-well region, the second memory cell comprising: a second gate a second charge storage structure disposed between the second gate and the substrate; and a third doped region and the second doped region disposed on the second gate In the substrate on both sides, the second memory cell shares the second dummy region with the first memory cell. 2. The P-type channel non-volatile memory of claim 1, wherein the material of the first charge storage structure and the second charge storage structure comprises tantalum nitride. 3. The P-type channel non-volatile memory of claim 1, further comprising: a first tunneling dielectric layer disposed on the first charge storage structure and the 19 1276105 17870 twf.doc/r Between the substrates; and - between the second tunneling dielectric layer substrates. The storage structure of the younger brother is placed in the fourth part of the book, such as the patent application section, wherein the first-through-hearted non-volatile record includes oxidized hair. "Correction 1 ^ dielectric layer material 5 · as claimed in the scope of the third memory, but also - the first _ (four) ^ ^ ' pass the non-volatile memory * blocking dielectric layer, set in the brother a charge Between storage structures. The gate and the memory 6: ϊ, the p-channel non-volatile memory: the limb further includes an H-trap between the second charge storage structure. $-gate with the _body 7,. Li = the first item? The non-volatile record of the type channel is reduced to the one-line line of the recorded area, and the non-volatile note of the third change zone is the other one, the younger brother-the idler_to-word line, the first二闸_接9· A method for operating a non-volatile memory of a Ρ-type channel, the channel is not a wei wei ** 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽 纽a memory cell, wherein the drain of the first memory cell is connected to a source of the second memory cell, each of the memory cells comprising: a gate disposed on the substrate, a charge storage structure, Provided between the substrate and the gate; a source 20 1276105 17870twf.doc/r a pole and a drain are respectively disposed in the substrate on both sides of the gate; the operation method includes: when the first memory cell of the P-channel non-volatile memory is programmed Applying a first voltage to a source of the first memory cell, applying a second voltage to a gate of the first memory cell, applying a third voltage to a gate of the second memory cell, and opening the second memory a channel below the cell, applying a fourth voltage to the drain of the second memory cell, applying a fifth voltage to the N-well region, the fourth voltage being greater than the first voltage, the fourth voltage being greater than the second The voltage is used to program the young memory cell by using the channel thermoelectric hole to induce the hot electron injection effect. 10. The method for operating a P-channel non-volatile memory according to claim 9 of the patent application, further comprising: when the second memory cell of the P-type non-volatile memory is programmed, the first memory cell Applying the fourth voltage to the source, applying the third voltage to the gate of the first memory cell, opening a channel below the first memory cell, applying the second voltage to a gate of the second memory cell, The first voltage is applied to the drain of the second memory cell, and the fifth voltage is applied to the N-well region to program the second memory cell using a channel thermoelectron induced hot electron injection mechanism. 11. The method for operating a P-type channel non-volatile memory according to claim 9 of the patent application, further comprising: applying a non-volatile memory of the P-type channel to the gate of the first memory cell A sixth voltage is applied to the N-type well region, wherein the seventh voltage is greater than the sixth voltage and is sufficient to induce an FN tunneling effect to erase the first memory cell. 21 1276105 17870twf.doc/r 12. The method for operating a P-channel non-volatile memory according to claim 11 of the patent application, further comprising: erasing the P-channel non-volatile memory, The gate of the two memory cells applies an eighth voltage, and the seventh voltage is applied to the N-type well region, wherein the seventh voltage is greater than the eighth voltage and is sufficient to induce an FN tunneling effect to erase the second memory cell. 13. The method for operating a P-channel non-volatile memory according to claim 12, further comprising: applying a ninth voltage to the source of the first memory cell or floating the first memory cell The source of the second memory cell applies a tenth voltage or floats the drain of the second memory cell. 14. The method for operating a P-channel non-volatile memory according to claim 9 of the patent application, further comprising: reading the first memory cell of the P-channel non-volatile memory, in the first memory An eleventh voltage is applied to the source of the cell, a twelfth voltage is applied to the gate of the first memory cell, and a thirteenth voltage is applied to the gate of the second memory cell, and the second memory cell is A fourteenth voltage is applied to the drain, and a fifteenth voltage is applied to the N-well region, wherein the fourteenth voltage is greater than the eleventh voltage. 15. The method for operating a P-channel non-volatile memory according to claim 14, further comprising: reading the second memory cell of the P-channel non-volatile memory, in the first memory Applying the fourteenth voltage to the source of the cell, applying the thirteenth voltage to the gate of the first memory cell, applying the twelfth voltage to the gate of the second memory cell, and the second memory cell The eleventh voltage is applied to the drain, and the fifteenth voltage is applied to the N-well region. twenty two