1275181 . 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種薄膜電晶體基板製造方法，還關於一種採用該 方法製造之薄膜電晶體基板。 【先前技術】， -目前，液晶顯示器逐漸取代用於計算機之傳統陰極射線管 -(Cathode Ray Tube，CRT)顯示器，而且，由於液晶顯示器具輕、薄、小 #等特點，使其非常適合應用於桌上型電腦、膝上型電腦、個人數字助 理(Personal Digital Assistant，PDA)、便攜式電話、電視及多種辦公自動 化與視聽設備中。液晶面板是其主要元件，其一般包括一薄膜電晶體 基板、一彩色濾光片基板及夾於該薄膜電晶體基板與該彩色濾光片基 板之間之液晶層。 請參閱第一圖，係一傳統的薄膜電晶體基板1〇〇之結構示意圖。 該薄膜電晶體基板100包括一基底101、一位於基底1〇1上之閘極 壽102、一位於該閘極1〇2及該基底1〇1上之閘極絕緣層1〇3、一位於該 閘極絕緣層上103之半導體層1〇4、一位於該半導體層1〇4及該閘極 絕緣層103上之源極1〇5與没極1〇6、一位於該閘極絕緣層1〇3、該源 極105及該汲極1〇6上之鈍化層1〇7以及一位於該鈍化層1〇7上之像 素電極108。 請參照第二圖，係該薄膜電晶體基板100之傳統製造方法之流程 圖。該製造方法採用五道光罩製程，包括以下步驟： 一、第一道光罩 6 1275181 (1)形成閘極金Μ爲· 成-閑極金朗及提供—絕緣基底，在該絕緣基底上依序形 弟一光阻層； 光顯(Γ t成閘蝴$: 道料關案對該第—光阻層進行曝 —閉請之_，=案；對該_金屬層進行糊，進而形成 口茶，移除第一光阻層； 一、苐二道光罩 ⑶減咖E緣層、非晶魏摻雜非㈣層：於具有該間極之 ==场成-閑極絕緣層1Q3、__非晶#及#雜非㈣層及_第 行曝=成1=料：…辦刪物二光阻層進 崎成1定®案；對該摻雜非_層及該非晶石夕層 減刻，進而形成—具有預定圖案之半導體層1〇4，移除第二光阻 增； 三、 第三道光罩 • (5)形成源/及極金屬層：於該基底及該半導體層圖案上形成一源/ 汲極金屬層及一第三光阻層； 、⑹形成源级極金屬層圖案：以第三道光罩_案對該第三光阻 …U顯衫’從而形成—預定圖案；對該源版極金屬層進行姓 d進而形成-源極105及一没極106，移除第三光阻層； 四、 第四道光罩 ⑺形成鈍化層：於具有該閘極、雜及没極的基底上沈積一純 化層及一第四光阻層； d 7 1275181 ⑻开y成鈍化層：料四道光罩的目賴該第四練層進 曝光顯影，從而形成―取圖案；對該鈍化層進行侧，進而定義出 一鈍化層107之圖案，移除第四光阻層； 五、第五道光罩 (9) ^/成^體層·於財該閘極、源極、雜及鈍化層圖案的 基底上形成一導體層及一第五光阻層； ⑽形成像錢極_ :以第五道解賴親該第五光阻層進 打曝光娜，從而形成―預定圖案；對該導體層進行蝴，進而定義 出一導體層圖案，即像素電極_ ，移除第五光阻層。 惟’該方法需要财鮮製程，*光稍鋪倾為複雜且成本 較高，從而使得製造成本較高。 【發明内容】 有4^於此提供一種製程簡單且成本低之薄膜電晶體基板製造方 法實為必要。 • 還提供一讎用上述方法製造之薄膜電晶體基板。 一種薄膜電晶體基板製造方法’其步驟包括·在—絕緣基底上依 次沈積-透明導電金屬層及一閘極金屬層；在該問極金屬層上沈積一 光阻層，以-預定圖案之光罩對該光阻層進行曝光及顯影，形成預定圖 案之光阻層；對該透明導電金屬層及閘極金屬層進行侧，形成預定 圖案之像素電極及閘極；去除剩餘光阻。 一種薄膜電晶縣板製造方法，其步驟包括：提供—絕緣基底； 依次在該絕緣基底上沈積一透明導電金屬層及一間極金屬層；在一道 ⑧ 8 1275181 _光罩製程中形成預定圖案之像素電極及閘極；在該絕緣基底、像素電 極及閘極上沈積-閘極絕緣層；在該閘極絕緣層上形成預定圖案之半 導體層；在該閘極絕緣層上形成-接觸孔圖案；在該半導體層及該閑 極絕緣層上形成源/汲極圖案。 -種薄膜電晶體基板，其包括-絕緣基底、—設置於該絕緣基底 .上之像素電極層及透明導電金屬層、一設置於該透明導電金屬層上之 -閘極層、-S变置於該閘極層及像素電極層上之閘極絕緣層、一設置於 籲該閘極絕緣層上之半導體層、-設置於該半導體層及該閑極絕緣層上 之源/沒極層。 相較於先前技術，上述薄膜電晶體基板製造方法將採用一道光罩 製程形成閘極圖案及像素電極圖案，從而節省一道光罩製程，光罩次 數減少，製程簡化，可有效降低成本。上述薄膜電晶體基板採用該方 法製造，製程簡單。 【實施方式】 鲁 明參閱弟二圖，係本發明薄膜電晶體基板一較佳實施方式所揭示 之結構示意圖。該薄膜電晶體基板200包括一絕緣基底2〇1、一設置 於該絕緣基底201上之像素電極212及透明導電金屬202、一設置於 該透明導電金屬202上之閘極213、一設置於該閘極213及該像素電 極212上之閘極絕緣層204、一設置於該閘極絕緣層204上之半導體 層215、一設置於該半導體層215及該閘極絕緣層2〇4上之源/没極 216、一設置於該源/汲極216及該閘極絕緣層2〇4上之鈍化層2〇7。 請參閱第四圖，係本發明之薄膜電晶體基板200製造方法之流程197. The invention relates to a method for manufacturing a thin film transistor substrate, and to a thin film transistor substrate manufactured by the method. [Prior Art] - At present, liquid crystal displays are gradually replacing the traditional cathode ray tube (CRT) display for computers, and because of the characteristics of light, thin and small liquid crystal display devices, it is very suitable for application. It is used in desktop computers, laptops, personal digital assistants (PDAs), cellular phones, televisions, and a variety of office automation and audiovisual equipment. The liquid crystal panel is a main component thereof, and generally includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate. Please refer to the first figure, which is a schematic structural view of a conventional thin film transistor substrate. The thin film transistor substrate 100 includes a substrate 101, a gate electrode 102 on the substrate 〇1, a gate insulating layer 1〇3 on the gate electrode 〇2 and the substrate 〇1, and a layer a semiconductor layer 1?4 on the gate insulating layer 103, a source 1?5 and a gate 1?6 on the semiconductor layer 1?4 and the gate insulating layer 103, and a gate insulating layer. 1〇3, the source 105 and the passivation layer 1〇7 on the drain 1〇6 and a pixel electrode 108 on the passivation layer 1〇7. Referring to the second figure, a flow chart of a conventional manufacturing method of the thin film transistor substrate 100 is shown. The manufacturing method adopts a five-mask process, including the following steps: 1. The first mask 6 1275181 (1) forms a gate metal · 成 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The order of the brother-one photoresist layer; light display (Γ t into the brake butterfly $: the material is closed to the first - photoresist layer exposure - closed _, = case; the _ metal layer paste, and then form Oral tea, remove the first photoresist layer; 1. 苐 two-pass mask (3) minus coffee E edge layer, amorphous Wei doping non-(four) layer: in the case of the interpolar electrode == field formation-idle insulation layer 1Q3, __Amorphous ############################################################################################# The layer is etched to form a semiconductor layer 1〇4 having a predetermined pattern to remove the second photoresist; 3. a third mask; (5) forming a source/and a metal layer: the substrate and the semiconductor layer Forming a source/dual metal layer and a third photoresist layer on the pattern; and (6) forming a source-level metal layer pattern: forming a third photomask by using a third photomask. pattern The source plate metal layer is subjected to a first name d to form a source 105 and a gate 106, and the third photoresist layer is removed. 4. The fourth mask (7) forms a passivation layer: having the gate, the impurity, and the Depositing a purification layer and a fourth photoresist layer on the substrate; d 7 1275181 (8) Opening the y into a passivation layer: the material of the four masks is exposed to the exposure layer to form a "take pattern"; The passivation layer is on the side, thereby defining a pattern of a passivation layer 107, and removing the fourth photoresist layer; 5. The fifth mask (9) ^/ into the body layer · the gate, source, impurity, and passivation Forming a conductor layer and a fifth photoresist layer on the substrate of the layer pattern; (10) forming a photo-like pole _: exposing the fifth photoresist layer to the fifth photoresist layer to form a predetermined pattern; The conductor layer is patterned to define a conductor layer pattern, that is, the pixel electrode _, and the fifth photoresist layer is removed. However, the method requires a fresh process, and the light is slightly complicated and costly, thereby manufacturing The invention has a high cost. [Invention] The present invention provides a thin film battery with simple process and low cost. A method of manufacturing a crystal substrate is necessary. • A thin film transistor substrate manufactured by the above method is also provided. A method for manufacturing a thin film transistor substrate includes the steps of: sequentially depositing a transparent conductive metal layer and a gate on an insulating substrate a thin metal layer; a photoresist layer is deposited on the interposing metal layer, and the photoresist layer is exposed and developed in a predetermined pattern of photomask to form a predetermined pattern of photoresist layer; the transparent conductive metal layer and the gate The electrode layer is formed on the side to form a pixel electrode and a gate of a predetermined pattern; and the residual photoresist is removed. A method for manufacturing a thin film electromorphic plate comprises the steps of: providing an insulating substrate; and sequentially depositing a transparent conductive metal on the insulating substrate a layer and a metal layer; forming a predetermined pattern of pixel electrodes and gates in an 8 8 1275181 _mask process; depositing a gate insulating layer on the insulating substrate, the pixel electrode and the gate; insulating the gate Forming a semiconductor layer of a predetermined pattern on the layer; forming a contact hole pattern on the gate insulating layer; forming a source on the semiconductor layer and the dummy insulating layer Pole pattern. a thin film transistor substrate comprising: an insulating substrate, a pixel electrode layer and a transparent conductive metal layer disposed on the insulating substrate, a gate layer disposed on the transparent conductive metal layer, and a -S transposition a gate insulating layer on the gate layer and the pixel electrode layer, a semiconductor layer disposed on the gate insulating layer, and a source/drain layer disposed on the semiconductor layer and the dummy insulating layer. Compared with the prior art, the above method for manufacturing a thin film transistor substrate uses a mask process to form a gate pattern and a pixel electrode pattern, thereby saving a mask process, reducing the number of masks, simplifying the process, and effectively reducing the cost. The above thin film transistor substrate is manufactured by the method, and the process is simple. [Embodiment] Lu Ming, referred to as the second drawing, is a schematic structural view of a preferred embodiment of the thin film transistor substrate of the present invention. The thin film transistor substrate 200 includes an insulating substrate 2, a pixel electrode 212 disposed on the insulating substrate 201, a transparent conductive metal 202, and a gate 213 disposed on the transparent conductive metal 202. a gate electrode 213 and a gate insulating layer 204 on the pixel electrode 212, a semiconductor layer 215 disposed on the gate insulating layer 204, and a source disposed on the semiconductor layer 215 and the gate insulating layer 2〇4 / No pole 216, a passivation layer 2〇7 disposed on the source/drain 216 and the gate insulating layer 2〇4. Please refer to the fourth figure, which is a flow chart of the manufacturing method of the thin film transistor substrate 200 of the present invention.
(S 9 1275181 圖。該薄膜電晶體基板之製造方法包括四道光罩製程，其具體步驟如 下： 一、 第一道光罩 (1) 形成一透明導電金屬層及一閘極金屬層； 請參閱第五圖，提供一絕緣基底201，該絕緣基底201可以係玻 .璃、石英或者陶瓷等絕緣材質；在該絕緣基底201上沈積一透明導電 -金屬層202，該透明導電金屬層202可以為銦錫氧化物（in(jium Tin • Oxide, ITO)或銦鋅氧化物（Indium Zinc Oxide, IZO);在該透明導電 金屬層上沈積一閘極金屬層203,其材料可為鋁（A!)系金屬、鉬（M〇) 或銅（Cu);在該閘極金屬層203上沈積一第一光阻層231。 (2) 形成閘極圖案及像素電極圖案； 請一併參閱第六圖，以第一道光罩製程的圖案對準該第一光阻層 231上方，以高能光線平行照射該第一光阻層231，再對該光阻層231 進行顯影，從而可於該第一光阻層231上形成一預定圖案，對該閘極 鲁金屬層203及該透明導電金屬層202進行蝕刻以形成預定的閘極213 及像素電極212之圖案。移除剩餘之第一光阻層231，清洗後烘乾基 底 201。 由於該閘極金屬層203及該透明導電金屬層202位於相鄰層次， 且閘極213及像素電極212在垂直於該基底2〇1方向並無重疊，所以 本步驟採用一道光罩製程即可同時形成閘極213及像素電極212之圖 案’相較於先前技術，可節省一道光罩，簡化製程，降低成本。 二、 第二道光罩 1275181 ' (3)依序形成閘極絕緣層、非晶矽及摻雜非晶矽層； 月併彡閱第七圖，用化學氣相沈積（Chemicai phase Deposition， CVD)方法，利用反應氣體石夕烷(SiH4)與氨氣卿），形成氮化石夕卿) 構成之閉極絕緣層204;再用化學氣相沈積方法在該閉極絕緣層2〇4 上形成-非晶㈣；再進行—道掺紅藝，在該非轉層表面進行播 雜’形成-層摻雜非晶發’從而形成非晶魏摻雜非晶補2〇5。 於該非晶魏摻雜非晶發層2〇5上形成一第二光阻層232。 • (4)形成半導體層之圖案； 併參閱第人圖，以第二道光罩製程的圖案對準該第二光阻層 232上方’以高能光線平行照射該第二光阻層232，從而可於該第二光 阻層232上形成一預定圖案，對該非晶石夕及摻雜非晶石夕層挪進行乾 蝕刻’以移除該二側部份之非晶石夕及摻雜非晶石夕，形成一具有預定圖 案之半導體層215，移除剩餘之第二光阻層232。 三、 第三道光罩 Φ (5)形成接觸孔圖案； 凊-併參閱第九圖及第十圖，於該半導體層加及該閘極絕緣層 204上沈積-第二光阻層233;以第三道光罩製程的圖案對準該第三光 阻層233上方，以高能光線平行照射該第三光阻層说，從而可於該 第三光阻層233上形成一預定圖案，對該閘極絕緣層204進行餘刻， 形成接觸孔214之圖案，移除剩餘之第三光阻層233。 四、 第四道光罩 形成源/汲極金屬層； 11 1275181 、"月併參閱第十一圖，在該間極絕緣層2〇4及該半導體層215上 依次沈積-源/汲極金屬層施及一第四光阻層放，該源/沒極金屬層 206知肋金屬或相合金製成。該源/汲極金屬層施通過該接觸孔 214與該像素電極212電連接。 (7) 形成源/汲極圖案； ，請-併參财十二圖，以細道光罩製程_雜準該第四光阻 -層234上方，以高能光線平行照射該第四光阻層234，從而可於該第 ❿四光阻層234上形成-預定圖案；對該源/汲極金屬層2〇6侧以形成 預定圖案之源/汲極216圖案，並移除剩餘之第四光阻層234。 (8) 形成鈍化層； 請-併參閱第十三圖，於該源/沒極216及該閘極絕緣層2〇4上沈 積一層鈍化層207，得到薄膜電晶體基板2〇〇。 相較於先前技術，該製造方法將採用一道光罩製程形成閑極圖案 213及像素電極圖案212，從而節省一道光罩製程，光罩次數減少，製 φ程簡化，可有效降低成本。 綜上所述，本發明確已符合發明專利之要件，爰依法提出專利申 請。惟，以上所述者僅為本發明之較佳實施方式，本發明之範圍並不 以上述實施例為限，舉凡熟習本案技藝之人士援依本發明之精神所作 之等效修飾或變化，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 第一圖係先前技術之薄膜電晶體基板結構示意圖。 弟一圖係先别技術之薄膜電晶體基板製造方法之流程圖。 12 1275181 t圖本發明之_電晶體基板結構示意圖。 第四圖係本發明之薄膜電晶體基板製造方法之流程圖。 弟五圖係第四圖所示形成透明導電金屬層及閘極金屬層之示音圖 第六圖係第四圖所示形成閘極圖案及像素電極圖案之示意^圖。 第七_第四圖所示形成閘極絕緣層、非晶魏摻雜非晶料之示音 .第八圖係第四圖所示形成半導體層圖案之示意圖。 鲁第九圖係本發明形成第四光阻層之示意圖。 -第十圖係第四圖所示形成接觸孔之示意圖。 第十一圖係第四圖所示形成源/；及極金屬層之示音圖 第十一圖係第四圖所示形成源/没極圖案之示音圖。 第十三圖係第四圖所示形成鈍化層之示意圖。 【主要元件符號說明】 絕緣基底 201 透明導電金屬層 閘極金屬層 203 像素電極 閘極 213 閘極絕緣層 非晶石夕及摻雜非晶石夕層 205 接觸孔 源/汲極金屬層 206 源/汲極 鈍化層 207 第一光阻層 弟二光阻層 232 第三光阻層 第四光阻層 半導體層 234 215 薄膜電晶體基板 202 212 204 214 216 231 233 2〇〇 13(S 9 1275181. The manufacturing method of the thin film transistor substrate comprises four mask processes, the specific steps are as follows: 1. The first mask (1) forms a transparent conductive metal layer and a gate metal layer; The fifth embodiment provides an insulating substrate 201. The insulating substrate 201 may be an insulating material such as glass, quartz or ceramic. A transparent conductive-metal layer 202 is deposited on the insulating substrate 201. The transparent conductive metal layer 202 may be Indium tin oxide (Indium Zinc Oxide, IZO); depositing a gate metal layer 203 on the transparent conductive metal layer, the material of which may be aluminum (A! a metal, molybdenum (M〇) or copper (Cu); a first photoresist layer 231 is deposited on the gate metal layer 203. (2) a gate pattern and a pixel electrode pattern are formed; The first photoresist layer 231 is aligned with the first photoresist layer 231, and the first photoresist layer 231 is irradiated with high energy light, and the photoresist layer 231 is developed. A predetermined pattern is formed on a photoresist layer 231, and the gate metal layer 20 is 3 and the transparent conductive metal layer 202 is etched to form a pattern of the predetermined gate 213 and the pixel electrode 212. The remaining first photoresist layer 231 is removed, and the substrate 201 is dried after cleaning. Due to the gate metal layer 203 and The transparent conductive metal layer 202 is located at an adjacent level, and the gate electrode 213 and the pixel electrode 212 do not overlap in a direction perpendicular to the substrate 2〇1. Therefore, in this step, the gate electrode 213 and the pixel electrode can be simultaneously formed by using a mask process. Compared with the prior art, the pattern of 212 can save a mask, simplify the process and reduce the cost. Second, the second mask 1275181 ' (3) sequentially form the gate insulating layer, amorphous germanium and doped amorphous germanium The layer is also shown in the seventh figure, using chemical vapor deposition (CVD) method, using the reaction gas (SiH4) and ammonia gas to form a closed-pole insulation composed of nitride stone a layer 204; forming a non-amorphous (four) on the closed-electrode insulating layer 2〇4 by a chemical vapor deposition method; and performing a red-doping process on the surface of the non-transfer layer to form a layer-doped amorphous layer Amorphous Wei-doped amorphous complement 2 〇 5. A second photoresist layer 232 is formed on the amorphous Wei-doped amorphous layer 2〇5. (4) forming a pattern of the semiconductor layer; and referring to the figure of the second, aligning the pattern of the second mask process with the pattern of the second photoresist layer 232, illuminating the second photoresist layer 232 in parallel with high-energy light, thereby Forming a predetermined pattern on the second photoresist layer 232, and performing dry etching on the amorphous and doped amorphous layer to remove the amorphous portion and the doped amorphous portion of the two sides. Shi Xi, a semiconductor layer 215 having a predetermined pattern is formed, and the remaining second photoresist layer 232 is removed. Third, the third mask Φ (5) forms a contact hole pattern; 凊 - and refer to the ninth and tenth views, the second photoresist layer 233 is deposited on the semiconductor layer and the gate insulating layer 204; The pattern of the third mask process is aligned with the third photoresist layer 233, and the third photoresist layer is irradiated with high energy light in parallel, so that a predetermined pattern can be formed on the third photoresist layer 233. The pole insulating layer 204 is left in a pattern to form a pattern of the contact holes 214, and the remaining third photoresist layer 233 is removed. Fourth, the fourth mask forms a source/dip metal layer; 11 1275181 , " month and see the eleventh figure, sequentially depositing - source/drain metal on the inter-polar insulating layer 2〇4 and the semiconductor layer 215 The layer is applied with a fourth photoresist layer, and the source/bold metal layer 206 is made of a rib metal or a phase alloy. The source/drain metal layer is electrically connected to the pixel electrode 212 through the contact hole 214. (7) Forming a source/drain pattern; , - and participating in the twelve-figure diagram, in a thin-pass mask process _ miscellaneously over the fourth photoresist-layer 234, the fourth photoresist layer 234 is illuminated in parallel with high-energy rays. So that a predetermined pattern can be formed on the fourth photoresist layer 234; the source/drain metal layer 2〇6 side is patterned to form a source/drain 216 pattern of a predetermined pattern, and the remaining fourth light is removed. Resistive layer 234. (8) Forming a passivation layer; - Referring to Fig. 13, a passivation layer 207 is deposited on the source/dot electrode 216 and the gate insulating layer 2?4 to obtain a thin film transistor substrate 2?. Compared with the prior art, the manufacturing method uses a mask process to form the idler pattern 213 and the pixel electrode pattern 212, thereby saving a mask process, reducing the number of masks, simplifying the process, and effectively reducing the cost. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a schematic view of the structure of a thin film transistor substrate of the prior art. A picture of a method for fabricating a thin film transistor substrate of the prior art. 12 1275181 t is a schematic view of the structure of the transistor substrate of the present invention. The fourth drawing is a flow chart of a method for manufacturing a thin film transistor substrate of the present invention. Figure 5 is a diagram showing the formation of a transparent conductive metal layer and a gate metal layer as shown in the fourth figure. Fig. 6 is a schematic view showing a gate pattern and a pixel electrode pattern shown in the fourth figure. The seventh to fourth figures show the formation of a gate insulating layer and an amorphous Wei doped amorphous material. The eighth figure is a schematic view of forming a semiconductor layer pattern as shown in the fourth figure. The ninth diagram of the invention is a schematic diagram of forming a fourth photoresist layer according to the present invention. - Figure 10 is a schematic view showing the formation of contact holes as shown in the fourth figure. Figure 11 is a diagram showing the source/; and the polar metal layer shown in the fourth figure. Figure 11 is a diagram showing the source/no-polar pattern shown in the fourth figure. The thirteenth diagram is a schematic view showing the formation of a passivation layer as shown in the fourth figure. [Description of main components] Insulation substrate 201 Transparent conductive metal layer Gate metal layer 203 Pixel electrode gate 213 Gate insulating layer Amorphous and doped amorphous layer 205 Contact hole source/dip metal layer 206 source /polarizing passivation layer 207 first photoresist layer two photoresist layer 232 third photoresist layer fourth photoresist layer semiconductor layer 234 215 thin film transistor substrate 202 212 204 214 216 231 233 2〇〇13