1274171 九、發明說明： 【發明所屬之技術領域】 電路狀態掃描鏈（scan chain)、資料獲取系統（built in probe)和模擬驗證方法（method of chip design verification) 【先前技術】 積體電路（integrated circuit)産品能否及時上市是影響 産品競爭力的一個重要因素，隨著積體電路規模的不斷擴 大以及矽智權複用（IP re-use)技術的發展，積體電路設計的 模擬驗證（verification)所需的時間越來越長。因此，提高模 擬驗證效率成爲目前壓縮積體電路産品設計時間的有效手 段之一。 模擬包括軟體模擬（simulati〇n)與硬體模擬 (emulation)。其中，軟體模擬是指把用硬體描述語言編寫的 描述積體電路的代碼（如暫存器傳送語言Register Transfer Language ; RTL )輸入軟體模擬系統，以軟體類比該積體 電路的邏輯功能。硬體模擬是指把所述的代碼輸入硬體模 擬糸統（如現％可程式化閘陣列Field pr〇grammable Gate Array ; FPGA) ’用FPGA類比該積體電路的邏輯功能。軟 體模擬與硬體模擬各有優缺點：軟體模擬的内部狀態為全 可見（full visibility)，因此可觀察待測元件（Device under Test ; DUT)(被軟體模擬系統類比的積體電路）内的任意 信號，所以能藉以對待測元件進行具體的分析，但模擬速 度慢。相反的，雖然硬體模擬速度快，但限於針腳（i/〇pin) 數的限制，其内部信號的觀察十分困難。 5 1274171 關待測元件除錯（debug)只需要在發生錯誤前' • 纟的—小段時間對待測元件進行詳細分析即可，所以只要 把發生錯誤前後的一小段測試程式放在軟體模擬系統上運 γ一卩可、、、"5硬體模擬與軟體模擬的模擬驗證方法在於保|1274171 IX. Description of the invention: [Technical field of invention] Circuit state scan chain, built in probe and method of chip design verification [Prior Art] Integrated circuit (integrated) The timely listing of products is an important factor affecting the competitiveness of products. With the continuous expansion of the scale of integrated circuits and the development of IP re-use technology, the simulation of integrated circuit design ( The time required for verification) is getting longer and longer. Therefore, improving the efficiency of analog verification has become one of the effective means of compressing the design time of integrated circuit products. The simulation includes software simulation (simulati〇n) and hardware simulation (emulation). Among them, the software simulation refers to inputting the code describing the integrated circuit written in the hardware description language (such as the register transfer language Register Transfer Language; RTL) into the software simulation system, and comparing the logic function of the integrated circuit with the software. The hardware simulation refers to inputting the code into a hardware analog system (such as the current DRAM Array) (FPGA) to compare the logic function of the integrated circuit with the FPGA. Both software simulation and hardware simulation have their own advantages and disadvantages: the internal state of the software simulation is full visibility, so the device under test (DUT) (integrated circuit analogized by the software simulation system) can be observed. Any signal, so it can be analyzed by the component to be tested, but the simulation speed is slow. On the contrary, although the hardware simulation speed is fast, it is difficult to observe the internal signal due to the limitation of the number of pins (i/〇pin). 5 1274171 The debugging of the component to be tested only needs to be analyzed before the error occurs. • • A small amount of time to analyze the component to be tested, so just put a small test program before and after the error on the software simulation system. The simulation verification method of γ 卩 卩, , , "5 hardware simulation and software simulation lies in guarantee|
二對f測70件進行具體分析的同時亦提高了模擬驗證效I 、：口之大邛刀的測试程式（test program)在硬體模 - m统上運行，將硬體模擬系、統的輸出信號與標準的輸出 ㈣進行比對，以判斷是否發生錯誤。而通過複製硬體模 • 擬线的電路狀態（state)及輸入序列（input化㈣㈣），使硬 體核擬系統在發生錯誤前後一小段時間的行爲在軟體模擬 系統上重現。最後，利用軟體模擬系統對待測元件進行具 一刀析上述的這種方法兼具硬體模擬與軟體模擬兩者 之優點。 任何單時脈、同步的數位系統都可以看成是一個巨大 的狀態機（state machine)。而硬體模擬系統類比的待測元件 就是這樣一個系統。這裏將對以下幾個概念進行說明： _ 輸入序列（以下簡寫爲inPut—seq ):輸入信號由時脈 (clock)採樣得到的離散序列。 輸出序列（以下簡寫爲output一Seq):輸出信號由時脈 採樣得到的離散序列。 狀態序列（以下簡寫爲state 一 seq):電路狀態由時脈採 樣得到的離散序列。 行爲函數（behavior一function ):由某個狀態和與其對 應的輸入序列得到輸出序列的函數，由當前狀態和輸入序 列作爲參數，産生狀態序列和輸出序列兩個序列。 1274171 行爲函數和狀態序列、輸入序列以及輸出序列的關係 如下： (state 一 seq，output 一 seq) =behavior—function (init—state，input—seq) 〇 上式可以描述爲：一段時間内，系統的行爲（state_seq 和 output一seq)由系統的行爲函數（behavior_function)、初 始狀悲（init—state )和輸入序列（input—seq )三者唯·決 定。 如果需要在軟體模擬系統上複現（reproduce)待測元件 在硬體模擬系統上的行爲，就需要在硬體模擬系統上得到 上述二種資訊：行爲函數、初始狀態和輸入序列。 衆所周知，一個單時脈、同步的積體電路，在任意時 刻’其狀態由内部記憶體存儲的資料唯一決定；其行爲函 數由其内部所有的組合邏輯唯一決定；輸入序列則由外部 決定。 硬體模擬系統中與軟體模擬系統中的該待測元件的組 合邏輯相同（至少在正常工作模式下的組合邏輯相同）。換 δ之’邊積體電路在兩個平臺上的行爲函數相同，因此， 只要有硬體模擬系統上該待測元件的“初始狀態，，和“輸 入序列就可以在軟體模擬系統上複現該待測元件在硬體 模擬系統上的行爲（即狀態序列與輸出序列）。這是前述結 合硬體模擬與軟體模擬的模擬驗證方案的基礎。 因此，要在軟體模擬系統中複現硬體模擬系統所類比 的忒待測兀件的行爲，首先需要從硬體模擬系統得到“初 始狀態’，# “輸人序列，，。“輸入序列，，可通過複製待測 1274171 =件的輪入得到，所以比較容易實現，然而問題在於如何 仔到初始狀態”（該領域一般把獲得“初始狀態，，的過 程稱爲快照·’ Snapshot)。目前，業界一般的做法是把軟體 模擬系統與硬體模擬系統以某一種方式連接，使兩者間可 進行電路狀態的相互傳輸，從而實現模擬在兩個系統間的 切換。如美國專利第5,937，179號（以下稱179號專利）所 揭不的方案，硬體模擬發生錯誤時，暫停測試程式的運行， 利用備份暫存器構建的掃描鏈（Scan_Chain)把待測元件的 電路狀態導出並輸入軟體模擬系統，在軟體模擬系統上從 這一刻繼續向前運行或者向後運行測試程式，在軟體模擬 系統上複現該錯誤並對之進行分析（請參179號專利說明 書第3攔第63行至第67行以及第4攔第39行至第43行）。 然而’這種模擬驗證方法仍有以下幾個缺點：第一，用額 外的備伤暫存器構建電路狀態掃描鍵，使積體電路閘數大 幅增加，提高了現場可程式化閘陣列（卯(}八）模擬的成本， 對超大型積體電路設計而言這點尤爲重要；第二，模擬在 軟體模擬與硬體模擬之間切換，切換次數比較多，使模擬 效率降低；第三，硬體模擬系統發生錯誤時，分析該錯誤 的發生原因的最佳時刻已經過去，而要在軟體模擬系統上 通過回跑測試程式獲得該時刻的“初始狀態，，非常困難， 且不一定能夠實現。 【發明内容】 因此’爲簡化模擬驗證’提南模擬驗證的效率，降低 模擬驗證的成本，亟需設計一種新的模擬驗證方案。 1274171 本發明提供一種電路狀態掃描鏈，包括··多個暫存哭 (register)以及與每個暫存器對應的輸入端組合邏輯二 combinational 1〇gic)和輸出端組合邏輯（⑽印加 combinational logic)。每個暫存器的輸出埠和與之相對應2 輸出端組合邏輯的輸入埠連接，所述電路狀態掃描鏈還包 括與所述多個暫存器相對應的多個第一多工器 及多個第二多工器，其中，每個暫存器與相應的一個第一 多工器和相應的一個第二多工器相關，第一多工器與第二 多工器都分別設有兩個輸入埠與一個輸出埠。其中，各第 一多工器的第一輸入埠和與之相應的暫存器的輪出埠連 接，各帛一多ill的第二輸入埠與前一暫存器的輸出璋連The two pairs of f-test 70 pieces of specific analysis also improve the simulation verification effect I, the test program of the mouth of the big file runs on the hardware module, the hardware simulation system The output signal is compared to the standard output (4) to determine if an error has occurred. By copying the circuit state (state) and input sequence (input (4) (4)) of the hardware model, the behavior of the hardware verification system is reproduced on the software simulation system for a short period of time before and after the error occurs. Finally, the software simulation system is used to analyze the components to be tested. This method combines the advantages of both hardware simulation and software simulation. Any single-clock, simultaneous digital system can be thought of as a huge state machine. The analog component of the analog analog system is such a system. The following concepts are explained here: _ Input sequence (hereafter abut-seq): A discrete sequence of input signals sampled by clock. The output sequence (hereafter abbreviated as output-Seq): The discrete sequence of the output signal sampled by the clock. The sequence of states (hereafter abbreviated as state - seq): A discrete sequence of circuit states derived from clock samples. Behavior function (behavior-function): A function that obtains an output sequence from a state and its corresponding input sequence. The current state and the input sequence are used as parameters to generate two sequences, a state sequence and an output sequence. 1274171 The relationship between behavioral functions and state sequences, input sequences, and output sequences is as follows: (state one seq, output one seq) =behavior-function (init_state, input-seq) The above equation can be described as: system for a period of time The behavior (state_seq and output-seq) is determined by the system's behavior function (behavior_function), initial sorrow (init-state), and input sequence (input-seq). If you need to reproduce the behavior of the device under test on the hardware simulation system, you need to get the above two information on the hardware simulation system: behavior function, initial state and input sequence. It is well known that a single-clock, synchronous integrated circuit, at any time, its state is uniquely determined by the data stored in the internal memory; its behavioral function is uniquely determined by all its internal combinational logic; the input sequence is determined externally. . In the hardware simulation system, the combination logic of the device under test in the software simulation system is the same (at least the combination logic in the normal operation mode is the same). The δ 'edge integrated circuit has the same behavior function on both platforms, so as long as there is an "initial state" of the component under test on the hardware simulation system, and the "input sequence can be reproduced on the software simulation system" The behavior of the device under test on the hardware simulation system (ie, the sequence of states and the sequence of outputs). This is the basis for the aforementioned simulation verification scheme combining hardware simulation and software simulation. Therefore, in order to reproduce the behavior of the analog component to be tested in the hardware simulation system, it is first necessary to obtain the "initial state", #" input sequence, from the hardware simulation system. "The input sequence can be obtained by copying the 1274011 of the test to be tested, so it is easier to implement, but the problem is how to get to the initial state" (this field generally refers to the process of obtaining the "initial state, the process is called snapshot". Snapshot. At present, the general practice in the industry is to connect the software simulation system and the hardware simulation system in a certain way, so that the circuit states can be mutually transmitted, so that the simulation can be switched between the two systems. Patent No. 5,937,179 (hereinafter referred to as the "No. 179"), when the hardware simulation error occurs, the test program is suspended, and the circuit of the device to be tested is constructed by using the scan chain (Scan_Chain) constructed by the backup register. The status is exported and input into the software simulation system. From the moment on the software simulation system, the test program is continued to run forward or backward, and the error is reproduced on the software simulation system and analyzed (see No. 179 Patent Specification No. 3) Lines 63 to 67 and 4th to 39th to 43rd.) However, there are still several shortcomings in this simulation method. First, the circuit state scan key is built with an additional scratch register to increase the number of integrated circuit gates, which increases the cost of the field programmable gate array (卯(}8) simulation, for very large integrated bodies. This is especially important in circuit design. Second, the simulation switches between software simulation and hardware simulation. The number of switching times is more, which reduces the simulation efficiency. Third, when an error occurs in the hardware simulation system, the error is analyzed. The best time for the cause has passed, and it is very difficult and impossible to achieve the "initial state" of the moment by running back the test program on the software simulation system. [Invention] Therefore, 'for simplified simulation verification' The efficiency of the simulation verification and the cost of simulation verification are reduced, and it is urgent to design a new simulation verification scheme. 1274171 The present invention provides a circuit state scan chain, including multiple temporary registers and each temporary storage. The corresponding input combination logic two combinational 1〇gic) and the output combination logic ((10) Incoming international logic). An output 埠 of each register is connected to an input 埠 of the corresponding two output combination logic, and the circuit state scan chain further includes a plurality of first multiplexers corresponding to the plurality of registers and a plurality of second multiplexers, wherein each of the registers is associated with a corresponding one of the first multiplexers and the corresponding one of the second multiplexers, the first multiplexer and the second multiplexer are respectively provided Two inputs 埠 and one output 埠. Wherein, the first input port of each first multiplexer is connected with the corresponding wheel 埠 of the register, and the second input 帛 of each ill ill is connected with the output of the previous register
接，各第一多工器的第一輸入埠和與之相應的暫存器所對 應的輸入端組合邏輯的輸出埠連接，各第二多工器的第二 輸入埠和與之相應的第一多工器的輸出埠連接，各第二多 工器的輸出埠和與之相應的暫存器的輸入埠連接，位於掃 描鏈最後的暫存器的輸出埠與掃描鏈上第一個暫存器所對 應的第一多工器的第二輸入埠連接。 本發明還提供一種利用上述電路狀態掃描鏈的一種資 料獲取系統’包括：快照控制模組（snapshQt e。咖㈣，通 過所述多個第一多工器和所述多個第二多工器，來控制所 述電路狀態掃描鏈的工作狀態（m〇de)。 如上所述的資料獲取系統，所述電路狀態掃描鏈的工 作狀態包括正常工作模式（normal mode)、保持模式（h〇iding m〇de)和快照模式（snapshot mode)。 在14所述的資料獲取系統中，快照控制模組内還設有 9 1274171 計數器（counter) ’用以控制所述電路狀態掃描鏈的暫存器的 值的移位（shift)次數。 本發明還提供一種利用如上所述的電路狀態掃描鏈或 資料獲取系統的模擬驗證方法，包括以下步驟··在測試程 式上設置多個檢測點；在硬體模擬系統上運行測試程式； 在運行測試程式的同時下載輸入資料；在檢測點處對電路 進仃快照；把電路狀態和輸入資料提供給軟體模擬系統， 在軟體模擬系統上重現待測元件在硬體模擬系統上的行 【實施方式】Connected, the first input port of each first multiplexer is connected with the output port of the input combination logic corresponding to the corresponding register, and the second input port of each second multiplexer and the corresponding The output of a multiplexer is connected, and the output 各 of each second multiplexer is connected to the input 埠 of the corresponding register, and is located at the output of the last register of the scan chain and the first temporary on the scan chain. The second input port of the first multiplexer corresponding to the register is connected. The present invention also provides a data acquisition system using the above-mentioned circuit state scan chain, including: a snapshot control module (snapshQt e. coffee), through the plurality of first multiplexers and the plurality of second multiplexers To control the working state of the circuit state scan chain (m〇de). As described above, the data state of the circuit state scan chain includes a normal mode and a hold mode (h〇iding) In the data acquisition system described in 14, the snapshot control module is further provided with a 9 1274171 counter (a counter for controlling the circuit state scan chain). The number of shifts of the value of the present invention. The present invention also provides a simulation verification method using the circuit state scan chain or data acquisition system as described above, including the following steps: setting a plurality of detection points on the test program; Run the test program on the body simulation system; download the input data while running the test program; take a snapshot of the circuit at the detection point; put the circuit status and input data A software simulation system, the simulation system software on the device under test lines on the reproduced hardware simulation system [Embodiment
本發明藉由改變待測元件的邏輯電路，將待測元件内 部的暫存n串聯成-條掃描鏈，料部㈣信號控制待測 兀件的工作模式（包括正常模式、快照模式及保持模式）。 另外，由於本發明的掃_首尾相連，當快照完成後，待 測元件的電路狀態隨即恢復成快照前的電路狀態。因此， 不需要額外的時間恢復待測元件的電路狀態，使得待測元 件可繼㈣❹丨試程式，提高了模擬紐的效率。 0_請=第1圖，第1圖為待測元件的原始邏輯的簡化 圖不°其包括N個暫存分別以lla、llb...lln#_、 及/、上述暫存0 11相應的輸入端組合邏輯 別 m.12n表示）與相應的輸出端組 以—，表示)。暫存器u具有輸入，阜(圖(; 不D端）與輸出琿（圖中所示Q端)，輸出埠的值即暫广 器所儲存的值，也就是暫存器的狀態。暫存器的特點在: 1274171 璋的值Γ 時，暫存器的輸出蟬的值就變成輪入 ，值。因此，想得到多個暫存器的值，只要把;= j成-條掃描鏈，再通過時脈的驅 二:: 者時脈把存館的值依次向前移位，鍵 器的輸出痒就可以接收到這 鍵取末4的暫存 八私士 霄畀态的值。如果不#用供 =備份待測元件的"個暫存器的值，就需要』： 的邏輯，在需要得到這些暫存器的值的時候： 二:暫存器串連成一條掃描鏈，利用婦 此 存"中料的代表電路狀態的資料輸出到外部。 :::2圖’第2圖是本發明待測元件的簡 比較，辦加了黛，肖待測几件的原始邏輯相 孕又“口了弟-多工器14 (分別以Μ 和第二多工器15 (分別以仏、15, Τ表不） 暫在哭nu泣 15n表不下面將以 时。η爲主體’舉例說明掃描鏈如何形成。第一多工 二 多工器15b分別有兩個輸入璋和一個輸出 —-夕―1工益15b的輸出埠與暫存器llb的輪入埠連接， 多工器15b的第-輸入埠與輸入端組合邏輯12 知連接，第二多工器15b的第二輸入璋與第一多工器^ 埠連接。第一多工器14b的第一輸入埠與暫存請 弟0^14b的第二輸入埠與前一個暫 子為Ha的輸出琿連接。處於掃描鏈最末端的暫存器⑴ 的輸出埠與處於掃描鏈的第一個暫存器、11a的第一多工器 的第一輸入埠連接，如此構成一個掃描鏈迴圈。 多工器14由移位致能（shiftenable)信號控制， 一多工器15由激發致能（str〇beenable)信號控制。這兩個 11 1274171 控制信號的組合與待測元件的工作模式的關係如下表所 示： 激發致能 移位致能 工作模式 0 0 正常模式 1 1 0 保持模式 1 1 快照模式By changing the logic circuit of the component to be tested, the temporary storage n inside the component to be tested is connected in series to a scan chain, and the material (4) signal controls the working mode of the component to be tested (including normal mode, snapshot mode and hold mode). ). In addition, since the scan of the present invention is connected end to end, when the snapshot is completed, the circuit state of the device to be tested is restored to the state of the circuit before the snapshot. Therefore, no additional time is required to restore the circuit state of the device under test, so that the component to be tested can follow the (4) test program, which improves the efficiency of the analog button. 0_Please=1, Figure 1 is a simplified diagram of the original logic of the device under test. It includes N temporary storages respectively lla, llb...lln#_, and /, the above temporary storage 0 11 corresponding The input combination logic is represented by m.12n) and the corresponding output group is represented by -,). The register u has an input, 阜 (figure (; not D terminal) and output 珲 (Q terminal shown in the figure), and the value of the output 埠 is the value stored by the temporary device, that is, the state of the temporary register. The characteristics of the memory are: 1274171 When the value of 璋 is ,, the value of the output 蝉 of the register becomes a round-in value. Therefore, if you want to get the values of multiple registers, just put ;= j into a scan chain, Then through the clock drive 2:: The clock of the store shifts the value of the store in turn, and the output of the button itch can receive the value of the temporary store of the key. If you use the value of the "register" of the device to be tested, you need the logic of ":" when you need to get the values of these registers: Second: the register is connected into a scan chain. The data of the representative circuit state of the female stock is output to the outside. :::2Fig. 2 is a simplified comparison of the components to be tested of the present invention, and the original logic of several pieces to be tested is added. In the same time, the younger brother-multi-worker 14 (respectively Μ and the second multiplexer 15 respectively (仏, 15, Τ 不 ) ) 暂 暂 暂 暂 暂 暂 暂 暂 暂 暂 nu nu nu nu nu nu nu nu nu nu nu nu nu nu nu nu nu nu η is the main body' exemplifies how the scan chain is formed. The first multiplexer 2 multiplexer 15b has two input ports and one output respectively - the output of the eve 1 work 15b and the wheel 埠 connection of the register llb The first input port of the multiplexer 15b is connected to the input combination logic 12, and the second input port of the second multiplexer 15b is connected to the first multiplexer. The first input of the first multiplexer 14b第二 and the temporary input 0^14b's second input 埠 is connected to the previous temporary sub-interface Ha. The output 埠 of the scratchpad (1) at the end of the scan chain and the first register in the scan chain The first input 埠 of the first multiplexer of 11a is connected to form a scan chain loop. The multiplexer 14 is controlled by a shift enable signal, and a multiplexer 15 is activated by excitation (str〇 Beenable signal control. The relationship between the combination of these two 11 1274171 control signals and the operating mode of the device under test is as follows: Excitation enable shift enable mode 0 0 Normal mode 1 1 0 Hold mode 1 1 Snapshot mode
當激發致能爲0時，第二多工器15選擇第一輸入埠的 輸入（即輸入端組合邏輯12的輸出）作爲輸出，第一多工 器14的輸出不被選擇，此時，待測元件回復原始的邏輯功 能，工作模式處於正常的模式下。 當激發致能爲1且移位致能爲0時，第二多工器15選 擇第二輸入埠的輸入（即第一多工器14的輸出）作爲輸出； 第一多工器14則選擇第一輸入埠的輸入（即當時對應該多 工器14之暫存器11的輸出）作爲輸出。此時，這暫存器 的值保持不變，待測元件工作處於保持模式。何時需要待 測元件工作在此模式下將在下文進行說明。 當激發致能爲1且移位致能爲1時，第二多工器15選 擇第二輸入埠的輸入（即第一多工器14的輸出）作爲輸出； 第一多工器14則選擇第二輸入埠的輸入（即前一個暫存器 11的輸出）作爲輸出。此時，隨著系統時脈，各暫存器的 值在掃描鏈中向前移位，在掃描鏈末端的輸出埠根據該時 脈採樣得到這些暫存器的值。經過N個時脈後，得到所有 暫存器的值，且所有暫存器的值恢復到移位元以前的狀態。 接著，請參考第3圖，第3圖是本發明資料獲取系統 12 1274171 的簡化硬體圖不。該資料獲取系統包括採集電路狀態（即 初始狀心）貝料的部分與輸入（即輸入序列）資料的部分。 第3圖中待測元件（DUT) 1的輸人信號被引至編碼器3, 該輸入信號經過編碼器3的編碼1縮後輸出至第三多工器 4。快照控制模組2控制待測元件1在何種工作模式下，同 時控制所述的編碼器3以及第三多工器4的工作。因爲未 採用備份暫存器構建掃描鏈，所以快照與測試不能同時進 行。^言之，電路狀態資料與輸入資料的上傳不會在時間 上重疊1 了節省硬體開銷降低成本，本發明的實施例利 用同-f料通道使得讓通過第三多工器4的電路狀態資料 與輸入貝料上傳外部設備，然而也可以採用兩條資料 分開上傳。 、 只有精確地控制掃描鏈1〇的移位次數才能得到正確的 電路狀態資料並且在快照完成後使暫存器n恢復快照前的 狀態。首先，要明確掃描鏈1〇由多少個暫存器u構成， 這可通過一些邏輯分析軟體對待測元件的rtl c〇de進行 为析來完成（這是本領域公知的技術手段）。其次，是對掃 描鏈10移位元次數的精確控制，這是由快照控制模=2 = 所設的計數器21纟完成的。軟體把表示暫存器數量的值賦 給計數器21，快照開始後，掃描鏈1〇開始移位，每進行一 次移位，計數器21就把所賦的值減一，當計數器21 =值 成爲0時說明快照完成並且暫存器恢復快照前的狀態。這 時快照控制模組2通過激發致能和移位致能兩個信二控= 停止快照。 資料獲取系統在上傳資料時可能會發生溢出等錯誤， 13 1274171 i«需輸出’否則自發生溢出至 消除期間，掃描鏈輸出的資料將會丢失，導致最終When the excitation enable is 0, the second multiplexer 15 selects the input of the first input ( (ie, the output of the input combination logic 12) as an output, and the output of the first multiplexer 14 is not selected. The test component returns to the original logic function and the operating mode is in normal mode. When the excitation enable is 1 and the shift enable is 0, the second multiplexer 15 selects the input of the second input ( (ie, the output of the first multiplexer 14) as an output; the first multiplexer 14 selects The input of the first input port (i.e., the output of the register 11 corresponding to the multiplexer 14 at that time) is output. At this point, the value of this register remains unchanged and the device under test is in hold mode. When the component under test needs to work in this mode will be explained below. When the excitation enable is 1 and the shift enable is 1, the second multiplexer 15 selects the input of the second input ( (ie, the output of the first multiplexer 14) as an output; the first multiplexer 14 selects The input of the second input port (i.e., the output of the previous register 11) is taken as an output. At this time, with the system clock, the values of the registers are shifted forward in the scan chain, and the output at the end of the scan chain is sampled according to the clock to obtain the values of these registers. After N clock cycles, the values of all the registers are obtained, and the values of all the registers are restored to the state before the shift elements. Next, please refer to FIG. 3, which is a simplified hardware diagram of the data acquisition system 12 1274171 of the present invention. The data acquisition system includes the acquisition of the state of the circuit (i.e., the initial centroid) and the portion of the input (i.e., input sequence) data. The input signal of the device under test (DUT) 1 in Fig. 3 is led to the encoder 3, which is outputted to the third multiplexer 4 by the code 1 of the encoder 3. The snapshot control module 2 controls the operation mode of the device under test 1 and controls the operation of the encoder 3 and the third multiplexer 4. Because the scan chain is not built with a backup scratchpad, snapshots and tests cannot be done at the same time. In other words, the uploading of the circuit state data and the input data does not overlap in time. 1 Save the hardware overhead and reduce the cost. The embodiment of the present invention utilizes the same-f material channel to make the circuit state through the third multiplexer 4 Data and input beakers are uploaded to external devices, but they can also be uploaded separately using two pieces of data. Only the number of shifts of the scan chain 1〇 can be accurately controlled to get the correct circuit state data and the scratchpad n can be restored to the state before the snapshot after the snapshot is completed. First, it is necessary to clarify how many scratchpads u are formed by the scan chain, which can be done by some logic analysis software rtl c〇de of the device to be tested (this is a technical means known in the art). Secondly, it is the precise control of the number of shifting elements of the scan chain 10, which is done by the snapshot control mode = 2 = set counter 21纟. The software assigns a value indicating the number of registers to the counter 21. After the snapshot starts, the scan chain 1〇 starts to shift. Each time the shift is performed, the counter 21 decrements the assigned value by one, when the counter 21 = the value becomes 0. Indicates the state that the snapshot is complete and the scratchpad is restored before the snapshot. At this time, the snapshot control module 2 enables two signals to control the activation and shifting to stop the snapshot. The data acquisition system may overflow or other errors when uploading data, 13 1274171 i«requires output, otherwise the data output from the scan chain will be lost during the erasure period, resulting in the final result.
並非完整的電路狀態資料。本發明的掃描鏈中的第一多工 器14及第二多工器15的組合可以克服這個難題。當；： 上傳通道發生溢出錯誤或者發生其他導致暫時無法接收資 料的情況時，㈣將發送信號給快照㈣模組2,快照控: 模組2使激發致能信號爲卜使移位致能信號爲q，此日工夺， 暫存器11的輸出埠與輸人埠連接，暫存器的值保持不變。 系統恢復正常後再繼續輸出掃描鏈中暫存器的資料。 另外，電路狀態資料包括了暫存器狀態與記憶體（如 SRAM)的内谷’則文主要描述如何獲得暫存器的值，這也 是本發明的重點所在，至於記憶體的内容可通過讀取操作 獲侍，此爲業界一般技術人員所知，故在此不進行贅述。 以上主要對本發明的掃描鏈結構進行描述，後文將對 本發明的模擬驗證方案進行說明。請參考第4圖，第4圖 是本發明在測試程式上設置檢測點的示意圖。首先，根據 貫際情況在測試程式上設置多個測試點，如圖中的A、B、 C D、E，這些測試點是進行快照的標誌（測試程式是在 硬體模擬系統中運行）；當測試程式運行到這些測試點的時 候，系統暫停對待測元件的輸入，同時把激發致能信號置 1，把移位致能信號置〇，這時電路狀態保持不變；當系統 準備好輸出電路狀態資料時，再把移位致能信號置丨，這時 掃描鍵10中暫存器n的值開始移位；電路狀態資料輸出 完成後’恢復系統對待測元件的輸入，同時把激發致能置 1 ’使待測元件恢復原來的邏輯功能，測試程式繼續運行。 1274171 整個測試程式結束後，輸入序列以及A、B、C、D、E五個 測試點的電路狀態都已被記錄。若硬體模擬在c和d之間 發生了一個錯誤，就把C點的電路狀態導入軟體模擬系 統，同時把C和D點之間的輸入序列提供給軟體模擬系 統，如此，軟體模擬系統就能夠重現這段測試程式在硬體 模擬系統上的運行狀況。從而可利用軟體模擬的電路狀態 全可見性對發生的錯誤進行詳細地分析。顯然，這種模擬 驗證方案不會錯失對錯誤進行具體分析的時機，不管錯誤 發生在何時，只要把發生錯誤前的一個測試點的電路狀態 及對應的輸入序列導入軟體模擬系統即可。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 濩範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ·Not complete circuit status data. The combination of the first multiplexer 14 and the second multiplexer 15 in the scan chain of the present invention overcomes this dilemma. When:: The upload channel overflow error or other circumstances that cause the data to be temporarily unavailable, (4) Send the signal to the snapshot (4) Module 2, Snapshot control: Module 2 makes the excitation enable signal be the shift enable signal For q, this day, the output of the register 11 is connected to the input port, and the value of the register remains unchanged. After the system returns to normal, continue to output the data of the scratchpad in the scan chain. In addition, the circuit state data includes the state of the scratchpad and the inner valley of the memory (such as SRAM). The text mainly describes how to obtain the value of the scratchpad, which is also the focus of the present invention. As for the contents of the memory, the content can be read. The operation is granted, which is known to those of ordinary skill in the art, and therefore will not be described herein. The scanning chain structure of the present invention is mainly described above, and the simulation verification scheme of the present invention will be described later. Please refer to FIG. 4, which is a schematic diagram of the present invention for setting a detection point on a test program. First, set up multiple test points on the test program according to the situation, such as A, B, CD, and E in the figure. These test points are the marks for taking snapshots (the test program is run in the hardware simulation system); When the test program runs to these test points, the system suspends the input of the component to be tested, and sets the excitation enable signal to 1 to set the shift enable signal, and the circuit state remains unchanged; when the system is ready for output circuit state When the data is used, the shift enable signal is set, and the value of the register n in the scan key 10 starts to shift; after the circuit state data is output, the input of the system to be tested is restored, and the excitation enable is set. 'Restore the device under test to restore the original logic function, and the test program continues to run. 1274171 After the entire test program is completed, the input sequence and the circuit states of the five test points A, B, C, D, and E have been recorded. If the hardware simulation has an error between c and d, the circuit state of point C is imported into the software simulation system, and the input sequence between points C and D is supplied to the software simulation system. Thus, the software simulation system Can reproduce the running status of this test program on the hardware simulation system. This makes it possible to analyze the errors that occur in detail using the full state visibility of the circuit state of the software simulation. Obviously, this analog verification scheme does not miss the timing of the specific analysis of the error, no matter when the error occurs, just input the circuit state of the test point before the error and the corresponding input sequence into the software simulation system. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is subject to the definition of the scope of the patent application. [Simple description of the diagram]
為讓本發明之上述和其他目的、特徵、優點與實施例 能更明顯易懂’所附圖式之詳細說明如下·· 第1圖爲待測元件的原始邏輯的簡化圖示。 。第2圖爲本發明之一較佳實施例之待測元件的簡化邏 簡 第3圖爲本發明之一 化硬體圖示。 較佳實施例之資料獲取系統的 第4圖爲本發明 才欢測點的不意圖。 之一較佳實施例之在測試程式上設置 15 1274171 【主要元件符號說明】 I : 待測元件 2 ： 快照控制模組 3 : 編碼器 4 : 第三多工器 10 : 信號置掃描鏈 II ( 11a〜11η):暫存器 12 ( 12a〜12η):輸入端組合邏輯 13 ( 13a〜13η):輸出端組合邏輯 14 ( 14a〜14η) ··第一多工器 15 ( 15a〜15η):第二多工器 21 ：計數器The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; . Figure 2 is a simplified logic diagram of the device under test in accordance with a preferred embodiment of the present invention. Figure 3 is a simplified hardware diagram of the present invention. Fig. 4 of the data acquisition system of the preferred embodiment is a schematic view of the present invention. In a preferred embodiment, 15 1274171 is set on the test program. [Main component symbol description] I : Component under test 2 : Snapshot control module 3 : Encoder 4 : Third multiplexer 10 : Signal scan chain II ( 11a~11n): register 12 (12a~12n): input combination logic 13 (13a~13n): output combination logic 14 (14a~14n) ··first multiplexer 15 (15a~15η): Second multiplexer 21: counter
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