1272731 九、發明說明： 【發明所屬之技術領域】 本發明係有關於發光二極體之封裝結構。特別是有關於利 用輔助框架形成一穿透之u型腔室用以容納一片倒置晶片之 led形成疊置封裝模組，再銲接於一塊紹質pc板上以獲得到 達PC良好之熱傳導而增強發光強度之封裝結構。 ' 【先前技術】 為增加LED之發光強度，以往在使用之複合材料上作廣泛 之研九’同日守亦對元件之結構加以變化，例如利用雙昱質接 面，量子井或多重量子井等，使發光強度在近年大幅提升至十 數倍。因此LDE使用場合愈來愈多，由指示燈到交通號諸、[ED 列印頭之感光源、LED顯示器、車輛之方向燈，甚至LE^S明。 然而，發光強度卻受限於接面崩潰，而接面崩潰大都肇因於接 面之過熱，所以散熱成為增進發光強度之重要手段。、 方去散熱亦影響至大’一般將晶粒底部以晶焊 方法¥接至封裝基座上，再以打線將正、負電 正、負接腳上，熱傳導路線不但太長，而且金線之 ^ ί定’以能將所生之熱與散熱達到平衡而 奴”最大電’亦即最大發光強度。因而目前之led仍 =燈明、室内照明等，仍殷切希望能替代耗電 因此有一需求，於⑽之封裝技術上能大而 而提高發光強度。本發_情此-需求，如力 1272731 【發明内容】 裝結發光二極體⑽）無打線之封 納-片倒置晶片 助穿透之ϋ型腔室（Cavity)以容1272731 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a package structure of a light-emitting diode. In particular, there is a method for forming a penetrating u-shaped chamber by using an auxiliary frame for accommodating a piece of inverted wafer to form a stacked package module, and soldering it to a piece of PCB board to obtain good heat conduction to the PC and enhancing illumination. Intensive packaging structure. [Prior Art] In order to increase the luminous intensity of LEDs, the past has been widely used in composite materials. The same day, the same structure changes the structure of components, such as the use of double tantalum junctions, quantum wells or multiple quantum wells. In order to increase the luminous intensity to a dozen times in recent years. Therefore, LDE is used more and more, from the indicator light to the traffic number, [the light source of the ED print head, the LED display, the direction light of the vehicle, and even LE^S. However, the luminous intensity is limited by the collapse of the joint, and the collapse of the joint is mostly due to the overheating of the joint, so heat dissipation is an important means to enhance the luminous intensity. The heat dissipation of the square also affects the large size. Generally, the bottom of the crystal grain is connected to the package base by the crystal welding method, and the positive and negative electric positive and negative pins are connected by the wire. The heat conduction route is not only too long, but also the gold wire. ^ 定定' in order to balance the heat and heat generated by the slave, the "maximum electricity" is the maximum luminous intensity. Therefore, the current LED is still = light, indoor lighting, etc., still eager to replace power consumption, so there is a demand, The packaging technology of (10) can greatly improve the luminous intensity. The present invention is in need of a light-emitting diode (10)) without a wire-bonding device. Cavity to accommodate
塊紹質PC二，以—f^倒置晶片表秘裝技術銲接於— 太旅日a々4獲侍良好之熱傳導而增加發光強度。 之封梦Γ士拔-人一目的在提供一種發光二極體（LED)無打線 ，巧籌，利用利用一片石夕辅助 型、:J 片倒置晶片之®’再以倒置晶片 m ΐ ^上，㈣魏好之熱傳導㈣加發光強度。 訂展、…構將LED晶片以倒置晶片 u型腔Ϊ内接（diebonding)在石夕晶輔助框架内之 封f 置封裝她。再將此触關置晶片表面 有u 之銘製pc板上，至少包含：一個石夕晶輔 ，=(1 nt)，在正面形成正電極及㈣極之銲錫凸Ξ r m 刻穿透石夕晶片之u型腔室以供容納 =片，利用侧時之自然遮罩在腔室内蒸鑛正、負電極及 片發光二極體（LED)晶片，可為一般習知技術製 以之曰曰片，具有基板、一個發光主動區，在正面有一個正 負電極，二# PC板，具有一層陽極氧化層，印刷電路、 μ frf置；將前述LED晶片以倒裝晶片方式焊接於前述石夕晶 ，助框采内，LED晶片之正電極及負電極分別對準石夕晶辅助框 狀正電極及負電極，形成疊置封裝模組；將前述疊 組以倒置⑼表面封裝於前述PC板上，在LED 個微凸透鏡。 办欣 J發明之以上及其他目的及優點參考以下之參照圖示及 取佳實施例之說明而更易完全暸解。 【實施方式】 6 1272731 ^發明之封裝結構之製造程序可參考第丨圖至第7圖而了解。 第1圖為依據本發明之實施例之矽輔助框架（submount)之晶 片製造程序示意圖。首先如第1圖（A)所示，第1圖（a)為在 石夕晶片上形成對準記號及接觸窗步驟之剖面圖。準備一片p 型、（100)方向、不限掺雜濃度，甚至為回收晶片之矽晶片作 ^基板102，於石夕基板102上，以LPCVD在正、反面沉積一層 氮化石夕（silicon nitride)層104，在正面以第一光罩微影 姓刻形成負極接觸窗106、正極接觸窗1〇8及步進機(stepper) 之對準記號110。參考第1圖（B)，第1圖（幻為形成銲錫凸塊 步驟之剖面圖。以蒸鍍(evaporati〇n)及第二光罩微影蝕刻形 成負極銲錫凸塊116、正極銲錫凸塊丨18、步進機( ） 對準記號H0之封口 114及反面對準記號（bad^ide aligner，BSA)112。參考第1圖（〇，第1圖為形成u型腔 室（Cavity)步驟之剖面圖。自背面以第三光罩開蝕刻窗12〇、 負電極區蝕刻窗120-1、正電極區蝕刻窗12〇—2，以便進行穿 透之蝕刻以形成u型腔室，此時預留有自然遮罩（native shadowmask) 122，作為沉積鋁金屬時形成隔離之遮罩，而避 免-巧侧步驟。織進行異向性（anis〇tiOpic)整體微機 電技術（bulk micromachining)形成一個穿透石夕晶片之u型 腔至121 ^此11型腔室121將用來容納led晶片。此時，矽基 =面之氮化碎層1〇4形成-鼓膜，支持其上之銲錫凸塊 116、118。矽基板反面之氮化矽自然遮罩122以鼓膜型式被保 留作沉積銘之遮罩（mask)。第丨圖⑼為第三光罩之一實施 例。此光罩有自然遮罩122、反射之金屬鏡面區12〇、負電極 區12〇一卜正電極區120一2。第1圖⑻為第三光罩之另一實施 此光罩有自然遮罩122、反射之金屬鏡面區12〇、圓形之 I電極卜圓形之正電極· 12〇一2，以便形成柱形之正 電極及負电極，以減少熱膨脹對封裝之影響。如第1圖（F)所 不。第1圖(F)為進行紹金屬蒸鍍（evaporation)步驟之示意 7 1272731 因鎗蒸鍍為宜’不能用濺鍍或化學氣相沉積，否 鍍為使1有電極皆相連而不能形成隔離。電子鎗蒸 tfff、源(PQlnt S嶋）。蒸鍍之方向為128，並無其它 負i桎ιί遮it/22之下陰影部份不被蒸鍍而形成隔離之正、 !ΤΪ 及反射之金屬鏡面130。如第1圖⑹所示。 金屬鍍完後碎基版之剖面圖。在第三光罩之反射之 負電ϊ區&=之下形成反射之金屬鏡面130、在第三光罩之 120-2^之下形成負電極126、在第三光罩之正電極區 开Μ二Τ形成正電極124。在第三光罩之自然遮罩122之下 、ί去S 。ί鍛完後石夕基版102之自然遮罩122可用機械 成容議晶片之具有U型腔室之條框 曰片ί ΐ ?!?1严2圖係倒裝晶片之LED晶片之剖面圖。⑽ 曰曰曰ί ^ ί造，如紅色、藍色、綠色或其他顏色。· 日日片200有一透明基板2〇2，例如藍 ^^上有蟲晶形狀ΡΝ接面204或量子井之^發光區。 f ^層上有正電極208,負電極於侧去除Ρ型層到達 層之後，形成負電極206而成到置晶片之狀態。 加參考第3圖（A)，第3圖(A)係將LED晶片置入石夕輔助框 =之U型腔室内以倒置晶片封裝法形成之混合封裝焊H 纠面圖。將Lro晶片200倒轉’使之正電極2〇8對準 f框架100之金屬正電極126 ’ LED之負電極206對準石夕辅助 框架100之金屬負電極124，然後加熱焊接成混合封裝 =上之銲錫凸塊116、118可卿懷晶片方式封裝於印刷電 路板上。自LK)發射之光302穿過透明基板2〇2而發射。 反射金屬鏡面128之光304再反射而出，以增強亮度。 圖（B)為矽輔助框架之金屬正、負電極與LED晶片之正、 電極之關係位置圖。矽輔助框架之金屬正、負電極124、126 為較寬之交叉指狀電極，LED晶片上之正、負電極2〇8、2〇6 1272731 則為較窄之交叉指狀電極。第3圖（c)為另一實施例石夕輔助 框架之金屬正、負電極與LED晶片上之正、負電極之關係位置 圖。石夕輔助框架之金屬正、負電極124、126為為圓柱形陣列 電極，LED晶片上之正、負電極208、2〇6則為較窄之交叉指 狀電極。 參考® 4圖，g 4圖係贿明歸形絲紐鏡之剖面 圖。以透明塑膠402滴入U型腔室121之空隙内，使LED曰M 200與石夕辅气框架100更密切结合。為使光線能聚焦在^曰表 二透明胸滅-個微凸透鏡(mi⑽lens) 拋物面以形成聚紐鏡，使光線聚焦向前Γ出 ί切過之碎晶圓102、正面及反面之氮化 曰^切面之負極鲜锡凸塊116及正極鮮錫凸塊118，將 日日圓切成晶片。 ¥= i i第5圖係將混合封裝之LED晶片及補助框 Ϊ年使二2式焊接於銘質PC板上之剖面圖。1呂f PC板係 -异自料具有散熱良好之優點。銘f PC板502上有 oxi曰加)5二1^陽極處理形成之自然陽極氧化層(native 正電絕緣之用’在氧化層刪上製成印刷電路，如 5〇2背面有气電極電路518 ’係銅膜之電路。紹質兕板 合體以倒裝晶片方式將銲接凸塊n8、m 上，使正^雷=八〇板502之正電極電路508、負電極電路518 控制電路3圖1由接線塾51G、512及打線514、516連至 下發光。由认Γ不）之正、負電源（未圖示）。LED即在控制 傳i，較習接面散熱片之距離甚短，獲得良好之熱 不上升，因二封裝方式能耐更大之電流，PN接面之溫度仍 :f而増加發光 以倒裝:以封=圖=合裝之LED晶片及矽辅助框架 八封裝在一般PC板上之剖面圖。此裝置之封裝 9 1272731 模組先封裝在-般PC板602上，PC板·上有金 604。將LED晶片200及石夕辅助框架⑽之混合體以倒 方式將銲接凸塊118、116分別焊接於一般pC板6〇2之 電路608、負電極電路618上，再將LED晶片2〇〇 架100及PC板602連接在紹質散熱裝置62〇上。銘 置620上有鰭狀散熱片624。PC板602上之正負電極分別^ 線墊610、612及打線614、616連至控制電路（未圖示）接 負電源（未圖示）。LED即在控制下發光。金屬導敎 、 :將熱快速傳導，亦較習知之封裝方式能 接面之溫度仍不上升，因而增加發光強度。 混合封裝之LED晶片及矽辅助框架亦可以用倒 基赴。利用—般接腳有限之散熱能力， 哭之才ΐίί考ilL第7圖係依據本發明之實施例形成顯示 ^之構4圖。在矽基板上形成穿透之蝕刻U型腔室 、土三色晶片702、704、706倒轉混合封裝於u型 月工至，列中，以形成顯示器之構造。 生 藉由以上較佳之具體實施例之詳述，係希望能加 精神，並相上麟揭露陳佳具體實^ 鱗加以限制。相反的，其目的是希望能涵蓋各 種改文及具相等性的安排於本發明所欲申請之專利範嘴内二 【圖式簡單說明】 (subm〇unt) 剖面_。丨_(A)為在♦晶卩上形成對準記號及接觸窗步驟之 ^圖⑻為形成銲錫凸塊步驟之剖面圖。 圖（c)為形成U型腔室（Cavity)步驟之剖面圖。第 1272731 6圖係倒裝晶片之led晶片之剖面圖。 弟1圖（D)為第三光罩之一實施例。 弟1圖（E)為第三光罩之一實施例。 弟1圖（F)為進行銘金屬蒸鍍（evaporation)步驟之示音 圖。 心 第1圖（G)為蒸鍍完後矽基版之剖面圖。 ，2圖係倒裝晶片之LED晶片之剖面圖。 第3圖（A)係將LED晶片置入石夕輔助框架之u型腔室內 倒置，片封裝法形成之混合封裝焊接後之剖面圖。The block is the second PC, and the -f^ inverted wafer table secret technology is soldered on - the travel time is a good heat transfer to increase the luminous intensity. The purpose of the dream is to provide a kind of light-emitting diode (LED) without wire, and to make use of a piece of stone-assisted type: the chip of the inverted chip of 'J' and then inverted the chip m ΐ ^ (4) Wei Hao's heat conduction (4) plus luminous intensity. The exhibition, the LED wafer is packaged in an inverted wafer u-cavity, which is diebonded in the Aussie auxiliary frame. Then touch this on the surface of the wafer with the u-shaped pc board, including at least: a Shi Xijing, = (1 nt), forming a positive electrode on the front side and a (four) pole solder bump rm through the Shi Xi wafer The u-shaped chamber is used for accommodating the slab, and the normal or negative electrode and the illuminating diode (LED) wafer are vaporized in the chamber by the natural mask on the side, which can be made by the conventional technique. , having a substrate, a light-emitting active region, a positive and negative electrode on the front side, a ##PC board having an anodized layer, a printed circuit, and a μfrf; the LED chip is flip-chip bonded to the aforementioned Shi Xijing, In the frame, the positive electrode and the negative electrode of the LED chip are respectively aligned with the auxiliary electrode and the negative electrode of the Sihuajing auxiliary frame to form a stacked package module; the stack is mounted on the PC board with an inverted (9) surface. In the LED micro convex lens. The above and other objects and advantages of the invention will be more fully understood from the following description of the drawings and the description of the preferred embodiments. [Embodiment] 6 1272731 The manufacturing procedure of the package structure of the invention can be understood by referring to the drawings to FIG. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a wafer manufacturing process of a submount in accordance with an embodiment of the present invention. First, as shown in Fig. 1(A), Fig. 1(a) is a cross-sectional view showing the steps of forming an alignment mark and a contact window on a stone wafer. Prepare a p-type, (100) direction, unlimited doping concentration, and even a wafer for recycling the wafer as a substrate 102. On the Shixi substrate 102, a layer of silicon nitride is deposited on the front and back sides by LPCVD. The layer 104 forms a negative contact window 106, a positive contact window 1〇8, and an alignment mark 110 of a stepper on the front side with a first mask lithography. Referring to FIG. 1(B), FIG. 1 is a cross-sectional view showing the steps of forming a solder bump. The negative solder bump 116 and the positive solder bump are formed by evaporation and second photomask etching.丨18, stepper ( ) Alignment mark H0 seal 114 and reverse face alignment mark (bad^ide aligner, BSA) 112. Refer to Figure 1 (〇, Figure 1 shows the formation of u-type chamber (Cavity) A cross-sectional view of the step: a third mask opening etching window 12 〇, a negative electrode region etching window 120-1, and a positive electrode region etching window 12 自 2 from the back surface for etching etching to form a u-type chamber, At this time, a natural shadow mask 122 is reserved, which forms an isolated mask when depositing aluminum metal, and avoids the side step. Weaving anisotropic (anis〇tiOpic) bulk micromachining (bulk micromachining) Forming a u-shaped cavity penetrating the lithographic wafer to 121. The 11-type chamber 121 will be used to accommodate the led wafer. At this time, the cerium-based nitriding layer 1 〇 4 forms a tympanic membrane, which is supported thereon. Solder bumps 116, 118. The tantalum nitride natural mask 122 on the reverse side of the substrate is retained as a deposition mask in the tympanic pattern. (Mask) (9) is an embodiment of the third reticle. The reticle has a natural mask 122, a reflective metal mirror area 12 〇, and a negative electrode area 12 〇 a positive electrode area 120-2. 1 (8) is another implementation of the third reticle. The reticle has a natural mask 122, a reflective metal mirror area 12 〇, a circular I electrode, a circular positive electrode, 12 〇 2, to form a cylindrical shape. The positive electrode and the negative electrode are used to reduce the influence of thermal expansion on the package. Figure 1 (F) does not. Figure 1 (F) shows the step of performing the evaporation step 7 1272731 by gun evaporation It is advisable that it can't be sputtered or chemical vapor deposited, or it can be plated so that no electrodes are connected and can not form isolation. The electron gun steams tfff, source (PQlnt S嶋). The direction of evaporation is 128, there is no other negative The shaded portion under 桎ιί itit/22 is not vapor-deposited to form a positive, ΤΪ and reflective metal mirror 130. As shown in Figure 1 (6), a cross-sectional view of the broken base after metal plating. a metal mirror 130 that forms a reflection under the negative electric ridge region &= of the third reticle, and a negative electricity under the 120-2^ of the third reticle The pole 126 is opened in the positive electrode region of the third mask to form a positive electrode 124. Under the natural mask 122 of the third mask, ί goes to S. After the forging, the natural cover of the Shi Xiji version 102 The cover 122 can be mechanically formed into a frame of a U-shaped chamber with a U-shaped cavity. The image of the LED chip of the flip-chip is (10) 曰曰曰ί ^ 造, such as red , blue, green or other colors. The solar sheet 200 has a transparent substrate 2〇2, for example, a blue crystal having a serpentine shape splicing surface 204 or a quantum well. The f^ layer has a positive electrode 208, and after the negative electrode removes the Ρ-type layer to the layer on the side, the negative electrode 206 is formed to be in a state of being placed on the wafer. Referring to FIG. 3(A), FIG. 3(A) shows a hybrid package solder H correction pattern formed by an inverted wafer package method in which an LED chip is placed in a U-shaped cavity. Inverting the Lro wafer 200 'aligns the positive electrode 2〇8 with the metal positive electrode 126 of the f-frame 100'. The negative electrode 206 of the LED is aligned with the metal negative electrode 124 of the stone-assisted frame 100, and then heat-welded into a hybrid package=upper The solder bumps 116, 118 can be packaged on a printed circuit board in a wafer-like manner. Light 302 emitted from LK) is emitted through the transparent substrate 2〇2. The light 304 of the reflective metal mirror 128 is then reflected back to enhance brightness. Figure (B) is a diagram showing the relationship between the positive and negative electrodes of the metal of the 矽 auxiliary frame and the positive and the electrodes of the LED chip. The metal positive and negative electrodes 124 and 126 of the auxiliary frame are wide interdigitated electrodes, and the positive and negative electrodes 2〇8 and 2〇6 1272731 on the LED chip are narrow interdigitated electrodes. Fig. 3(c) is a view showing the relationship between the metal positive and negative electrodes of the Shixi auxiliary frame and the positive and negative electrodes on the LED chip of another embodiment. The metal positive and negative electrodes 124 and 126 of the Shixi auxiliary frame are cylindrical array electrodes, and the positive and negative electrodes 208 and 2〇6 on the LED chip are narrow interdigitated electrodes. Refer to Figure 4, g 4 for a cross-sectional view of the bristle-shaped wire-shaped mirror. The transparent plastic 402 is dropped into the gap of the U-shaped chamber 121 to more closely bond the LED 曰M 200 to the Shixi auxiliary gas frame 100. In order to make the light focus on the transparent chest-a micro-convex lens (mi(10)lens), the paraboloid is formed to form a clustering mirror, so that the light is focused and forwarded out. The chip 102, the front and back sides of the tantalum nitride are cut. The negative electrode tin bump 116 and the positive electrode tin bump 118 of the cut surface are cut into wafers. ¥= i i Figure 5 is a cross-sectional view of a hybrid packaged LED chip and a supplementary frame. 1 Lu f PC board system - different materials have the advantage of good heat dissipation. Ming f PC board 502 has oxi曰 plus) 5 2 1 ^ anodized to form a natural anodized layer (native positive electrical insulation used in the oxide layer to make a printed circuit, such as 5 〇 2 back gas electrode circuit 518 'The circuit of the copper film. The 兕 兕 合 合 以 以 绍 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接 焊接1 Connected to the lower side by the wiring ports 51G, 512 and the wires 514, 516. The positive and negative power supplies (not shown) are not recognized. The LED is in the control pass, the distance from the heat sink is very short, and the good heat does not rise. Because the second package can withstand more current, the temperature of the PN junction is still f: plus the light to flip: A cross-sectional view of the LED chip and the 矽 auxiliary frame eight packaged on a general PC board in the form of a seal = figure. The package of this device 9 1272731 The module is first packaged on a general PC board 602, and the PC board has a gold 604. The solder bumps 118 and 116 are respectively soldered to the circuit 608 of the general pC board 6〇2 and the negative electrode circuit 618 in a reverse manner, and the LED chip 2 is trussed. The 100 and PC board 602 are connected to the heat sink 62 〇. There is a fin fin 624 on the name 620. The positive and negative electrodes on the PC board 602 are connected to a control circuit (not shown) via a power supply line (not shown) for connecting the wire pads 610 and 612 and the wires 614 and 616, respectively. The LED is illuminated under control. Metal guides: : Conduct heat quickly, and the temperature of the junction can be increased compared with the conventional packaging method, thus increasing the luminous intensity. Mixed-packaged LED chips and 矽 auxiliary frames can also be used with inverted substrates. Using the limited heat dissipation capability of the general-purpose pin, the crying of the ilL is shown in Fig. 7 to form a display 4 according to an embodiment of the present invention. A etched U-shaped chamber, a three-color wafer 702, 704, 706, which is formed to penetrate through the ruthenium substrate, is inverted and packaged in a u-shaped column to form a display structure. With the detailed description of the preferred embodiments above, it is hoped that the spirit will be added, and that Lin will reveal the limitations of Chen Jia. On the contrary, the purpose is to cover various kinds of texts and equal arrangements in the patent nozzles of the present invention. [Subm〇unt] section _.丨_(A) is a step of forming an alignment mark and a contact window on the ♦ wafer. FIG. 8 is a cross-sectional view showing a step of forming a solder bump. Figure (c) is a cross-sectional view showing the step of forming a U-shaped cavity. Section 1272731 6 is a cross-sectional view of a flip chip of a flip chip. Figure 1 (D) is an embodiment of a third reticle. Figure 1 (E) is an embodiment of a third reticle. Figure 1 (F) is a sound map for performing the evaporation process of the metal. Heart Figure 1 (G) is a cross-sectional view of the ruthenium plate after vapor deposition. 2 is a cross-sectional view of an LED chip of a flip chip. Fig. 3(A) is a cross-sectional view showing the LED chip placed in the u-cavity chamber of the Shixi auxiliary frame and inverted, and the mixed package formed by the sheet encapsulation method is welded.
第3圖（B)為矽辅助框架之金屬正、負電極與led晶片上 之正、負電極之關係位置圖。 第3圖（C)為另一實施例矽辅助框架之金屬正、負電極與 LED曰=曰片上之正、負電極之關係位置圖。、/、 第4圖係以透明塑膠形成聚焦透鏡之剖面圖。 第5圖係將混合封裝之㈣晶片及矽輔助框架以倒 方式焊接於I呂質PC板上之剖面圖。 i圖係將混合裝之LED晶片及補助框架以倒裝晶片方 式封裝在一般PC板上之剖面圖。 第7圖係依據本發明之實施例形成顯示器之構造圖。 104氮化矽層 108正極接觸窗 112反面對準記號 116負極銲錫凸塊 120蝕刻窗 120-2正電極區钱刻窗 122自然遮罩 【主要元件符號說明】 100矽辅助框架 102秒基板 106負極接觸窗 110步進機對準記號 1Μ對準記號之封口 118正極銲錫凸塊 120 一 1負電極區钱刻窗 121 υ型腔室 π 1272731 124 正電極 126 128 蒸鍵之方向 130 200 LED晶片 202 204 PN接面 206 208 正電極 302 304 反射光 402 404 微凸透鏡 502 504 鰭狀散熱片 506 508 正電極電路 510 514 、516打線 518 602 一般PC板 604 608 正電極電路 610 614 、616打線 618 702 706 紅色LED晶片 藍色LED晶片 704 負電極 反射之金屬鏡面 透明基板 負電極 LED發射之光 透明塑膠 鋁質PC板 氧化層 512接線墊 負電極電路 金屬導熱孔 612接線墊 負電極電路 黃色LED晶片 12Fig. 3(B) is a view showing the relationship between the metal positive and negative electrodes of the 矽 auxiliary frame and the positive and negative electrodes on the led wafer. Fig. 3(C) is a view showing the relationship between the metal positive and negative electrodes of the auxiliary frame and the LED 曰=positive and negative electrodes on the cymbal in another embodiment. , /, Figure 4 is a cross-sectional view of a focusing lens formed of transparent plastic. Figure 5 is a cross-sectional view of the (4) wafer and the 矽 auxiliary frame of the hybrid package soldered to the Ilu PC board in a reverse manner. The figure is a cross-sectional view of a hybrid PC chip and a supplementary frame packaged on a general PC board in a flip chip format. Figure 7 is a block diagram showing the construction of a display in accordance with an embodiment of the present invention. 104 tantalum nitride layer 108 positive contact window 112 reverse side alignment mark 116 negative electrode solder bump 120 etching window 120-2 positive electrode area money engraving window 122 natural mask [main component symbol description] 100 矽 auxiliary frame 102 seconds substrate 106 Negative contact window 110 stepper alignment mark 1 Μ alignment mark seal 118 positive solder bump 120 1 negative electrode area money engraving window 121 υ type chamber π 1272731 124 positive electrode 126 128 steaming direction 130 200 LED chip 202 204 PN junction 206 208 positive electrode 302 304 reflected light 402 404 micro convex lens 502 504 fin fin 506 508 positive electrode circuit 510 514, 516 line 518 602 general PC board 604 608 positive electrode circuit 610 614, 616 line 618 702 706 red LED chip blue LED chip 704 negative electrode reflection metal mirror transparent substrate negative electrode LED emission light transparent plastic aluminum PC board oxide layer 512 wiring pad negative electrode circuit metal thermal hole 612 wiring pad negative electrode circuit yellow LED chip 12