TWI271850B - ESD protection device structure - Google Patents

Abstract

An electrostatic discharge (ESD) protective device is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, in which the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage.

Description

1271850 IX. Description of the invention: [Technical field to which the invention pertains] Gas A protective element structure for electrostatic discharge. [Prior Art] As the size of the semiconductor integrated circuit device continues to shrink, in the deep submicron mutual complement type MOS micro-transistor (CMOS) technology, the shallow junction depth is fine (10) depth) The thickness of the gate oxide layer (gate〇xide), the structure or process such as lightly doped (LDD), shallow trench isolation (STI), and seif_aiigned silicide have become standard processes. . However, the above structure or process makes the integrated circuit product more susceptible to electrostatic discharge (ESD) damage, so the ESD protection circuit design must be added to the chip to protect the integrated circuit from ESD damage. In the general market, _ body circuit products, in the body to kiss the taste · HBM) 'at least more than 2000 volts above the financial capacity, and in order to withstand such a large ESD package, ESD protection circuit must be designed to have A sufficiently large component size increases the area of the wafer that is occupied. In a typical example, in the input and output circuit (10) also (3) (8) esd P square circuit recognition port ten NMOS channel length (channei iength) is often larger than μιη this large size component design, often drawn on the layout It has a multi-finger structure (flnger) in parallel. However, when the voltage of the ESD is generated, the multi-finger layout in the ESD protection circuit cannot be turned on at the same time to release the esd current. 1271850 • Only part of the finger layout will be turned on, so these finger layouts will be ESD pulses. Burned out. Therefore, although the NMOS in the ESD protection circuit already occupies a very large size, the ESD voltage that can be withstood is still very low. In order to improve the non-uniform conduction of these multi-finger layout structures, a gate-driven design has been employed to increase the ESD compression capability of large-sized NMOSs in protection circuits. However, in the gate-driven NMOS of the ESD protection circuit, when the gate drive voltage increases above a certain value, the ESD tolerance is drastically reduced. Because the gate drive design directs the esd current to the channel surface of the NMOS, the NMOS is more susceptible to burnout due to ESD current. Please refer to Figure 1. Figure 1 is a circuit diagram of the ESD protection design in the conventional gate drive technology. Since the ESD protection design in all gate drive technologies is designed using the same basic concepts, an ESD protection design using gate drive technology disclosed in Fig. 1 is now described. The ESD protection circuit design 10 includes an NMOS 12 having an ESD protection circuit, and the NMOS 12 includes a source 13, a dipole 14 and a gate 16. The gate 14 is connected to a buffer port 18, and the gate 16 is supplied with a voltage by a gate bias circuit 20. In the conventional design, the gate bias circuit 20 is usually provided with a pair of capacitors and resistors for connecting the pad and the gate, and the resistor is used to connect the gate to the vss power pin. In addition, the ESD protection circuit design 10 is electrically connected to an internal circuit 22 and a buffer pad 18 by a wire 23. 1271850 When a positive ESD voltage is introduced from the input/output buffer 塾18, the rapid • rising ESD voltage is coupled to the gate 16 of the ESD protection circuit _〇8 12. The NMOS 12 is turned on to turn the ESD current. It is discharged to the μ power pin via the buffer pad 18. This is the so-called gate coupling design or the esd protection circuit for the gate drive design. Although the biased gate can improve the shortcomings of the multi-finger layout structure in the ESD protection circuit, the excessively high gate bias will cause the ESD to flow, and the L will flow through the surface of the channel. The transition layer (inversi (10) hy sink), burned the NMOS channel due to _. Please refer to Figure 2, which is a schematic diagram of the path of the ESD current flowing through the gate drive NMOS in the ESD protection circuit. As shown in Fig. 2, the NMOS 3G in the protection circuit includes - a p-type substrate 3 - a p-type well % is located in the p-type substrate 31, and an NMOS 34 is provided in the P-type well 32. The NM0S 34 includes a source 35, a drain 36, a doped polysilicon gate 37, and two lightly doped gates (1^〇) φ 38 disposed adjacent to the source 35 and the drain 36, respectively. The source 35 is electrically connected to the vss power pin, the drain 36 is electrically connected to the pad 4A, and the gate is electrically connected to a gate bias circuit 42. When the positive ESD voltage is introduced from the input/output buffer 塾4〇, the gate biasing turtle 42 generates a bias voltage (vg) applied to the drain 37 in the NMOS 34, and the surface channel of the NMOS 34 is turned on. . Since the inversion layer of the wire channel is extremely shallow and the volume is small, it is not only easy to be burnt due to overheating, but also easily damages the _〇834 by electrostatic discharge, and ESD damage usually occurs in the light exchange next to the bungee 36. Miscellaneous 1271850 • Surface channel near the 38th corner (comer). Therefore, when a large ESD current, • a typical example of 1 · 33Amp (for a 2kV HBM ESD ) flowing through a very shallow surface channel in the NMOS 34, the NMOS 34 is often burned, even if the NMOS 34 has a large component size. It is also impossible to avoid such a situation. In order to reduce the damage of the surface channel of the NMOS 34, the conventional ESD protection component 30 is often filled with a p+ diffusion region 33 under the drain 36 of the NMOS 34 to reduce the breakdown voltage of the PN junction between the Lulu pole 36 and the P-well. (breakdown voltage), as shown in FIG. 3, FIG. 3 is a schematic view of a well-filled well in a well of an ESD protection element. However, since the filled P+ diffusion region is located below the drain 36, it is generally necessary to cooperate with a deep well process and to reuse at least one additional metallization resist layer (salicide bl〇ck, The SAB) photomask and ion implant are privately formed to form this P+ diffusion region, thereby achieving the purpose of lowering the voltage and improving the ESD protection component. Therefore, it will increase the problem of reduction and reduction and group deviation (4). SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a health-sinking component structure to improve the problems of conventional ESD protection components. According to the Japanese version, please turn it over and expose it to a type of electrostatically charged canister ic-ge, ESD. The protective component structure is disposed on a substrate and the ESD protection component structure contains at least _ The first conductive type metal 1271850. an oxidized semiconductor (MOS), at least a second conductive type diffusion region, and at least one dummy gate. The drain and the source of the first conductivity type m〇s are electrically connected to the -th power supply terminal and the second power supply terminal, respectively, and the dummy interpole is disposed in the first conductivity type M0S and the Between the second conductivity type diffusion regions. In addition, the gate length of the gate of the dummy gate is smaller than the gate length of the gate of the first conductivity type MOS, so that the diffusion region of the third conductivity type and the drain of the first conductivity type MOS The mask has a low breakdown voltage. In addition, the scope of the present application further discloses an electrostatic discharge (ESD) protection device structure. The 忒ESD protection device structure is disposed on a substrate, and the ESD protection device structure includes at least one first conductivity type metal oxide semiconductor (M). 〇 s), at least one second conductivity type diffusion region, and at least one first conductivity type lightly doped drain (LDD). The drain and the source of the first conductive type M〇s are electrically connected to a first power terminal and a second power terminal, respectively, and the first conductive type is slightly doped with a dopant (LDD) system. And adjacent to the first conductive pattern MOS and the second conductive pattern diffusion region, such that the second conductive pattern diffusion region and the first conductivity type MOS drain has a low breakdown voltage junction. Different from the conventional ESD protection component, the present invention reduces the breakdown voltage of the pN junction by forming a -N+ diffusion region and a -p+ diffusion region at both ends of a dummy electrode. Therefore, when the dummy length is reduced to - Jianlin, the concentration at the junction of the PN junction formed between the N+ diffusion region and the P+ diffusion region is increased, thereby reducing the breakdown voltage of the junction to improve ESD. Overall performance. 1271850 [Embodiment] Please refer to FIG. 4, which is an electrostatic discharge (ESD) protection element according to an embodiment of the present invention.

Schematic diagram of the structure of the 90 piece. As shown in FIG. 4, the ESD protection element 90 is formed on a p-type well 92 of a substrate 91, which is a symmetrical structure and includes two _8 pieces 93, and an input/output of an electrical connection nmos element 93. A buffer (I/〇buffering pad) (not shown) and a Vss power pin (not shown), a p+ diffusion region 1〇〇, a P+ diffusion region 99, and a dummy gate 98 are provided in each Between the NMOS device 93 and the _P+ diffusion region 10A. The substrate 91 can be a p-type substrate or a type of substrate, and an NMOS device 93 further includes a drain 96 electrically connected to the input/output buffer pad, and a source electrically connected to the Vss power pin. The pole 95, and a doped 曰曰 曰曰 夕 夕 。 94. As also shown in FIG. 4, the P+ diffusion region 1〇〇 is opposite to the source 95 of the element 93; and the gate 96 is on the same side, and the gate length of the dummy gate 98 is smaller than the NMOS. The gate length of the doped polysilicon gate 94 of element 93. In addition, the electrostatic discharge protection device 9 of the present invention further includes a plurality of shallow trench isolations (STIs) 97 for isolating the source 95 of the NMOS device 93 and for connecting the pup well 92 as a pickup. P+ diffusion region 99. Since the present invention utilizes the P-type ion implantation process and mask pattern necessary for the drain and source of the PMOS element in other regions on the substrate 91, and utilizes the dummy gate 98 for self-aiigment. Forming a P+ diffusion region 1〇〇 to increase the concentration at the junction of the N+ diffusion region (ie, the drain electrode 96) and the P+ diffusion region 1〇〇, thereby reducing the breakdown voltage of the PN junction, and finally And to achieve the purpose of changing the overall performance of ESD. Therefore, the present invention does not require an additional metal germanide 1271850 barrier layer (SAB) mask and an ion implantation process to form the p+ diffusion region, so that the complexity and alignment deviation of the conventional process can be effectively solved. (misalignment) and other problems, and when the length of the dummy gate 98 is reduced to a certain extent, its effect is more obvious. ¥ When the T7H input/output buffer is applied with a momentary ESD voltage, the component 93; and the pole 96 and the P-well 92 form a low breakdown voltage pN junction (PNjunction), and Each _〇8 element 93汲 pole % and source % is # and P type well 92 constitutes a parasitic lateral surface bipolar transistor (4) lion plus (5) NPNBJT) 'So when this ESD voltage pulse is applied to the input / When the buffer is output, the ESD voltage pulse is conducted from the drain of the component 93 through the pN junction to the p+ diffusion region 100, and then propagated through the p+ diffusion region 1 to the P-type below the dummy gate 98. The well 92 is finally led by the source 95 of the NMOS component 93 to the vss power pin to quickly release the ESD voltage pulse. Referring to FIG. 5, FIG. 5 is a schematic structural view of an electrostatic discharge (ESD) protection element 11〇 structure according to an embodiment of the present invention. As shown in FIG. 5, the ESD protection element 11 is formed on the N-type well 112 of a substrate 111, and includes two PM〇s elements 113, and an input/output buffer pad electrically connected to the PMOS element 113 (not shown). And a power supply pin, an N+ diffusion region 120, a two N+ diffusion region 119, and two dummy gates 118 are provided between each of the PMOS elements 113 and the N+ diffusion region 120. The substrate 111 can be a P-type substrate or an N-type substrate, and the two pM〇s elements 113 each include a drain 116 electrically connected to the input/output buffer, and an electrical connection to the Vss power pin. A source 115 and a doped polysilicon gate 114 are provided. Another example is the fifth (S: 11 1271850). The N+ diffusion region 12〇 is opposite to the source ιΐ5 of the PM〇s element 113. • The same side as the gate 116, and the gate length of the dummy gate 118. The gate length of the doped polysilicon gate 114 of the U3 is less than the PMOS tree. In addition, the electrostatic discharge protection device 110 X of the present invention includes a plurality of shallow trench isolation (STI) 117 for isolating the pm 〇 component m The source m and the N+ diffusion region 119 used as a pinup of the N-type (four) 2. Similarly, when the input/output buffer is applied with an instantaneous ESD voltage, the drain of the PMOS device 113 A PN junction is formed between the Π6 and the n-type well 112. Since each pm 〇s element 113 has a drain 116 and a source 115 and a P-well 112, a parasitic lateral PNP bipolar electron crystal is formed. ^(parasitic丨(4)PNPBJT), so when a BSD voltage pulse is applied to the input/output buffer, the voltage is conducted from the drain 116 of the PMOS element in through the PN junction to the N+ diffusion region 120, Then, via the n+ diffusion region 12, to the N-well 112 below the dummy gate 118 φ, and finally to the source 115 of the PMOS element 113. The Vss power pin is used to quickly release the ESD voltage pulse. Referring to Fig. 6, Fig. 6 is a schematic structural view showing the structure of an electrostatic discharge (ESD) protection element 130 according to a third embodiment of the present invention. As shown in Fig. 6, ESD protection The component 13 is formed on a P-well 132 of a substrate 131. The device includes a second NMOS device 133, an input/output buffer (not shown) electrically connected to the NMOS device 133, and a Vss power pin, a P+. The diffusion region 140, the two p+ diffusion regions 139, and the two N+ lightly doped drain electrodes (NLDD) 138 are disposed between each NMOS device 133 and the P+ diffusion region (§) 12 1271850 domain 140. The substrate 131 may be a p a type of substrate or an n-type substrate, and the two NMOS devices 133 each further include a drain 136 electrically connected to the input/output buffer pad, a source 135 electrically connected to the Vss power pin, and a doped polycrystal In addition, the electrostatic discharge protection element 13 of the present invention further includes a plurality of shallow trench isolation (STI) 137 for isolating the source 135 and the diffusion region 139 of the _8 element 133. In the previously described embodiment, the present embodiment is based on the _8 element 133 and the P+ diffusion region. A second lightly-doped drain 138 is formed between 140 to replace the dummy gates 98, 118 of the previous embodiment such that the distance between the P+ diffusion region 14A and the adjacent two N+ lightly doped gates 138 It is smaller, so it can be effectively applied to processes below 9 inches. Moreover, since the present invention also utilizes the P-type ion implantation process and the mask pattern necessary for the drain and source of the iPM〇s elements in other regions on the substrate 131, even the other elements of the substrate 13 can be utilized. The ion implantation process and the mask pattern necessary for lightly doping the drain are respectively formed to form the p+ diffusion region and the second light-changing drain 138, respectively, to improve the diffusion region (also called the i3_p+ diffusion region M0) The concentration at the junction of the PN junction, which in turn reduces the collapse of the pN# surface: the end of the process is to achieve the goal of improving the overall performance of the ESD. Therefore, the present invention does not require an additional gold shot resisting layer (SAB). The reticle and the ion implantation process form the P+ diffusion region 140, so that the complexity of the conventional process and the alignment deviation can be effectively solved. Similarly, when an ESD voltage pulse is applied to the input/round-out buffer When padding, 1271850. The immersive NM〇S component 133 secret 136 Qin N+ light lion immersion i38 ' leads to the P+ expansion area 140, and then passes through the p+ diffusion region 140 to N+ lightly doped; and the pole I38 Below the P-type well Yang, and finally by the source of Gu Yu 8 components (3) (3) Leading to the vss power pin to quickly release the ESD voltage pulse. Referring to FIG. 7, FIG. 7 is a schematic structural view of the structure of the electrostatic discharge (10) talk element 150 according to the fourth embodiment of the present invention. Which protection element 15〇I is formed on the substrate 151 ^ well 152, which comprises: a pM〇s element 153, an input/output buffer (not shown) electrically connected to the PM〇s element 153, and a A Vss power pin, an N+ diffusion region 16A, a two N+ diffusion region 159, and two p. a dopant drain (PLDD) 158 are provided between each of the PMOS element 153 and the N+ diffusion region 160. a p-type substrate or an n-type substrate, and the MOS device M3 further includes a drain 156 electrically connected to the input/output buffer pad, a source 155 electrically connected to the Vss power pin, and a modified polysilicon Gate m. Further, the electrostatic discharge protection element 1S0 of the present invention further includes a plurality of shallow trench isolation (STI) 157 for isolating the source 155 and the N+ diffusion region 159 of the PM〇s element 153. In the third embodiment, the present embodiment is formed between the pM〇s element (5) and the N+ diffusion region by two!>+ · The pole (10) replaces the previous two virtual 1 wooden mouth. When the ESD voltage pulse is applied to the input/output buffer, the voltage will be controlled by the PMOS tree (5) and the p-lightly doped 158. To the N+ diffusion region 16〇, then pass the N+ diffusion region 16〇 to the material to change the noise

14 (N-well 152 below S 1271850 and 58, finally guided by the source i55 of the ?M〇s component (5), to the Vss power pin to quickly release the ESD pulse. / phase # 习 习 习 ESD protection components, The invention utilizes the Z-to-N+ diffusion region and the -p+diffusion region_ method at both ends of the dummy gate to reduce the breakdown voltage of the state junction. Therefore, when the dummy gate length is reduced to a certain extent, the N+ diffusion region The thick ship at the junction with the P's 卩 卩 red PN junction will increase, and then the sag will reduce the breakdown voltage of the junction to improve the overall performance of the lion. For example, the TM junction breakdown voltage It is about 9V, and when the dummy gate length of the ESD protection element of the present invention is ai5//m, the system collapse can be greatly reduced to about 6V. Therefore, in general, in order to ensure that the ESD protection component can be used in the conventional 3· Smooth operation under 3ν' user can selectively increase the length of the dummy gate to control (4) the voltage at the collapse is about 7V. In addition, the invention can form a second light-doped bungee in each soup tilting element and Ρ+diffusion. Between the regions, or two ρ+ lightly doped bungee in each of the 8 elements and the Ν+ spring diffusion region In place of the dummy gates of other embodiments of the present invention, as a bridge connecting the respective τ and the diffusion regions, thereby simultaneously achieving the reduction process, reducing the junction breakdown voltage of the Ν, and improving the overall performance of the ESD protection component. The above is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be within the scope of the present invention. 15 8 1271850 [Simple Description] 1 is a circuit diagram of an ESD protection design in a conventional gate driving technique. Fig. 2 is a schematic diagram showing a path of a conventional ESD current flowing through a gate driving in an ESD protection circuit. Fig. 7 is a fourth embodiment of the present invention. FIG. 3 is a schematic view showing a well-filled diffusion region in a well of an ESD protection element. FIG. 4 is a schematic view showing the structure of an electrostatic discharge protection tree structure according to a first embodiment of the present invention. FIG. 5 is a second embodiment of the present invention. The structure of the electrostatic discharge protection element = Fig. 3 is the structure of the electrostatic protection element structure = the structure diagram of the figure [the main component symbol description] 10 ESD protection circuit design i2 nm〇s 13 Source 16 Gate 2 〇 Gate Bias Circuit 23 Conductor 31 P-Substrate 33 P+ Diffusion Region 35 Source 37 Doped Polysilicon Gate 40 Cushion 90 ESD Protection Element 92 P-well 14 Bungee 18 Cushion 22 internal circuit 30 NMOS 32 P-well 34 NMOS 36 >

38 lightly doped drain 42 gate bias circuit 91 substrate 93 NMOS 16 1271850

94 doped polysilicon gate 96 > and pole 98 dummy gate 100 first P+ diffusion region m substrate

113 PMOS 115 source 117 shallow trench isolation 119 second N+ diffusion region 130 ESD protection component 132 P-well 134 hybrid poly gate second gate 136 drain 138 N+ lightly doped drain 140 first P+ diffusion region 151 substrate

153 PMOS 155 source 157 shallow trench isolation 159 second N+ diffusion region 95 source 97 shallow trench isolation 99 second P+ diffusion region 110 ESD protection component 112 N-well 114 push polycrystalline gate gate 116 drain 118 dummy Gate 120 first N+ diffusion region 131 substrate

133 NMOS 135 source 137 shallow trench isolation 139 second P+ diffusion region 150 ESD protection device 152 N-well 154 doped polysilicon gate 156 no pole 158 P+ lightly doped drain 160 first N+ diffusion region

(S 17

Claims (1)

1271850 X. Patent Application Range: 1 · An electrostatic discharge (ESD) protection element structure, the ESD protection element structure is disposed on a substrate, and the ESD protection element structure comprises: at least one first conductivity type a metal oxide semiconductor (M0S), wherein the drain and the source of the first conductivity type MOS are electrically connected to a first power terminal and a second power source; at least one second conductivity type diffusion region; and at least a dummy gate disposed between the first conductivity type chopstick 8 and the beta first conductivity type diffusion region such that the second conductivity type diffusion region and the first conductivity type MOSFET are bungee The mask has a low breakdown voltage. The electrostatic discharge protection element structure of claim 2, wherein the substrate has a second conductivity type well, and the esd protection tillage structure is disposed in the second conductivity type well. = If the application is specific, the slave static Wei _ type M0S immersed, the second conductive type well, and the second electric ^, such as the application of the electrostatic discharge protection component structure of the first item, wherein the dummy 18 1271850 :::Length·__ is less than the gate length of the gate of the first conductivity type. Shen (7) patent fine item i of the conductive form of the diffusion area of the 仵,, the summer of the younger brother - not the same side. Knowing that the source of the conductive form 嶋s is the same as the 6th, such as the scope of the patent scope, the second gate of the virtual gate length, in the second description structure, wherein the different M〇S The diffusion region has a different breakdown voltage from the junction of the first conductivity type wood. The conductivity type is N type, as in the case of the patent application, and the second conductivity type is P type. ~ Electrostatic discharge protection structure, wherein the first-to-conductance 1st electrostatic discharge protection element structure, wherein the first electrical type is? Type, and the second conductivity type is N type. The electrostatic power supply end of the J-th patent range is an input/output buffer pad (10) bufferingpa=configuration pin one brother = _ electric security _ structure, -· 11. kind of electrostatic discharge _) Lai Shu turn, The lake Laiyuan hiding system (si 19 1271850 is placed on the substrate, and the ESD protection element structure comprises: 1 less than a first conductivity type metal oxide semiconductor (MOS), and the first conductivity type, MOS The gate and the source are electrically connected to a first power terminal and a second power terminal respectively; at least one first conductive type diffusion region; and at least one first conductive type lightly doped drain (LDD), And adjacent to the first conductive type MOS and the second conductive type diffusion region, so that the second conductive type diffusion region and the first conductive type of the river 8 have a low breakdown voltage connection U. The electrostatic discharge protection component structure of claim U, wherein the wire bottom further comprises a second conductivity type rotation, and the rigid protection element structure is disposed in the second conductivity type well. ·If you claim to be the 12th item of electrostatic discharge protection a device structure, wherein the drain of the first conductivity type MOS, the second conductivity type well, and the source of the first conductivity type MOS form a parasitic lateral bipolar transistor (4) BJT) 如·如申The electrostatic discharge device structure of the item U is the same as the source of the first conductive form m〇s with respect to the source of the first conductive form m〇s. 20 1271850 U slave electrostatic layout component structure, wherein different μ $ lengths have different breakdown voltages on the junctions of the second conductivity type diffusion region MOS. V type 1 a 6 lead " U, where the 'th is N type, shouting the second conductivity type is p type. ^ The second conductivity type is the Ν type. 18·For example, the application of the power supply terminal is the structure of the electrostatic discharge protection component of the input, wherein the second buffer pad (I/O buffering pad) 19·such as the patent scope of the application] The structure is a -V t-shaped electrostatic discharge device structure in which the Vss power pin is connected. XI. Schema: 21