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TWI270329B - Method for fabricating conducting bump structures of circuit board - Google Patents

Method for fabricating conducting bump structures of circuit board Download PDF

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Publication number
TWI270329B
TWI270329B TW094110691A TW94110691A TWI270329B TW I270329 B TWI270329 B TW I270329B TW 094110691 A TW094110691 A TW 094110691A TW 94110691 A TW94110691 A TW 94110691A TW I270329 B TWI270329 B TW I270329B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
circuit board
bump structure
metal
Prior art date
Application number
TW094110691A
Other languages
English (en)
Other versions
TW200637448A (en
Inventor
Wen-Hung Hu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW094110691A priority Critical patent/TWI270329B/zh
Priority to US11/397,417 priority patent/US20060219567A1/en
Publication of TW200637448A publication Critical patent/TW200637448A/zh
Application granted granted Critical
Publication of TWI270329B publication Critical patent/TWI270329B/zh

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Classifications

    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • C25D5/022Electroplating of selected surface areas using masking means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3473Plating of solder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/421Blind plated via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09436Pads or lands on permanent coating which covers the other conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09563Metal filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/043Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography
    • H05K2203/054Continuous temporary metal layer over resist, e.g. for selective electroplating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/0568Resist used for applying paste, ink or powder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/062Etching masks consisting of metals or alloys or metallic inorganic compounds
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/064Photoresists
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/423Plated through-holes or plated via connections characterised by electroplating method

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Electrochemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Description

1270329 九、發明說明: 【發明所屬之技術領域】 =明係有關於-種電路板導電凸塊結構之製法,尤 構種在電路板之電性連接塾上形成導電凸塊結 【先前技術】 為使封裝件更輕薄短小,生產且 墊尺寸之细缚挪彳F. 產/、有鈿小線路覓度與焊 之目根,而: e 業已成為業界持續努力 s. τ β 如 BGA、Fllp Chlp、晶片尺寸封褒(CSP, Chip ^ pac age)與多晶片模組(MCM,咖“ c叫则加 路的面積且具有高密度與多接腳化特性之封裝 ,,二斤成為封裝市場上的主流。以覆晶技術為例
Hi 導體積體電路(IC)晶片的表面上配置有電 ^ (Electrode pads),並且於電路板上形成有相對應之命 早猎由在。亥曰曰片與電路板之間設置焊錫凸塊 s:bump)或其他導電黏著材料,以提供該晶片以 接觸面朝下的方式設置於該電路板上。 在現行覆晶技術中,半導體積體電 :有電極墊細-一而電路板亦具有 性連接墊,在該晶片的電 心、甩 置焊錫凸Mm + 的電性連接塾可設 :干錫嶋其他導電黏著材料,而該晶片係以 面朝下的方式接置於該電路板上,其中,今觸 電黏著材料提供該晶片以及電 X .鬼或導 (i/〇)的連接。 及$路板間的讀輸入/輸出 ]8]83 1270329 塊或㈣板的電性連接塾形成焊錫凸 性連接塾之間隙:二的方式形成,但隨著電 縮小,造成後續性連接墊之尺寸更加 旻·、’、員$成:^干錫凸塊不易附基 上,導致焊錫材料與電性連接塾之間的二性連接墊 由於烊踢材料支撐強度不足,致;:::佳’同時 錫材料亦會有溢流之現象。 、斗蚪叉熱熔融之焊 為解決上述弊端,或有以電鍍方 + 錫材料之技術,藉以達到細線路之目的二板上形成焊 焊錫的方式相較於印刷塗佈 於電鍍形成預 到細線路,以達高密声你碎、,:精达、度,因而得以達 鑛方式在電路板的;:連接板面積。而以電 該電性連接墊上形成導電層,以在焊錫前,則先在 錫。而在電路板之電性連接塾上形=電=上形成電鍍焊 第1Α圖至第1F圖所示。 y兒鍍焊錫之技術,如 請參閱第1A圖,待於 θ , 之電路板1〇上η , 具有複數個電性連接請 。月芩閱第1Β圖,於該防焊 以顯露出該電路板10之電性連接塾^成有開孔110,俾 凊芩閱第1C圖’接著在該防 内的電性連接墊100表面形:“及其開孔110 請參閱第m圖,復於干电層i2(seedlayer)。 形成有開孔一以外辑於:^ ]8]83 6 1270329 電層12。 “閱第1E圖’然後進行電鍍製程,|i由哕導#声 12作為電鍍的通路,以在h 赭由Μ电層 . 在4笔路板10之電性連接墊100 上形成導電凸塊14。 請參閱第1F圖,之徭梦^ # 電層12,並於該導電凸塊二该阻層13及其所覆蓋之導 以保護該導電凸塊14。 面形成金屬保護層15,藉 層係形成在防焊層11之開孔110及阻 深較n I巾’而该開孔110及130疊置所構成的孔 7《於孔形較深的孔巾形成導電 鍍製程的困難度。 只P曰加免 再者,欲於開孔i丨〇、丨3〇中形 所欲電錄的區域面積小,故所;電’因該 =定,使得該些導電凸塊14形成後的高度;= 千正性i而影響後續製程之進行。 、 因此,鑒於上述之問題,如 凸塊在孔形較心… ㈣免白知技術中之導電 札H乂冰及所欲電鍍的區域 整性不佳影響^中心成,導致平 題。 “衣私之進仃,貫已成目前亟欲解決的課 【發明内容】 鑒方、别述習知技術之缺點,本 -種電路板導電凸塊…” 要目的係提供 導電凸塊之平敕:以避免產生電路板表面 電性連接製程可靠度問題。 /、Μ…件作 】8183 7 1270329 本發明之再—目的係提供一種電 製法,得以避免習知由於電 、电凸塊結構之 兒級适域面積小或备 較深,導致電鍍製程難度增加等問題。' —兔鍍區域孔形 本發明之另—目的係提供—種電 製法,可減少焊锡材料使用量及__ /凸塊結構之 本發明之又再一目的係提供 及其製法,俾得有 種电路板導電凸塊結構 向外作電性導接之導電結^距之笔路板電性連接塾上形成 為達上述及其他目的,本發 一 塊結構之製法,係包括以下步驟:提::至:路板導電凸 =電性連接墊之電路板,且於該電路板面形成 保纟又層,並令該絕緣保護 谈现一絕緣 連接墊;於該絕緣保護層路出该琶性 該導兩衣向办成一導電層,B 士人 。亥W層上電鍍形成—金屬 :,且於 緣保護層開口中;於該金〜屬層填充於該絕 對應該電性連接墊位置形成一阻層,且令該阻層 y成(有開口,以夕卜霞山 -,於相層開口中形成_ 。刀。亥金屬 該層所覆蓋之金屬層及導 :/及私除該阻層及為 性連接墊上形成導電凸塊 路板表面之電 材料,後續復包括進行回尸制中㈣黏著層為焊錫 ‘者層包覆於該金屬層之外露表面上。 干錫材料之 本發明之電路板導電凸塊 例係包括以下實施步驟:提;另-較佳實施 墊之電路板,且於該電路:二!面形成有複數電性連接 板上復盍一絕緣保護層,並令該 8 ]8]83 1270329 絕緣保護層形成複數開口以 保護層及其開口表面形成—導;; 亥笔性連接塾’ ·於該絕緣 形成一金屬層,並使該金^心二於該導電層上電錢 中;於該金屬層上形成=保護層開口 該阻層僅覆蓋住對應於該電性 订13木化製程,以使 層;移除外露於該阻層之金屬 分金屬 之蛉电層,以及移除該阻層,並於 α復皿 一黏著層。 / 萄層外路表面形成 因此,本發明之電路板導電凸塊聋 在電路板上形成具禎激η η ^ 苒之衣法主要係 說车 /、 幵之絕緣保護層以外露出兮命?々 板表面之電性連接墊 。出.亥电路
成道十a 於該絕緣保護層及開口表W 成一導電層,不同於習知之 表面形 口疊置的孔形,藉由該導電二::成阻層,再形成開 m备表面積,而提供較 。 上電鑛形成-金屬層,再移除部:=方,層 再於其表面形成:;二連接塾部分之金屬層及導電層, 接墊上形成導電凸塊結構反表面之電性連 區域面積過小,所提 i免白知電鑛製程中電鍍 電鍍製程因難度増加,且本發明 =面而, 该絕緣保護層之表面及開 j先王面,成於 ,心的金屬層以形成高度一 : 俾可避免習知電铲制 〒兒凸塊結構, 置開=接於絕緣保護層與阻層之4 成W凸塊時,因欲於孔形較深的孔中形 9 18183 1270329 ;導電凸塊’而增加電鍍製程的困難度,導致卜 度—致性無法控制,造成電路板與外界電::_鬼高 完成電性連接。 电子兀件無法有效 同時,本發明之電路板導電凸塊結 電路板表面之絕緣保護層上依次形成導衣〉中,係於 移除部分金屬層及其所覆蓋 '二:屬層,於 藉以在該電路板之電性連接塾上形二::成㈣層’ 技術中,於絕緣保護層上形成導電層 、避免智知 阻層,然後於絕緣保護層及阻層之開 上形成 塊,高所導致電_二^ 卷月可由材料成本較低且 、 :;物峨鐘出銅質之金屬層,藉以縮 程難^了^由較大的電鑛區域進行電鍍製程以降低電鑛f 層、二’ “後形成材料成本較高之例如為焊錫材料之^著 二心:=程所需時間,以透過減少焊錫材料使用量 而卜低材科成本與環保問題,且可同 成架橋現象及短路問題,俾二:二 塊尺及避免習知模板印刷技術形成導電凸 頸。寸及彳目鄰電性連接㈣距之限制及製程技術上之瓶 【實施方式】 ϋ I W㈣定料體實射'm明本發明之實施方式’ =1:之人士可由本說明書所揭示之内容輕易地瞭解 x ”他優點及功效。本發明亦可藉由其他不同的具 10 麵 1270329 體實施例加以施行或應用,本說明書中的各項細節亦可基 於不同的觀點與應用,在不择離本發明之精神下 修飾與變更。 ° 請參㈣2Α至第21^,將詳細㈣本發明之電路板 塊結構之製法較佳實施例之剖面示意圖。此處須注 思的一點是,該些圖式均為簡化之示意圖,盆僅 式說明本發明之基本架構, 1、 〜方 構成,且所顯示之構成並非以;;1=與f娜 及尺寸比例㈣,其作二= 一之數目、形狀、 為-種選擇性之數目、形狀及尺寸比例 x 〇t且其構成佈局形態可能更H #。 請參閲第2A圖至第2D岡、,士』 此更马妓4。 個電性連接百先提供表面形成有複數 接墊之電路板。如第2A圖所示,係在 表面絕緣層41上形成導命息 , 反 述電鑛金屬材料所需之電;4、首二導電層42主要作為後 數層金屬層所構成::、v ’其可由金屬或沉積 錫-鉛等單声銅、錫、鎳、鉻、鈦、銅-鉻或 年早層或多層結構,或可使用例 有機硫聚合物等導電高八 跃承本胺或 在該導電層42上;;_刀子材料;如第2B圖所示,接著 膜或液態光阻等光阻:層43 :該阻層43可為-例如乾 用印刷、旋塗或貼人等::叫或非感光阻層’其係利 r H τ 〇寺方式形成於該導電;49矣;$ „ %、光、顯影或雷射等方 s 、,猎 有複數外露出部分導1 49目案化’以使該阻層形成 進行電_leci 之開口 430;如第2〔圖所示, 性,俾在進^==程,藉由該導電層42具導電特 又可了作為電流傳導路徑,以在該等欲電 Π 18183 1270329 鍍開口 430中電銀形成有電 電錢形成有電路板表面之導電線路二當然亦可同時 示,接著即可移除將該阻層圖不),如#扣圖所 •電層42。 ^及该阻層43所覆蓋之導 =閲第_’接著,於 一 保4層45。於本實施例中 ㈣攻 '、‘巴蝝 —方式將該絕緣保護層45塗^用/^、旋塗及貼合之任 案化製程以使該電性連接•‘、二路板表面,再藉由圖 其中’該絕緣保護層45可為例如^讀該絕緣保護層〜 藉由曝光、顯影或雷射等方式力、’’、、防卜層材料所製成,並 45形成有複數個開口 45。邑緣保護層 請參閲第㈣,於性連接塾秦 面形成—導電層46。該導電声 ^ 及其開口物表 屬材料所需之電流傳導路/ 要係作爲後續電鐘金 層金屬層所構成,或可使;例π金屬、合金或沉積數 請參閲第2G圖,接著進行電:子材 46作為電流傳導路徑,且藉 導電層 鍍區域,以於該導帝 W層46表面較大的電 且使該全屬二: 全面電鑛形成-金屬層… 孟屬層47填充於該絕緣 金屬層47表面平整。其中,該合=開口 450中以保持該 錫、銀、銅等金屬或為其合金,惟“二二材:可為錯、 田方、钔為成熟之電鍍材料且 ^ 以由,銅所構成者為較佳,但非以此為限广金屬層47 4閱…,於該金屬層47上形成—阻層48,並 18183 12 1270329 方式將該阻係利用印刷、旋塗及貼合之任一 製程以你邱二亥金屬層47表面,再藉由圖案化 阻層48之°:之该金屬層47顯露於該阻層㈤口 480,且該 位置處。# °彻係對應該電路板表面之電性連接墊440 請參閲第21圖,於哕卩日思+ μ -軸❹49^t;m4㈣形成—黏著層 鉑或1人全,…:“銅、錫、鉛、銀、錄、金、 口盃亚可以電鍍方式直接形成。 請參閲第2J圖,接著,利 式移除該阻層48。 干χΙ或物理移除等方 請參閲第2Κ圖,接著移除未為該黏 =屬層47及導電“,僅留下該黏著;4二斤= ^性連接墊440位置處之部分金屬層^及^下對^ 以於:玄電性連接墊44〇上形成導電凸塊結構。-曰, 晴參閲第2L圖,若兮教益庶 即可進行回焊製程以使得該焊錫:料完時,接著 電性連接塾440上之金屬層47外 正。4該形成於該 、曾請參閱第3A至第3〇圖,將詳細說 V電凸塊結構之製法第二實施例之剖面示—月之笔路板 請參閲第3A,首先提供一至少— 二θ。 連接墊510之電路板50。 、形成有複數電性 +請參閱第3Β圖,接著於該形成有電性連 電路板50上覆蓋一絕緣保護層55。於/ 51〇之 、、舞、施例中,係利 18183 13 1270329 ^刷'mu合之任—方式將該絕 -,藉以使該電性 開口 55〇中。 10择員路方^玄絕緣保護層55之 請參閱DC目,於該絕緣保 面形成一導電層56。爷導^ + 及八開口 550表 屬材料所需要的電流料路^。56主要係作爲後續電鑛金 爲電:透:::錢製程,該導電層56作 於該導電層56上電鐘形成—全;声大的電鑛區域 填充於該絕緣保護層之開 S 便咸金屬層57 平整。 層之開口 550中以保持該金屬層57表面 阻/5月所3£圖’於該金屬層57上形成—阻層58,該 用=膜或液態光阻。於她 -表面,再^荦之==758覆於一 於該電路板5”… 層58僅覆蓋住對應 二=面之電性連接墊51〇位置處之金屬層57。 屬声 圖’移除未為該阻層58所覆蓋之部分全 屬層57及導雷爲以,仅如斗 |刀孟 表面之電性遠驗 層58下對應於該電路板50 56。 510位置處之部分金屬層57及導電層 口月參閲弟3G圖,接菩音,丨田儿过、士 方式移除卿58,清 干 稭以於該金屬層47外露表面上> 電電鍍方式形成—黏著層59。 卜〜表面上以热 18J83 ]4 1270329 口此本發明之電路板導電凸塊纟士播制 在電路板上形成具複數開口之絶緣保1之表法,主要係 板表面之電性連接墊,接…隻曰以外路出该電路 成一導+思 …玄、吧緣保護層及開口表面y 攻v毛層,因該導電層表面夫罗& 面形 有較大的暴露表面積 ^置阻層,而提供導電層 上電鍍形成-全屬>,_ 的電鍵區域而於該導電層 再於其=Γ:連接墊部分之金屬層及導電層 /、衣曲形成一黏著層 接墊上形成導電凸塊έ k笔路板表面之電性連 區域面積過…夕 避免習知電鍍製程中電穿 屬層係=1:Γ』程因難度增加,且本發明該: 該金屬層表面平整,Α接梦^ 表面及開口中,以使 致之導電凸塊結構,俾可二::;金屬層以形成高度-上形成阻層,而導_田白讀製程,係於導電層 口中電㈣豐置的孔形,然後於該疊置的開 τ兒鍍形成導電凸塊,因φ J間 製程難度增加及所欲電::σ”孔形較深,使得電鍍 密戶;^έ 又品或面積小,造成製程的電浐 件電性連而影響後續製程— 而非性說明本發明之原理及其功效, 違背本發明之糾及/㈣白此項技藝之人士均可在不 此本發明之=:w,對上述實施例進術 【圖式C乾圍,應如後述之申請專利範圍所列。 18183 15 1270329 第1A圖至第11?圖係顯示習知恭 形成電導電凸塊之剖面示意圖;、电路板之電性連接墊上 笔凸塊結構之製 笔凸塊結構之製 弟Α至第2l圖為本發明之 法弟一實施例之剖面示意圖’·以及 …弟3A至第3G圖為本發明之電路板導 法第二實施例之剖面示意圖。 、
【主要元件符號說明】 10 電路板 100 電性連接墊 110 、 130 開孔 11 防焊層 12 、 46 、 56 導電層 13 阻層 14 導電凸塊 15 金屬保護層 41 絕緣層 42 導電層 43 、 48 、 58 随層 430、450、480、550 開〇 45 > 55 绝緣保護層 440 、 510 電性連接墊 47、57 金屬層 49、59 令占著層 50 電路板 18183 16

Claims (1)

1270329 广申請專利範圍: 種,路板導電凸塊結構之製法,係包括: 板,且於:=;表'形成有複數電性連接塾之電路 吨鹿 毛板上覆盍一絕緣保護層,並人兮π #仅 嗖層形成有斿私μ , 亚7忒絶緣保 ^ 旻數開口以外露出該電性連接墊; 方…亥、纟巴緣保護層及開口表面、 導電層上電铲彤+ 入租 取 層,亚於該 絕緣保護相,且使得該金屬層填充於該 性連:妾ίίί:上覆蓋一阻層,且令該阻層對應於該電 於=么處形成有開口以外露出部分金屬層; ' €開口中形成一黏著層;以及 移除該阻層及其所覆 黏著層下對應於該電性連接墊位置7二=,保留該 導電層,藉以、 置處之。卩为金屬層及 2.如申,專#^〜〃性連接墊上形成導電凸塊結構。 Τ明專利乾圍第1項之 傅 法,其中,兮φ卩、 路板^电凸塊結構之製 ^电性連接墊之製程係包括·· 於:V:表面絕緣層上形成導電層; 開口以外露出邱八:成阻層’亚令該阻層形成有複數個 路出邛分導電層;以及 於該阻層開口中帝 3.如申往|&丨— 中电鍍形成電性連接墊。 甲°月專利乾圍第2項之恭 法,復包括移除用板導電凸塊結構之製 所覆蓋的導電層。叉乂成°亥電性連接墊之阻層及其 4·如申請專利 項之電路板導電凸塊結構之製 18183 ]7 !27〇329 =°玄附著層黏著層係藉由電鑛及塗覆之其中一 者形成於該金屬層上。 L申::利範圍第1項之電路板導電凸塊結構之製 二'’该黏著層材質係選自鎮、銀、金、銅、錄、 蚝、鉑及其合金其中一者。 & 申:專利範圍第5項之電路板導電凸塊結構之製 露表面。’ _著層係經回焊以完整包覆於該金屬層外 I ΓίΓ範圍第1項之電路板導電凸塊結構之製 金所構:群選自錯、錫、銀、銅及其合 δ. 圍第1項之電路板導電凸塊結構之製 4 -中’㈣電層係為金屬材料製成。 . 申請專利範圍第以之電路 法,其中,哕邋币 ο兄、、口稱之衣 10 -種電路板導二 機高分子材料製成。 種电路板導電凸塊結構之製法,係包括. 板:Γ:;广表面形成有複數電性連接塾之電路 御成;::二上覆盖'絕緣保護層,並令該絕緣保 層开4有複數開口以外露出該電性連接墊; 於該絕緣保護層及其開 該導電層上電鑛形成—金;声,表且;^成一導電層’並於 絕緣保護層開口中; 日便遠金屬層填充於該 方;6亥金屬層上覆蓋一卩且# 化,該胆層僅覆蓋住對應; 18183 18 1270329 部分金屬層; 移除未為該阻層所覆蓋之 移除該祖層,且於該金屬7及\電層;以及 層。 Γ路表面上形成一黏著 η.如申請專利範圍第1〇項之 法,其中,兮# 板冷电凸塊結構之製 。亥電性連接墊之制 於電⑹包括: 电路板之表面絕緣層上 於該導雷层丄 从今电層, 口以外露出,:導::阻層’且令該阻層形成複數個開 ㈤°卩分導電層;以及 於該阻層開口中Φ 12如申,| » 电、’又/成电性連接墊。 12.々甲D月專利範圍第u項之 法,復包括沪p/v田 板凸塊結構之製 所覆蓋之導電層。 乂多包性連接墊之阻層及其 13·如申請專利範圍第10項之 法,其中,兮利— 路板蜍电凸塊結構之製 、 5亥黏者層材質係選自錫、鉀八 U二二及其合金所構成群組之其中1 1〜、錄、 /、γ ’该金屬層材質係遝白 金所構曰柯貝知込自鉛、!易、銀、銅及其合 15 7偁成群組之其中一者。 〇申請專利範圍第1〇項 法,复由^ 貝兒路板ν笔凸塊結構之製 ]6·如申’該導電層係為金屬材料製成。 法,I中利乾圍第10項之電路板導電凸塊結構之製 〃,該導電層係為有機高分子材料製成。 ]8]83 ]9
TW094110691A 2005-04-04 2005-04-04 Method for fabricating conducting bump structures of circuit board TWI270329B (en)

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