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TWI268661B - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
TWI268661B
TWI268661B TW091123027A TW91123027A TWI268661B TW I268661 B TWI268661 B TW I268661B TW 091123027 A TW091123027 A TW 091123027A TW 91123027 A TW91123027 A TW 91123027A TW I268661 B TWI268661 B TW I268661B
Authority
TW
Taiwan
Prior art keywords
signal
delay
input signal
circuit
accordance
Prior art date
Application number
TW091123027A
Other languages
English (en)
Inventor
Tsuyoshi Higuchi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TWI268661B publication Critical patent/TWI268661B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
TW091123027A 2002-03-26 2002-10-04 Semiconductor integrated circuit TWI268661B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002086344A JP4021693B2 (ja) 2002-03-26 2002-03-26 半導体集積回路

Publications (1)

Publication Number Publication Date
TWI268661B true TWI268661B (en) 2006-12-11

Family

ID=28449302

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091123027A TWI268661B (en) 2002-03-26 2002-10-04 Semiconductor integrated circuit

Country Status (4)

Country Link
US (1) US6765423B2 (zh)
JP (1) JP4021693B2 (zh)
KR (1) KR100806152B1 (zh)
TW (1) TWI268661B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3818216B2 (ja) * 2002-05-17 2006-09-06 ヤマハ株式会社 遅延回路
JP2004127147A (ja) * 2002-10-07 2004-04-22 Hitachi Ltd デスキュー回路およびそれを用いたディスクアレイ制御装置
US7269754B2 (en) * 2002-12-30 2007-09-11 Intel Corporation Method and apparatus for flexible and programmable clock crossing control with dynamic compensation
JP3779687B2 (ja) * 2003-01-29 2006-05-31 Ｎｅｃエレクトロニクス株式会社 表示装置駆動回路
KR100586841B1 (ko) * 2003-12-15 2006-06-07 삼성전자주식회사 가변 딜레이 제어 방법 및 회로
US7463680B2 (en) * 2003-12-16 2008-12-09 California Institute Of Technology Deterministic jitter equalizer
US7505505B2 (en) 2003-12-16 2009-03-17 California Institute Of Technology Crosstalk equalizer
JP2007258995A (ja) * 2006-03-23 2007-10-04 Sharp Corp データ信号位相調整装置及び半導体装置
WO2009050803A1 (ja) * 2007-10-18 2009-04-23 Shimadzu Corporation Ｔｆｔアレイ検査装置および同期方法
JP5245658B2 (ja) * 2008-09-05 2013-07-24 富士通株式会社 バス接続におけるチップ間信号の共有化方法及び回路
KR101062853B1 (ko) * 2009-07-01 2011-09-07 주식회사 하이닉스반도체 반도체 장치의 데이터 샘플링 회로
KR20130129782A (ko) * 2012-05-21 2013-11-29 에스케이하이닉스 주식회사 입력버퍼
KR20180119071A (ko) * 2017-04-24 2018-11-01 에스케이하이닉스 주식회사 전자장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098796A (ja) * 1995-06-16 1997-01-10 Hitachi Ltd データ転送装置
JP4090088B2 (ja) 1996-09-17 2008-05-28 富士通株式会社 半導体装置システム及び半導体装置
JP3908356B2 (ja) * 1997-10-20 2007-04-25 富士通株式会社 半導体集積回路
US6289068B1 (en) * 1998-06-22 2001-09-11 Xilinx, Inc. Delay lock loop with clock phase shifter
JP3522126B2 (ja) * 1998-11-17 2004-04-26 沖電気工業株式会社 同期検出方法及び装置、並びに位相同期方法及び装置
JP2000244469A (ja) * 1999-02-23 2000-09-08 Nippon Telegr & Teleph Corp <Ntt> ビット同期回路
KR100533984B1 (ko) * 1999-12-30 2005-12-07 주식회사 하이닉스반도체 잡음 제거를 위해 딜레이제어기를 갖는 지연고정루프
KR100521418B1 (ko) * 1999-12-30 2005-10-17 주식회사 하이닉스반도체 지연고정루프에서 짧은 록킹 시간과 높은 잡음 제거를갖는 딜레이 제어기

Also Published As

Publication number Publication date
JP2003283477A (ja) 2003-10-03
KR100806152B1 (ko) 2008-02-22
KR20030077927A (ko) 2003-10-04
JP4021693B2 (ja) 2007-12-12
US6765423B2 (en) 2004-07-20
US20030184354A1 (en) 2003-10-02

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