1264805 九、發明說明： 【發明所屬之技術領域】 =日=關於-種於承裁件中整合半導體元件 法，尤指一種將薄化晶片固定 、衣 【先前技術】 n载件之開孔内的製法。 ，子產業的蓬勃發展，電子 方向，同時外形也朝向輕薄短小之方“：。 因此，如何在日益緊縮之有限办 π义化。 置高佈線密度之半導俨曰片：内，在曰曰片承載件上安 要課題。 1已成為承《界的-項重 者半導體裝置之製程，首先係由晶片承載件萝迭苹 或導線m t 曰曰片承載件’如各式電路板 者進s 將該些晶片承載件交由半導體封裝孝 者進灯置晶、打魏、据厭 条 足半導雕封壯&^ 、土、l及植球等製程。同時，為滿 足丰^料件㊅積集度（IntegmiQ_及微型化 ((ΓΓΓ咖iGn)的封裝要求，係可採用層間連接技術 ΓΓ1ΓΓΤ一以擴A電路板上可利用的佈線面 '、取、所1展出的一種可藉由將晶片嵌埋入電路板 預开/成的開孔中，並使晶片固定於電路板内 導麵，電路板結構，如第丨至第2圖所示。一 之半i:二圖：不，係為美國專利第6,7。9,898號所提出 广 、、衣件。如圖所示，該半導體封裝件係以-散熱 板102作為承載件，該散熱板⑽具有至少一凹部刚， 以由▲凹# 1〇4接置—半導體晶片n4。其中，係塵合一 ]8]〇】 1264805 ，"電層Π 2於該半導體晶片】]4及散熟板〗〇2的表囬，裔 介電層112係貼置於該半導體晶片1]4之主動面]]$，且 该半導體晶片114之非主動面1]8則係藉由一熱傳導黏著 材料120接置於該凹部1〇4中。而且，藉由增層技術^可 於該散熱板102及該半導體晶片114上形成一線路增層結 構12 2，如第2圖所示。 心惟，由於該介電層112具有流動性，該介電層ιΐ2會 :入該半導體晶片114與該凹部ι〇4間之缝隙後，使得該 ”電層112表面形成多個凹處。如此一來，因介電層112 坦性不足’將影響後續進行線路增層結構之i程品 貝與電性連接的可靠度。 —匕外為使I體體積更為輕薄短小以及設置更多主被 力兀件，係將晶圓背面加以 化再進仃切割，以獲得 /二ά的損傷’例如去除晶面貼片時變得容易破 衣’化成晶圓的報廢。 因此，如何於整人a y ?此" 術之製f的阁斤 口 3曰片承載件之製造與半導體封裝技 性，：：、” ’均勻控制承載件接置晶片之表面的平敕 陡，亚有效降低晶圓之破 1+1 【發明内容】 男'為亟待抓纣之课題。 提供技術之缺點，本發明之主要目的传 表面所形成的介”二“體元件之製法，使該承载件 程之進行。％…面保持平整，俾利後續增層線路製 18101 1264805 本兔明々又-目的係提供—種於承 元件之製法，以於令整體結構薄 ：“〜豆 工晶圓時之破片率。 #化之…降低研磨及加 本發明之再一目的係提供-種於承载件中整合半導俨 板中。 曰日片此輕易地置放且接置於核心 為達上述目的以及其他目的 合半導體亓彳^ 發明之於承載件中整 曰η你曰+ 支係包括.百先提供至少一薄化 係具有-主動面及非主動面； 開口之承載件；於該承載件底面形成一第_介：^至二 非主動面結合在該第中再;使該薄化晶片之 晶…面形成一第二介電;表:及；：該承載件及薄化 订平坦化製程，使該第二介電層表面保持平整:層表面進 於—個較佳實施例中，該薄 一具有—主動面以及-非主動之製程係包括··提供 面形成—保護層，·接著料曰圓之:函，於該晶圓之主動 於該晶圓之非主動面形成非，面進:研磨；再 晶圓設置於—支承板上. "猎由5亥黏著層以將該 遽声.以及 ，二後移除該晶圓之主動面上的佯 以二及切利該晶圓以形成複數個薄化晶片。保 、較佳實施例中，將至少—薄化晶片 件之開口之步戰係包括：加熱該薄化 ^^承裁 内，使該薄化晶；涛化晶片置於該承載件之— 日日片、4合在第一介電層表面。 】8]〇] 1264805 另一較佳實施例中，將至+ 一 件之開口之步驟 y “曰曰片整合於一承載 乂 系包括··將該薄 之開口内之第一介~化卵片直接置於該承載件 著，而在該第一介+ '"弟；丨笔層未固化前黏 載件。 ^層固化後以將該薄化晶片固定於該承 於分別實施上述兩將薄 得以將該薄化晶片接—B曰片置於承裁件之方式後， 承載件及薄化晶片表面上形成，内，並後續於該 晶片固定於該承載件。 弟—"黾層，以將該薄化 於一個較佳實施例中，該承載 成該電路板之步驟係包括：提供 笔路板，且形 板；於該金屬層進行圖案 金屬層之核心 該核心板上形成至少—開口。 形成—線路層，·以及於 於一個較佳實施例中 路增層結構之步驟。 匕在該線路層上形成一線 1 於一個較佳實施例中， — 為含膠量不同之材質所製成者。复二^層與该第二介電層 膠量低於該第二介電層。較佳者為’該第—介電層之含 動性之物質，而該第二介電層則具—介電層為低流 於一個較佳實施例中，對 _ 土之黏性及流動性。 程之步驟係採化學機械研磨。介電層進行平坦化製 化製程之步驟後藉由增層技^ ’ ^可選擇該進行平坦 透過前述本發明之製法中曰U° 保護層後，再將該晶圓背面研戶加^曰曰圓之主動面黏著 吁工加以缚化；然後將該晶圓 18101 8 1264805 =於一支承板後，再進行切割最 動面上的保護層。因此， 牙、日日®之主 , J解決習知技術中研声、望 中’該晶圓容易破裂所造成之種種問題，俾過程 個別晶片’使整體之體積更為輕薄短小。。更身之 同時，本發明係在進行 形成一線路增層社構，故一衣私後，藉由增層技術 的平整性，心；!Jr控制接置薄化晶片之表面 丨：私品質與電性連接可靠度之種種缺失。故，心：構之 有利於後續細線路製程之進行。 心用本發明 【實施方式】 以下係藉由特定的具體實施例說 式，熟習此技藝之人士可由本說明 方 瞭解本發明之其他優點與功效。本 T一内易地 的具體實施例加以施行或庫 ;;^可错由其他不同 可基於不同觀點與應用，在不 員、.、田即亦 種修飾與變更。 本杂月之精神下進行各 請參閱第3A圖至第3Nn 合半導體元件之製法的剖面示意圖。…、承载件中整 首先請參閱第3A至第开圖，係 之製程。 月之潯化晶片 如第3A圖所示，首先提供一晶圓卜 主動面la以及一非主動面lb。苴口具有— Ύ έ亥晶圓1可设姐达 -矽晶圓或砷化鎵(GaAS)晶圓，但非以此為限。、為 如第3B圖所示，接著於該晶圓]之主動面！"著— 9 18101 1264805 保護層3。 如第3C圖所示，之後對該晶圓 研声，頦yfl· # Θ m 1 非主動面1 b進行 汁以 >専化该晶0 1之厚度 一研磨機台（未圖示）内進行 /日日貝’丁、如移入 ^ ^ ^ 琨仃研磨，而使該晶圓1達到預 叹厗度。其中，研磨該晶圓i之 .預 不另為文贅述。 Μ屬業界習知者，故 於本實施例中，該保護層3可例如為 ; 片（tape)或平板，以於研磨期 ’、、子又：二之膠 h。但，於其他實施例中， 動面 所仏制上+ %保邊層3亦可為諸如剛性姑 貝所製成之藍寶石（Sapphire)、X梓力 材 士丄 ）不鐵鋼、或其他等效物株。 冋犄，由剛性材質所製成之保護 件 曰门 曼續3亦可於研磨時禪罐斗 日日圓1不致變形破裂。因此，σ 呆°蒦硪 主叙；士 ，、要可於研磨該晶圓1之非 主動面lb時可保護該主動面1 之非 明，而非侷限於本實施例中所述者。 、本毛 如第3D圖所示，於該經薄化 成一黏著層1c。該黏著声& 之非主動面lb形 彻“甘 層“糸如聚亞酿胺㈣yimide)、 、离寺、或其他具黏性之材質所製成 上士如第則所示，將該經薄化晶《Μ設置於-支承^ 广如圖所示’係將該晶《Μ之非主動面 支’： 5上，並藉由該黏著声lc將兮曰问， 直万…亥支承板 而。甘// 亥晶圓1固定於該支承板5夺 ，、中，该支承板5可為例如一切割架。 乂 如第3F圖所示，接著移除該保護層3並進行切單作 業，以將該晶圓1切割成複數薄化晶片u。 之後，如第3G至第31圖所示，俜A 士 口岍不知為本發明之承載件 ]8]〇] 10 1264805 製，而該承載件係可為陶£材料、❹… 有線路之電路板。本發明僅以其 ·〜’,a i »層或具 說明，惟並非用以限制其可實_圍兒路板實施例作詳細 如弟3G圖所示，當本發明之承載件 路板實施時，其主要製作方法如下 ，、有線路之電 7]，於該核心板71之上下表面:先提供一核心板 而各該全屬声72釗4叮达 ’、刀別形成—金屬層72, 。。乡至屬層72例如可為銅金 所構成。 蜀飞具他具導電性之金屬 如第3Η圖所示，係可選握 等方弋右兮 、 用機械鑽孔或雷射鑽孔 寺方式在该核心板71形成複數個 、，、_ 形成一電鑛導通孔，以漣Έ μ ，亚進行電鍵以 兒锁♦逋孔以連通上下表面的 ，田上 蝕刻技術形成-線路圖案化 θ ’亚利用如 件7。其中，該線路層721亦可選擇採曰用2 ’以形成該承載 方半於闰安儿 用黾錢（Electroplating) 方法灰圖案化之電鍍中形成細 亡问仏μ 略亚非以此為限。因此， 有關線路圖案化技術繁多，惟 苴非太安斗"从 乃業界所周知之製程技術， /、非本案技術特徵，故未再予贅述。 如第31圖所示，係可選擇利 以名兮·?甚a 用械械銑孔或雷射製孔， 以在忒承載件7形成至少一開口 74。 第3J至第3Κ圖所示者，係士夕石， 人係肸至少一薄化晶片11整 合於该承載件7之開口 74中。 接著’如第3 J圖所示，传斟认 ^ ? ^ 於欲整合該薄化晶片11 之考載仵7表面壓合一第一介電； 一 日5。如圖所示，係在該 核心板71底面壓合一第一介電 a ^ ^ ^ , 而该乐一介電層75 7送擇為例如背膠銅箔（Resi1264805 IX. Description of the invention: [Technical field to which the invention pertains] = day = related to the method of integrating a semiconductor component in a carrier, especially a method of fixing a thinned wafer, a garment [previously] n carrier Method of production. The sub-industry is booming, the electronic direction, and the shape is also facing the light and short side. "Therefore, how to do the simplification of the squeezing of the increasingly tight. The semi-conducting piece with high wiring density: inside, in the 曰曰On the sheet carrier, it is necessary to solve the problem. 1 It has become the process of the semiconductor device of the "Boundary-Core", firstly by the wafer carrier, Luodieping or wire mt, the carrier of the chip, such as various circuit boards. The wafer carrier is handed over to the semiconductor package, the filial piety is placed in the lamp, the Wei, the ridiculous foot semi-guided engraving & ^, soil, l and ball planting processes, etc. The six-integration degree (IntegmiQ_ and miniaturization ((ΓΓΓ咖iGn)) package requirements can be achieved by using the inter-layer connection technology to expand the available wiring surface on the A-board. By embedding the wafer in the pre-opened/opened hole of the board and fixing the wafer to the inner surface of the board, the circuit board structure is shown in Figure 2 to Figure 2. One and a half i: two : No, it is the wide and cloth parts proposed in U.S. Patent No. 6,7,9,898. The semiconductor package has a heat sink 102 as a carrier, and the heat sink (10) has at least one recess just to be connected by the recess #1〇4 - the semiconductor wafer n4. wherein the dust is combined] 〇] 1264805, "Electrical layer Π 2 in the semiconductor wafer]] 4 and the slab of the slab 2, the dielectric layer 112 is placed on the active surface of the semiconductor wafer 1] 4]], The inactive surface 1] 8 of the semiconductor wafer 114 is placed in the recess 1 〇 4 by a thermally conductive adhesive material 120. Moreover, the heat dissipation plate 102 and the semiconductor wafer 114 can be applied by a build-up technique. A line build-up structure 12 2 is formed thereon, as shown in Fig. 2. However, since the dielectric layer 112 has fluidity, the dielectric layer ι 2 will enter between the semiconductor wafer 114 and the recess ι 4 After the gap, the "electric layer 112 surface is formed with a plurality of recesses. As a result, the dielectric layer 112 is not sufficiently "will affect the reliability of the subsequent process and the electrical connection of the line build-up structure. In order to make the volume of the I body thinner and thinner and to set more main force components, the back side of the wafer is added. Then cut into the , to get the damage of the / ά ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Manufacturing of the port 3 cymbal bearing member and semiconductor packaging technology, ::, ''Uniform control of the surface of the carrier attached to the wafer is steep and steep, and the sub-effectively reduces the break of the wafer 1 +1 [Inventive content] The problem that needs to be grasped. Providing the shortcomings of the technology, the main purpose of the present invention is to form a method for forming a "two" body element, so that the carrier is carried out. The surface is kept flat, and the subsequent layer is added. Line system 18101 1264805 This rabbit is also provided for the purpose of making the component in order to make the overall structure thin: "The fragmentation rate of the bean wafer. #化之...Reduced Grinding and Addition A further object of the present invention is to provide an integrated semi-conducting raft in a carrier. The 曰日片 is easily placed and placed in the core for the above purposes and other purposes. The semiconductor is invented in the carrier. The 曰 曰 + branch includes: Bai Xian provides at least one thinning system with - an active surface and a non-active surface; an opening bearing member; forming a first surface on the bottom surface of the carrier member: ^ to two non-active surfaces are combined in the middle portion; forming a second surface of the thinned wafer Dielectric; Table: and;: the carrier and the thinning and planarizing process to keep the surface of the second dielectric layer flat: the surface of the layer is in a preferred embodiment, the thin one has an active surface and - The non-active process system includes: providing a surface formation - a protective layer, and then a material: a non-active surface of the wafer is actively formed on the wafer, face-in: grinding; re-wafer Set on the support plate. " Hunting from the 5 HAI adhesive layer to the beep. And, then remove the enamel on the active surface of the wafer to second and slice the wafer to form a plurality of thinning Wafer. In a preferred embodiment, at least the step of thinning the opening of the wafer member comprises: heating the thinned cladding to make the thinned crystal; and placing the wafer on the carrier - The day piece and the 4 piece are on the surface of the first dielectric layer. 8] 〇] 1264805 In another preferred embodiment, the step y to the opening of the + piece 曰曰 "integration of the cymbal into a carrier 包括 system includes the first mediated egg in the thin opening The sheet is placed directly on the carrier, and in the first dielectric layer, the first layer is uncured. The layer is cured, and the thinned wafer is fixed to the substrate. After the thinned wafer is placed in the receiving member, the carrier and the thinned wafer are formed on the surface, and subsequently attached to the carrier. The brother-"黾a layer for thinning in a preferred embodiment, the step of carrying the circuit board includes: providing a pen board, and forming a plate; forming a core of the patterned metal layer on the core layer of the metal layer At least - opening. forming a circuit layer, and in the preferred embodiment a step of adding a layer structure. 匕 forming a line 1 on the circuit layer. In a preferred embodiment, - a material having a different amount of glue The finished product has a lower amount of glue than the second dielectric layer and the second dielectric layer a dielectric layer, preferably a material of the first dielectric layer, and a second dielectric layer having a low dielectric flow in a preferred embodiment, Viscosity and fluidity. The steps of the process are chemical mechanical polishing. After the dielectric layer is subjected to the planarization process, the layering technique can be selected to perform the flat transmission through the aforementioned method of the present invention. ° After the protective layer, the active surface of the wafer on the back of the wafer is adhered and bonded; then the wafer 18101 8 1264805 is placed on a support plate, and then the cutting surface is cut. The protective layer. Therefore, the master of the tooth, the day of the day, J solves the problem of the sound of the conventional technology, and the problems caused by the easy cracking of the wafer, the process of individual wafers makes the overall volume thinner and shorter. At the same time, the invention is in the process of forming a line-increasing layer structure, so that after a private dress, by the flatness of the layer-adding technology, the heart; Jr controls the surface of the thinned wafer: private quality There is a lack of reliability with electrical connections. Therefore, the heart: the structure is beneficial to the post The present invention will be understood by those skilled in the art from the following description. Other advantages and effects of the present invention will be apparent to those skilled in the art. The specific embodiment can be implemented or stored in the library;;^ can be mistaken by other differences and can be based on different viewpoints and applications, and is not modified, and is also modified and changed in the field. Please refer to Figure 3A for the spirit of this month. A schematic cross-sectional view of the method for fabricating the 3Nn semiconductor device. ..., the first part of the carrier is referred to the 3A to the first drawing, and the process is the same. The wafer of the moon is shown in FIG. 3A, and a wafer is first provided. The active surface la and the non-active surface lb. The 具有 具有 晶圆 晶圆 wafer 1 can be set up with Suzuki-矽 wafer or gallium arsenide (GaAS) wafer, but not limited to this. , as shown in Figure 3B, followed by the active side of the wafer]! "着— 9 18101 1264805 Protective layer 3. As shown in Fig. 3C, the wafer is then ground, 颏yfl·# Θ m 1 inactive surface 1 b is juiced > the thickness of the crystal 0 1 is reduced into a polishing machine (not shown) Performing / day-day ding, such as moving into ^ ^ ^ 琨仃 grinding, so that the wafer 1 reaches the pre-sigh. Among them, grinding the wafer i is not mentioned in the text. It is a well-known person in the industry. Therefore, in this embodiment, the protective layer 3 can be, for example, a tape or a flat plate for the grinding period, and the second and second glues h. However, in other embodiments, the + % edge layer 3 can be made of a sapphire (Sapphire), a non-ferrous steel, or the like. Effect strain.冋犄, a protective member made of a rigid material. The door can also be used to grind the Zen tank. The Japanese yen 1 will not be deformed and broken. Therefore, it is necessary to protect the active surface 1 from grinding when the non-active surface 1b of the wafer 1 is polished, and is not limited to the one described in the embodiment. The hair is thinned into an adhesive layer 1c as shown in Fig. 3D. The non-active surface of the adhesive sound & lb-shaped "Gan layer", such as poly-araminide (four) yimide), from the temple, or other viscous material made by the sergeant as shown in the first paragraph, the Thinning crystal "Μ set in - support ^ as shown in the figure" is the crystal "Μ non-active surface support": 5, and by the adhesion sound lc will ask, straight Wan...hai support plate and. The galvanized wafer 1 is fixed to the support plate 5, and the support plate 5 may be, for example, a dicing frame.乂 As shown in FIG. 3F, the protective layer 3 is then removed and a singulation operation is performed to cut the wafer 1 into a plurality of thinned wafers u. After that, as shown in Figures 3G to 31, 俜A 士口岍 is not known as the carrier of the present invention] 8] 〇] 10 1264805, and the carrier can be made of materials, ❹... circuits with lines board. The present invention is only described in terms of its layer, or is not limited to the embodiment of the road plate, as shown in detail in Figure 3G, when the carrier plate of the present invention is implemented. The main production method is as follows, there is a line of electricity 7], on the lower surface of the core board 71: first provide a core board and each of the sounds 72 钊 4 叮 、, knife formation - metal layer 72, . . The township-to-generator layer 72 can be made of, for example, copper gold.蜀 具 他 他 他 他 他 他 他 他 他 他 他 他 他 他 他 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属 金属An electric mine conduction hole, with 涟Έ μ , sub-keys to lock 逋 逋 hole to connect the upper and lower surfaces, the field etching technology formed - line patterning θ 'U use as a piece 7. Wherein, the circuit layer 721 can also select 2' for picking, to form the carrier, and to form a thin layer in the electroplating of the electroplating method (Electroplating). . Therefore, there are many kinds of circuit patterning techniques, but it is not a process that is well known in the industry, and is not a technical feature of this case, so it will not be repeated. As shown in Fig. 31, it is possible to select a hole in the machine or a hole in the laser to form at least one opening 74 in the crucible carrier 7. As shown in Figs. 3J to 3, a thinner wafer 11 is integrated into the opening 74 of the carrier member 7. Then, as shown in FIG. 3J, the surface of the test substrate 7 to be integrated with the thinned wafer 11 is pressed to a first dielectric; As shown in the figure, a first dielectric a ^ ^ ^ is pressed on the bottom surface of the core board 71, and the Le dielectric layer 75 7 is selected, for example, as a backing copper foil (Resi
〇ated copper，RCC)、ABF η 18101 1264805 (Ajinomoto build-up film)、pp(pre„preg)、以及 βΤ (Bismaleimidetriazine)等所製成。 隨後’如第3K圖所示，將号舊/μ曰 肘邊溥化晶片11整合至承載 件7之開口 74。其中，各簿什曰H ]飞π /寻化日日片11得以係如晶片吸取 設備（圖式中未表示）吸取，而置於該承載件7之開口 ％ 中。由於該晶片吸取設備及其吸取原理俱為習知技術，且 並非本案特徵’故不多作說明。 化W中，係先加熱該薄化晶片u，令該薄化晶 將”之：者層1C (如弟3 F圖所示）軟化並產生黏性，再 ：置於該承載件7之開内之第—介電 ^M；V 該黏著層1e可為例如膠膜。而且，於本 知例中，係形成可爲-正方形或長方形之開口 、t 以供收納該薄化晶片1 i ’然而，於其他 、幵^ 擇形成至少-狹槽以供收納該薄化晶“二可選 件，而非侷限於此。 次一他笔子元 轶者，如 1<费从 你對於欲整合該薄化曰Η 件7表面壓合-第二介電層76。如圖所 曰曰 心板71頂面及薄化晶片U之非 ’、係在纪 命居γ 斤 王動面lb上壓合一輦一 包層76，而該第二介電層76 。弟一 ABF、pp、BT等所製成。 ”、、歹1如背膠銅箔 、於本實施例中，該第一介電層75 _八 為含膠量不同之材質所製成 —j丨電層76 m ^ ^ 運用該第一介 恥置較低而具有較低之流動性，1包層75之含 量則較高而具有較佳之黏性及、_ <弟；丨甩層76之含勝 及，。如此-來，第―、 18101 12 1264805 二介電層75,76於進 部分該第二介泰厚7“ “至違核心板日寺.便可使 电运76 w入該薄化晶片J ]盥 間隙，以確實將爷舊# B u ，、4開口 74間之 隹貝亂專化晶片u固定於承載件7中。 、，，、、'、後，如第3M圖所示，對該第二介電層76 > 平坦化製程，以使該第__介命 、仃 可進行例如化學機找I; 表面保持平整。其中， CMP) ' 1： (Ch--l Machine P〇lishing? 而神的Ϊ 式，讓該第二介電層76表面達到全 .面性，平坦化，以利後續製程之進行。 最後，如第3Ν圖所+，π 4曰# + 721上形成一線路” μ 輕乂據貫際需要在該線路層 4、果路心層結構77，係在該第二介 成線路層771及導電盲孔77 : 形 利用增犀法ΓΒ丨]ϋ 方、本只鈀例中，係可選擇 θ UP Pl〇CeSS)，如全加成法(Full additive -叫、_加成法（Semi_additivepr〇cess)、或減成法 (Subtractive process) ^ ^ ^ ^ ^ ^ ^ ^ ^ 構77。1中, ，口木化之線路增層結 .X„4. 乂 成法、半加成法、以及減成法均屬孝 ►"自知者，故於此不再多作說明。 業 敕1 於係採平坦化製程使該第二介電層％表面保持平 :，相％C於習知技術，應用本實施例之承載件7 層表面。 、〃、化、、泉路有效且平整地形成於該介電 月/上所述之具體實施例，僅係用以例釋本發明之特點 ^效，而非用以㈣本發明之可實施範_。舉例來說、、、， 本貫域係將具黏著層之薄化晶片整合至承載件，作於复 他實施例中，亦可將不具黏著層之薄化晶片直接置於該i 1810] 13 1264805 載件之開口。如此，在整合薄化aa 預先加熱該薄化 ：八載件時，可省略 置於該承載件7之開口 7二第=薄化晶片π直接 第-介電層75未固化前黏著 ：'：層75上，並由該 ^ 考而在該第一 後以將該薄化晶片u固定於 ：層75固化 介電層76淥入每仆曰Hll # 或可再藉由第二 固… 弟二介電層76將該薄化曰片η 口疋於该承載件7之開口 74内。 匕日日片11 同¥，於其他實施例中，亦豆帝 承載件。舉例來說，於第卞子元件整合至 電子元I ，亦可先在承載件7表面設置至少- 然後再於承载件為動兀件或被動元件， 如第^該第二介電層％。之後， 程。最後，如第3Nn / 表面進行平坦化製 路增声^77 & ㈣線路層721上形成該線 吩’日尽、答口構7 7 〇如此，係^p脸士 ^ 片U盥電子… 本發明應用於整合有薄化晶 乃1 1只甩子兀件9之承載〇ated copper, RCC), ABF η 18101 1264805 (Ajinomoto build-up film), pp (pre„preg), and βΤ (Bismaleimidetriazine), etc. Subsequently, as shown in Fig. 3K, the number is old/μ The elbow-side wafer 11 is integrated into the opening 74 of the carrier 7. The books of the H 飞 寻 / 寻 日 日 11 can be sucked by a wafer pick-up device (not shown). In the opening % of the carrier member 7. Since the wafer pick-up device and the principle of suction thereof are all known techniques, and are not characteristic of the present invention, the description is not made. In the case of W, the thinned wafer is heated first. The thinned crystal will soften and form a viscous property, and then: the first dielectric layer placed in the opening of the carrier member 7; V; the adhesive layer 1e It can be, for example, a film. Moreover, in the present example, an opening which is a square or a rectangle, t is formed for accommodating the thinned wafer 1 i 'however, at least a slit is formed in the other to accommodate the thinned crystal "The second option is not limited to this. The next one is his pen 轶 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The top surface of the core plate 71 and the thinned wafer U are not combined with a cladding layer 76, and the second dielectric layer 76. , pp, BT, etc. made of ",", 歹 1 such as a backing copper foil, in the present embodiment, the first dielectric layer 75 _ eight is made of a material having a different amount of glue - j electrical layer 76 m ^ ^ using the first shame is lower and has lower fluidity, the content of one cladding 75 is higher and has better viscosity and _ <弟;丨甩; and,. So - come, the first, 18101 12 1264805 two dielectric layers 75, 76 in the part of the second Jietai thickness 7 "" to the core board of the Japanese Temple. You can make the electric transport 76 w into the thinned wafer J] The gap is fixed in the carrier 7 by the mussel specialization wafer u between the 74 and the 4 openings. ,,,,, and after, as shown in FIG. 3M, planarizing the process for the second dielectric layer 76 > so that the first aging can be performed, for example, by a chemical machine; smooth. Among them, CMP) ' 1: (Ch--l Machine P〇lishing? and God's formula, let the surface of the second dielectric layer 76 reach full surface, flattened, in order to facilitate the subsequent process. Finally, As shown in Fig. 3, a line is formed on π 4曰# + 721. μ 乂 乂 乂 乂 乂 乂 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 771 771 771 771 771 771 771 771 771 771 771 771 771 Blind hole 77: Shape using the rhinoceros method ΓΒ丨] ϋ square, this palladium case, can choose θ UP Pl 〇 CeSS), such as full additive method (Full additive - called, _ addition method (Semi_additivepr〇cess ), or Subtractive process ^ ^ ^ ^ ^ ^ ^ ^ ^ In the structure of 77. 1, the line of the mouth of the wood is increased. X „4. 乂 method, semi-addition method, and reduction The method is filial ►"self-knowledge, so there is no longer any explanation here. Industry 敕1 is a flattening process to keep the surface of the second dielectric layer flat: %C in conventional technology Applying the surface of the 7-layer layer of the carrier member of the embodiment, the 〃, 、, and 泉路 are effectively and evenly formed on the dielectric month/above, and are merely used to illustrate the features of the present invention. Instead of using (4) an implementable method of the present invention, for example, the present embodiment integrates a thinned wafer with an adhesive layer into a carrier, and in the embodiment, it may not have The thinned wafer of the adhesive layer is directly placed on the opening of the i 1810] 13 1264805 carrier. Thus, when the thinning: a carrier is preheated by the integrated thinning aa, the opening 7 of the carrier 7 can be omitted. The first thinned wafer π direct first dielectric layer 75 is uncured before the adhesion: ': layer 75, and by this test, after the first to fix the thinned wafer u to: layer 75 cured dielectric The layer 76 is immersed in each servant Hll # or may be entangled in the opening 74 of the carrier member 7 by the second dielectric layer 76. 匕日日片11 with ¥ In other embodiments, the bean carrier is also provided. For example, the second component is integrated into the electronic component I, and the surface of the carrier 7 may be first disposed at least - and then the carrier is passive or passive. The component, such as the second dielectric layer %. After that, finally, as the 3Nn / surface is flattened, the road is boosted ^77 & (four) line The line 721 is formed on the line 721, and the answer is 7 7 〇. The system is used to integrate the thinned crystals and the 11 pieces of the electronic components. Bearer
圖之順序亦可加以變化 ’ * 至第3L 合於-承載件之開口中，個該薄化晶片整 下表面分別加熱陶一第：;:5:化晶片之承載件上 發明。 一 及弟-介電層者皆適用於本 :亡可知’本發明係於晶圓薄化製程中先將晶圓非主 t 如朦膜之黏著層以及在晶圓主動面黏貼保護層， ~後進饤缚化，然後將經薄化晶圓貼置於諸如切割架之支 ]8]〇] 14 1264805 f板’再除去保護層以進行切割。如此，可由該支承板妹 涛化^0製程中避免於去除保護層後產生破片現象。而 且斜=別形成之各薄化晶片以諸如晶片吸取設備吸取， 化晶片加熱，以使晶背上之膠膜軟化並具黏性， =專：晶片置於承載件之開口中之介電層上，接著再全 成介電層；而最後，便對該介電層進行平坦化’ 以利後績進行線路增層製程。 戶斤34，本發明係可使承載件表面所壓合的介電層 發明，俾利後續線路增層製程之進行，且應 整體結構薄化之際，™^ =實_僅為例示性說明本㈣ ==發明。任何所屬技術領域具有通二 修飾*變：：因：明ί精神及範° 壽下，對上述實施例進行 申靖專利^本發明之_簡範圍，應如後述之 〒明專利乾圍所列。 【圖式簡單說明】 :1以及第2圖係為美國專利第6,7 出的半導體裳置之剖面示意圖； 5 虎案所棱 體元係爲本發明之於承載件中整合半導 衣法之w程示意圖；以及 第3L’至第3N，圖传第3L 5楚⑽m 程示意圖。 口知弟几至乐3N圖之另一實施之製 【主要元件符號說明】 18101 15 1264805The order of the figures can also be changed. ** The third surface of the thinned wafer is heated in the opening of the carrier, and the entire surface of the thinned wafer is heated on the carrier of the wafer: One and the younger-dielectric layer are suitable for this: It is known that the invention is based on the adhesion layer of the wafer non-master t such as the germanium film and the protective layer on the active surface of the wafer in the wafer thinning process. After the shackles are tied, the thinned wafers are then placed on a support such as a cutting frame. 8 1 264 805 f plate 'removal of the protective layer for cutting. In this way, the chipping phenomenon can be avoided by removing the protective layer from the process of the support plate. Moreover, the thinned wafers which are formed separately are sucked by, for example, a wafer suction device, and the wafer is heated to soften and adhere the film on the crystal back, and the dielectric layer is placed in the opening of the carrier. Then, the dielectric layer is further formed; and finally, the dielectric layer is planarized to facilitate the line build-up process. The utility model is characterized in that the dielectric layer which can be pressed on the surface of the carrier member is invented, and the follow-up line build-up process is carried out, and the overall structure is thinned, TM^ = real_ is only an illustrative description This (four) == invention. Any one of the technical fields has the following two modifications:: because: the spirit of the spirit and the scope of the life, the application of the Shenjing patent to the above embodiment, the scope of the invention, should be as listed in the following paragraph . [Simple description of the drawings]: 1 and 2 are schematic cross-sectional views of the semiconductor skirts of U.S. Patent No. 6,7; 5 The prismatic elements of the tiger case are the integrated semi-guided clothing method in the carrier of the present invention. Schematic diagram of the w-range; and 3L' to 3N, the diagram shows the 3L 5 (10) m process diagram. Another implementation of the mouth of the brother to the music 3N diagram [main symbol description] 18101 15 1264805
102 散熱板 104 凹部 112 介電層 114 半導體晶片 116 主動面 118 非主動面 120 熱傳導黏著材料 1 晶圓 11 薄化晶片 la 主動面 lb 非主動面 1 c 黏著層 3 保護層 5 支承板 7 承載件 71 核心板 72 金屬層 721 線路層 73 開孔 74 開口 75 第一介電層 76 第二介電層 77 ^ 122 線路增層結構 771 線路層 772 導電盲孔 9 電子元件 16 ]8]0]102 heat sink 104 recess 112 dielectric layer 114 semiconductor wafer 116 active surface 118 inactive surface 120 heat conductive adhesive material 1 wafer 11 thinned wafer la active surface lb inactive surface 1 c adhesive layer 3 protective layer 5 support plate 7 carrier 71 core board 72 metal layer 721 circuit layer 73 opening 74 opening 75 first dielectric layer 76 second dielectric layer 77 ^ 122 line build-up structure 771 circuit layer 772 conductive blind hole 9 electronic component 16 ] 8] 0]