1264662 九、發明說明： 【發明所屬之技術領域】 本發明係提供一種實現電路佈局的方法，尤指一種在每 個電路單元中取消帶狀電源佈局以縮減電路單元高度、增 加積體電路集積度的電路佈局實現方法。 【先前技術】 半導體積體電路是現代化資訊社會最重要的硬體基礎 之一，如何提高積體電路的集積度’讓積體電路的佈局面 積能夠更有效率地被運用，也成為現代半導體工業的研發 重點。 一般來說，功能複雜的積體電路都是由一群具有基本功 能的電路單元(cell)組合出來的。舉例來說，數位積體電路 中常會以各種邏輯閘（像是及閘、或閘、反相器等等）、正 反器（flip-flop)、加法器、計數器（counter)等等電路單元來 組合出積體電路的整體功能。在實現特定功能的積體電路 時，首先就是以基本電路單元來組合架構出積體電路的整 體功能；選擇所需的基本電路單元後，就能規劃半導體積 體電路的佈局設計，進而實際製造出半導體積體電路。如 1264662 熟悉技術者所知，半導體電路是以不同性質的半導體層疊 積而成，在不同的半導體層上進行不同的佈局，就能具體 實現出各種電晶體與電晶體間連線，進而組合出各個電路 單元，乃至於整個積體電路。 為了便利積體電路的設計，半導賤業者會將常用的電路 單元及其對應之佈局設計建立為一電腦的資料庫 (library)。在設計積體電路時’料者先依積體電路之功能 在資料庫中選定其所需的電路單元，再由資料庠中將這些 電路單元所對應的佈局設計加以排列、組合，就能完成積 體電路整體的佈局設計，並以半導體製程具體地製造出所 需的積體電路。 請參考第1圖。第1圖即為習知技術以資料庫中電路單 元之佈局設計來實現積體電路整體佈局的示意圖。在此習 知技術中，資料庫（library)lO中s己錄有複數個電路單元 Ρ(1)、Ρ(2)···Ρ(ηι)至P(M)的佈局設計。在各個電路單元的佈 局設計中，會包括有作用區（active regi〇n)佈局df (像是摻 雜井、擴散區的佈局位置）、多晶矽佈局Pi、第1金屬層佈 局mtl、第2金屬層佈局mt2以友接點/穿礼（contact/via)佈 局ct等等。不同的作用區、多晶矽佈局可形成電晶體的基 1264662 本半導體架構（像是金氧半電晶體中的源極、汲極與閘 極），各個金屬層可連接不同的電晶體，接點/穿孔佈局則 可將不同層的佈局連接起來，像是將金屬層mtl的走線連 接於金屬層mt2的走線；某些接點/穿孔則形成各個電路單 元的訊號輸入端、輸出端，也就是各個電路單元的訊號佈 局。根據這些不同半導體層的佈局設計，就能在各個電路 單元中組合出各種電晶體，進而實現各個電路單元的基本 功能。 值得注意的是，在習知技術中，各個電路單元都會以金 屬層佈局（像是第1金屬層佈局）來形成帶狀(Strip)的電源 佈局。如熟悉技術者所知’各個電路单元中的電晶體需要 連接至適當的直流偏壓電源(power)，像是直流供電電壓 Vdd或是地端電壓（譬如電壓Vss)等等；而在習知技術的 電路單元中，就會在各個電路單元中設置橫貫的帶狀電源 佈局pwl、pw2，以使得各個電路單元能經由這些帶狀電源 佈局連接至直流電源。基本上，每個電路單元中的帶狀電 源佈局是橫貫於電路單元的相異兩侧（如第1圖所示），使 得各個電路單元在比鄰排列時，各個電路單元的電源佈局 能銜接在一起，共同揍收直流偏壓電源。 1264662 舉例來t兒，在設計一積體電路12時，若積體電路12中 需要電路軍元p(m)及p(M)，設計者就能由資料庫10中將 電路單元P(m)、P(M)的佈局設計找出，並列於積體電路12 的整體佈局中，使電路單元P(m)、P(M)的帶狀電源佈局相 互連接。接下來，使用者可進行一繞線(routing)程序，適當 地將各個電路單元中的訊號輸出入接點/穿孔連接起來，組 馨合出積體電路的整體功能。像在第1圖的示意例中，此繞 線程序可能會在第2金屬層上用一特定的繞線佈局rtO將電 路單元P(m)的某一接點/穿孔與電路單元P(M)的某一接點/ 穿孔連接起來，以使這兩個電路單元中的訊號佈局能彼此 ’相連，並能互相交換訊號，發揮整體功能。完成繞線程序 的繞線佈局後，就能完成積體電路12的整體佈局設計，益 進行半導體製程，實際製造出半導體積體電路。 不過，上述的習知技術也有缺點。其缺點 n ，’γ 尤疋 每個電路單元的佈局設計中均包括有帶狀的電源佈局 pwl、pw2。此種佈局設計的原意是讓使 ° +爲特別設 電源佈局，因為各個電路單元在排列組合時其帶狀兩 局自然會互相銜接，形成積體電路中整體的電源佈=源 而，此種帶狀電源佈局設計也會佔用相當 °。」 — j回積，使久 電路單元的高度（也就是兩個帶狀電源佈局間的距離口 1264662 第i圖所示）無法減低。電路單元的高度無法減低，也就 會使每個電路單元的佈局面積無法縮減，無法有效增加半 導體積體電路的集積度。 【發明内容】 因此，本發明之主要目的，即在於提出一種較佳的電路 佈局實現（設計/製造）方法，在每個電路單元中取消帶狀 的電源佈局，以縮減每個電路單元的高度及面積’並能有 效地增加半導體積體電路的集積度。 在本發明中，係在每個電路單元中以格點之電源接點/ 穿孔來取代習知技術中的帶狀電源佈局。在設計積體電路 的整體佈局時，設計者可選定、排列其所需的電路單元， 再於繞線程序中，順帶地繞線連接各個電路單元中的電源 接點。換句話說，在本發明中，本發明之電路單元不需再 設置帶狀的電源佈局；各個電路單元在鄰接排列後，各個 電路單元的電源接點/穿孔（格點電源佈局）不會直接互相 連接，而是在繞線程序中才繞線而連接各個電路單元的電 源接點/穿孔。 由於本發明之電路單元可排除帶狀之電源佈局，故本發 1264662 明可有效地減少各個電路單元的佈局高度及面積，提高積 體電路的整體集積度。另外，在現代的半導體工業中，繞 線程序已經是一個高度自動化的程序，利用繞線程序來形 成電路單元間的電源佈局並不會增加繞線程序的複雜程 度，還能使電路單元間的佈局更有彈性，不再像習知技術 中僅能偈限於各個電路單元既有的帶狀電源佈局。 針對現有的製程可發現，本發明可使每個電路單元的高 度縮減更多。舉例來說，在習知技術中原本高度為1〇間距 (pitch，在.13微米製程中，一個間距相當於0.28微米）的電 路單元，本發明可將其高度縮減為8間距。既然本發明能 使電路單元的高度（面積）能有所縮減，自然就能提高積 體電路的集積度，充分利用積體電路的佈局面積。 【實施方式】 請參考第2圖；第2圖即以本發明之電路單元來實現（設 計/製造）半導體積體電路之示意圖。在本發明之資料庫20 中，同樣記錄有複數個電路單元C(l)、C(2)...C(n)至C(N) 的佈局設計；各電路單元可作為積體電路的基本構築方 塊。舉例來說，各電路單元可以是數位電路中的各種邏輯 閘、正反器、加法器、計數器等等。在各個電路單元的佈 1264662 局設計中，至少可具有（但不受限於）作用區佈局df (可 以包括換雜井及/或擴散區）、多晶石夕佈局pl、接點/穿孔佈 局ct以及第1金屬層佈局_、第2金屬層佈局mt2等等。 作用區佈局df/多晶石夕佈局pl可在各個電路單元中形成電 晶體的基本架構’接點/穿孔佈局etj連接不同半導體層的 佈局，紋將各個電晶體連接於金屬層；而金屬層佈局 -、⑽上之繞線就能將各個電路單元中的電晶體連接在 -起’以麟各個轉單元縣本舰。料，各電路單 :中的某雜點/穿關軸各個魏單元的訊號輸入 端、輸出端，也就是訊號佈局設計。 本發明的重點之一，古t Η — — y ”之就疋在母個電路單元中改用柊點之 =穿孔作為電源佈局來接收運作的電力 == 術中所使用的帶妝 取代白知技 每個電路單μ 圖所示，在本發明的 的電源佈局pel L佈局來料各個電路單元 佈局pel、Ρ^、Γ使各個電路單元可經由這些電源 像是直^電=別連接ί不㈣直流偏壓電源(ρ叫， 等。這樣:Wd或二地h電壓（譬如電壓VSS)等 向兩側的帶狀+ ^ ^在母個电路早70巾省去橫貫連接對 積。讀電源佈局，以降低每個電路單⑽高度及面 1264662 如第2圖所示意的，在以本發明實現一積體電路22之 佈局設計時，設計者可先依據積體電路22的功能需求而選 出適用的電路單元，再由資料庫20中將這些電路單元的佈 局設計調出來’套用至積體電路22的佈局設計上。由於本 發明之各個電路單元並沒有帶狀的電源佈局，故各個電路 單元（假設是電路單元C⑻及C(N))在相鄰並排後，其電 源佈局pci、Pc2 (也就是格點之電源佈局）並不會互相連 接。接下來，在繞線程序中，一方面可將各個電路單元的 訊號佈局（也就是訊號接點/穿孔）繞線連接起來，另一方 面就可將各個電路單元的格點電源佈局繞線連揍起來。這 樣一來，不但能整合各個電路單元的功能而使積體電路22 發揮應有的功能，還能使各個電路單元間的電源佈局連接 起來。像在第2圖的示意例中，繞線程序會以繞線佈局rtl •來連接電路單元C(n)、C(N)的訊號接點/穿孔，並分別以繞 線佈局prl、pr2來使電路單元c(n)、C(N)的電源佈局pcl、 Pc2能共同連接至各個電源（像是電壓Vdd及Vss)。 換句話說，本發明是將各個電路單元中格點之電源佈局 田作疋矾號接點/穿孔的一種，在繞線程序中統一將各電路 單元中分散的電源佈局繞線連接起來，完成積體電路中的 整體電源佈局。在現代的半導體工業中，繞線程序已經可 1264662 以藉由電子自動化設計工具（EDA tool，Electronic Design Automation)而以高度自動彳b的方式來完成，故本發明並不 會增加繞線程序的複雜程度。事實上，本發明在繞線程序 才形成電路單元間的電源佈局繞線連接不僅能有效縮減每 個電路單元的高度及面積，也能增加電路佈局的設計彈 性，不必像習知技術一般受限於各個電路單元原本的帶狀 _電源佈局。在習知技術中，各個電路單元的帶狀電源佈局 會設置於第1金屬層；而在實際實施本發明之技術時，則 可利用第2金屬層（metal 2)來實現電路單元間的電源佈局 繞線連接以及訊號佈局繞線連接。當然，本發明也可利用 不同的金屬層來分別實現電路單元間的電源佈局繞線連接 與訊號佈局繞線連接。 | 為進一步說明本發明之優點，請繼續參考第3圖；第3 圖比較了本發明電路單元C0與習知技術電路單元P0的電 路举元南度。由於本發明之電路早元改用格點之電源佈 局，而此格點之電源佈局就可内縮於電路單元中，省去了 帶狀電源佈局所佔用的高度與面積。這樣一來，本發明就 可以有效縮減每個電路單元的高度與面積，進而增加半導 體積體電路的集積度。以實際的例子來進行比較，在本發 明中，電路單元的高度（如第3圖所標示）可包括有N型 1264662 /P型金氧半電晶體作用區中第1金屬層之間距(metal 1 pitches in NMOS/PMOS active area) 1·92 微米，加上第 1 金 屬層上走線的間距（spacing of metal 1 to metal 1)0· 12 微 米，其電路單元的總高度就是2·04微米，以一個間距為0·28 微米來計算，本發明電路單元之高度為8個間距(pitch)。 相較之下，在習知技術中，除了上述之基本高度之外，還 要另外加上帶狀電源佈局之高度，也就是在P型金氧半電 晶體處需要佔用0.35微米，在N型金氧半電晶體處需佔用 另外0.35微米，故總高度會增加為2.04+0.35+0.35二2.74微 米，以一個間距為0.28微米來計算，其電路單元的總高度 為10個間距。由此例可知，本發明的確可將電路單元的高 度由習知之10間距縮短為8間距，進而提高半導體積體電 路的集積度。 總結來說，本發明是在每個電路單元中以格點之電源佈 局來取代習知電路單元的帶狀電源佈局，在繞線程序中才 連接各個電路單元的電源佈局。所以，相較於習知技術， 本發明能有效地減少每個電路單元的高度及面積，進而增 加積體電路的集積度，充分利用積體電路的佈局面積。 1264662 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知技術以電路單元實現積體電路的示意圖。 第2圖為本發明以電路單元實現積體電路的示音圖。 第3圖為習知技術電路單元與本發明電路單元:高度比較 示意圖。 【主要元件符號說明】 10、20 資料庫 12、22 積體電路佈局 P(1)-P(M)、C⑴·C(N)、P〇、c〇 電路翠元 pwl-pw2、pcl_pc2 電源佈局 mtl-mt2 ct pi df rt0，rtl、prl、pr2 金屬層佈局 接點/穿孔佈局 多晶梦佈局 作用區佈局 繞線佈局1264662 IX. Description of the Invention: [Technical Field] The present invention provides a method for realizing circuit layout, in particular, a strip power supply layout is eliminated in each circuit unit to reduce the height of the circuit unit and increase the integrated circuit accumulation degree. The circuit layout implementation method. [Prior Art] Semiconductor integrated circuit is one of the most important hardware foundations of the modern information society. How to improve the accumulation degree of integrated circuits? Let the layout area of integrated circuits be used more efficiently, and become the modern semiconductor industry. The focus of research and development. In general, complex integrated circuits are assembled from a group of basic functional cells. For example, in a digital integrated circuit, various logic gates (such as gates, or gates, inverters, etc.), flip-flops, adders, counters, and the like are often used. To combine the overall function of the integrated circuit. In the realization of a specific function of the integrated circuit, the first is to combine the overall function of the integrated circuit with the basic circuit unit; after selecting the required basic circuit unit, the layout design of the semiconductor integrated circuit can be planned, and then the actual manufacturing A semiconductor integrated circuit. As known to those skilled in the art, the semiconductor circuit is formed by stacking semiconductors of different properties, and different layouts are performed on different semiconductor layers, so that various wirings between the transistors and the transistors can be realized, and then combined. Each circuit unit, or even the entire integrated circuit. In order to facilitate the design of the integrated circuit, the semi-conductor will establish the commonly used circuit unit and its corresponding layout design as a computer library. When designing the integrated circuit, the material operator selects the required circuit unit in the database according to the function of the integrated circuit, and then arranges and combines the layout designs corresponding to these circuit units in the data frame. The overall layout design of the integrated circuit, and specifically the required integrated circuit is fabricated by a semiconductor process. Please refer to Figure 1. Fig. 1 is a schematic view showing the overall layout of the integrated circuit by the prior art in the layout design of the circuit unit in the database. In this prior art, a database has been recorded with a plurality of circuit elements Ρ(1), Ρ(2)···Ρ(ηι) to P(M). In the layout design of each circuit unit, an active regi〇n layout df (such as a doping well, a layout position of a diffusion region), a polysilicon layout Pi, a first metal layer layout mtl, and a second metal are included. The layer layout mt2 is in a friend/contact/via layout ct and the like. Different regions of action, polysilicon layout can form the base of the transistor 1466662. The semiconductor architecture (such as the source, the drain and the gate in the MOS transistor), each metal layer can be connected to different transistors, contacts / The perforation layout can connect the layouts of different layers, such as connecting the trace of the metal layer mtl to the trace of the metal layer mt2; some contacts/punches form the signal input end and output end of each circuit unit, It is the signal layout of each circuit unit. According to the layout design of these different semiconductor layers, various transistors can be combined in each circuit unit, thereby realizing the basic functions of each circuit unit. It is worth noting that in the prior art, each circuit unit is formed with a metal layer layout (such as a first metal layer layout) to form a strip power layout. As is known to those skilled in the art, the transistors in the various circuit units need to be connected to a suitable DC bias power source, such as a DC supply voltage Vdd or a ground terminal voltage (such as voltage Vss), etc.; In the circuit unit of the technology, the traversing strip power supply layouts pw1, pw2 are arranged in the respective circuit units so that the respective circuit units can be connected to the DC power supply via these strip power supply layouts. Basically, the strip power supply layout in each circuit unit is traversed on the opposite sides of the circuit unit (as shown in FIG. 1), so that when the respective circuit units are arranged adjacent to each other, the power supply layout of each circuit unit can be connected Together, the DC bias power supply is collectively collected. 1264662 For example, when designing an integrated circuit 12, if the circuit elements p(m) and p(M) are required in the integrated circuit 12, the designer can use the circuit unit P in the database 10. The layout design of P(M) is found and juxtaposed in the overall layout of the integrated circuit 12, so that the strip power supply layouts of the circuit units P(m) and P(M) are connected to each other. Next, the user can perform a routing program to appropriately connect the signals in the respective circuit units to the contacts/punches to combine the overall functions of the integrated circuits. As in the schematic example of FIG. 1, the winding procedure may use a specific winding layout rtO on the second metal layer to connect a certain contact/perforation of the circuit unit P(m) with the circuit unit P (M). A certain contact/perforation is connected so that the signal layouts in the two circuit units can be connected to each other and can exchange signals with each other to perform the overall function. After the winding layout of the winding program is completed, the overall layout design of the integrated circuit 12 can be completed, and the semiconductor integrated circuit can be actually fabricated by performing a semiconductor process. However, the above-mentioned prior art also has disadvantages. Its disadvantages n , ' γ 疋 疋 电路 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋The original intention of this layout design is to make ° + a special power supply layout, because the various circuit units are naturally connected to each other when they are arranged and combined to form an overall power supply cloth source in the integrated circuit. The strip power layout design also takes up quite a bit. — — j Back product, so that the height of the long circuit unit (that is, the distance between the two strip power supply layouts 1264662 shown in Figure i) cannot be reduced. The height of the circuit unit cannot be reduced, and the layout area of each circuit unit cannot be reduced, and the accumulation degree of the semiconductor body circuit cannot be effectively increased. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a preferred circuit layout implementation (design/manufacture) method in which a strip-shaped power supply layout is eliminated in each circuit unit to reduce the height of each circuit unit. And the area 'and can effectively increase the accumulation of semiconductor integrated circuits. In the present invention, the strip power supply layout in the prior art is replaced by a power contact/perforation of a grid point in each circuit unit. When designing the overall layout of the integrated circuit, the designer can select and arrange the required circuit elements, and then, in the winding procedure, wire-connect the power contacts in the respective circuit units. In other words, in the present invention, the circuit unit of the present invention does not need to be provided with a strip-shaped power supply layout; after each circuit unit is adjacently arranged, the power contacts/puncturing (grid power layout) of each circuit unit is not directly They are connected to each other, but are wound in the winding program to connect the power contacts/punches of the respective circuit units. Since the circuit unit of the present invention can eliminate the strip power supply layout, the present invention can effectively reduce the layout height and area of each circuit unit and improve the overall accumulation degree of the integrated circuit. In addition, in the modern semiconductor industry, the winding program is already a highly automated program, and the use of the winding program to form the power layout between the circuit units does not increase the complexity of the winding program, but also between the circuit units. The layout is more flexible and can no longer be limited to the existing strip power layout of each circuit unit as in the prior art. It can be seen with respect to existing processes that the present invention can reduce the height of each circuit unit more. For example, in the prior art, a circuit unit having a height of 1 pitch (a pitch of 0.28 micrometers in a .13 micron process) can be reduced to 8 pitches. Since the present invention can reduce the height (area) of the circuit unit, it is naturally possible to increase the accumulation degree of the integrated circuit and make full use of the layout area of the integrated circuit. [Embodiment] Please refer to Fig. 2; Fig. 2 is a schematic view showing (designing/manufacturing) a semiconductor integrated circuit by the circuit unit of the present invention. In the database 20 of the present invention, a layout design of a plurality of circuit units C(1), C(2)...C(n) to C(N) is also recorded; each circuit unit can be used as an integrated circuit. Basic building blocks. For example, each circuit unit can be a variety of logic gates, flip-flops, adders, counters, and the like in a digital circuit. In the design of the cloth 1246662 of each circuit unit, at least (but not limited to) the active area layout df (which may include changing wells and/or diffusion areas), polycrystalline eve layout pl, contact/punch layout Ct and the first metal layer layout_, the second metal layer layout mt2, and the like. The active area layout df / polycrystalline eve layout pl can form the basic structure of the transistor in each circuit unit 'contact / perforation layout etj connect the layout of different semiconductor layers, the pattern connects each transistor to the metal layer; and the metal layer The layout--(10) winding can connect the transistors in each circuit unit to the ship. Material, each circuit list: the signal input end and the output end of each Wei unit in a certain noise point/crossing axis, that is, the signal layout design. One of the focuses of the present invention, the ancient t Η — y 之 改 改 改 母 母 母 母 母 母 母 母 = = = = = = = = = = = = = = = = = = = 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔 穿孔As shown in the single μ diagram of the circuit, in the power supply layout pel L layout of the present invention, the layout of each circuit unit is pel, Ρ^, Γ, so that each circuit unit can be directly connected via these power sources. DC bias power supply (ρ叫, etc.. Such: Wd or two ground h voltage (such as voltage VSS), etc. to the two sides of the strip + ^ ^ in the mother circuit early 70 wipes out the cross-connected product. Read power layout In order to reduce the height of each circuit (10) and the surface 1246662 as shown in FIG. 2, when implementing the layout design of an integrated circuit 22 by the present invention, the designer may first select and apply according to the functional requirements of the integrated circuit 22. The circuit unit is then transferred from the database 20 to the layout design of the circuit unit. The layout of the integrated circuit 22 is applied to the layout design of the integrated circuit 22. Since each circuit unit of the present invention does not have a strip-shaped power supply layout, each circuit unit (assuming a circuit list After C(8) and C(N)) are adjacent to each other, their power supply layouts pci, Pc2 (that is, the power supply layout of the grid points) are not connected to each other. Next, in the winding procedure, each circuit unit can be used on the one hand. The signal layout (that is, the signal contact/perforation) is connected by winding, and on the other hand, the grid power layout of each circuit unit can be connected to the winding, so that not only the functions of the respective circuit units can be integrated. The integrated circuit 22 functions as intended, and the power supply layout between the respective circuit units can be connected. As in the schematic example of Fig. 2, the winding program connects the circuit unit C with the winding layout rt1. n), C (N) signal contacts / perforations, and the winding layout prl, pr2 to make the circuit elements c (n), C (N) power layout pcl, Pc2 can be connected to each power supply (like In other words, the present invention is a type of connection/perforation of the power supply layout of the grid points in each circuit unit, and the power supply dispersed in each circuit unit is uniformly unified in the winding program. Layout windings are connected to complete the integrated circuit Overall power supply layout. In the modern semiconductor industry, the winding procedure has been completed in 1364662 by means of an electronic automated design tool (EDA tool, Electronic Design Automation), so the invention does not increase. The complexity of the winding procedure. In fact, the winding arrangement of the power supply between the circuit units formed by the winding program can not only effectively reduce the height and area of each circuit unit, but also increase the design flexibility of the circuit layout. Conventional techniques are generally limited by the original strip-power layout of the various circuit elements. In the prior art, the strip power supply layout of each circuit unit is placed in the first metal layer; while the technology of the present invention is actually implemented. The second metal layer (metal 2) can be used to realize the power layout winding connection and the signal layout winding connection between the circuit units. Of course, the present invention can also utilize different metal layers to respectively realize the power layout winding connection and the signal layout winding connection between the circuit units. To further illustrate the advantages of the present invention, please refer to FIG. 3; FIG. 3 compares the circuit south of the circuit unit C0 of the present invention with the prior art circuit unit P0. Since the circuit of the present invention is changed to the power supply layout of the grid, the power supply layout of the grid can be reduced in the circuit unit, eliminating the height and area occupied by the strip power supply layout. In this way, the present invention can effectively reduce the height and area of each circuit unit, thereby increasing the degree of integration of the semi-conductor volume circuit. Comparing with practical examples, in the present invention, the height of the circuit unit (as indicated in FIG. 3) may include the distance between the first metal layers in the N-type 1466662 /P type MOS transistor. 1 pitches in NMOS/PMOS active area) 1.92 μm, plus spacing of metal 1 to metal 1 to 0 · 12 μm, the total height of the circuit unit is 2·04 μm The height of the circuit unit of the present invention is eight pitches, calculated as a pitch of 0·28 micrometers. In contrast, in the prior art, in addition to the above-mentioned basic height, the height of the strip power supply layout is additionally added, that is, it needs to occupy 0.35 micrometers at the P-type MOS transistor, in the N-type. The gold oxide semi-electrode needs to occupy another 0.35 micron, so the total height will increase to 2.04 + 0.35 + 0.35 two 2.74 micrometers, calculated by a pitch of 0.28 micrometers, and the total height of the circuit unit is 10 pitches. As can be seen from this example, the present invention can surely shorten the height of the circuit unit from the conventional 10 pitch to the 8 pitch, thereby increasing the degree of integration of the semiconductor integrated circuit. In summary, the present invention replaces the strip power supply layout of the conventional circuit unit with the power layout of the grid in each circuit unit, and the power supply layout of each circuit unit is connected in the winding program. Therefore, compared with the prior art, the present invention can effectively reduce the height and area of each circuit unit, thereby increasing the accumulation degree of the integrated circuit and making full use of the layout area of the integrated circuit. 1264662 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a conventional circuit in which a circuit unit realizes an integrated circuit. Fig. 2 is a diagram showing the sound circuit of the integrated circuit in the circuit unit of the present invention. Figure 3 is a schematic diagram showing the height comparison between the prior art circuit unit and the circuit unit of the present invention. [Main component symbol description] 10, 20 Database 12, 22 Integrated circuit layout P(1)-P(M), C(1)·C(N), P〇, c〇 circuit Cuiyuan pwl-pw2, pcl_pc2 Power layout Mtl-mt2 ct pi df rt0, rtl, prl, pr2 metal layer layout contact / perforation layout polycrystalline dream layout area layout winding layout