1264054 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種覆晶接合方法及覆晶接合結構，詳言 之係關於一種直接將晶片上之凸塊嵌入基板上之孔洞之 覆晶接合方法及覆晶接合結構。 【先前技術】 參考圖la至lc，顯示習用覆晶接合方法之步驟示意圖。 • 首先參考圖1a，提供一晶片1 〇，該晶片1 〇具有一線路面 11及一非線路面12，其中該線路面丨丨具有複數個晶片銲墊 每一晶片銲墊13上具有一凸塊14。 接著，提供一基板20，該基板20具有一上表面21及一下 表面22。該上表面21具有複數個基板銲墊23及一導電線路 層（圖中未示），該等基板銲墊23之位置係相對於該等凸塊 14 〇 接著’參考圖lb，對準該晶片10及該基板20，即以該晶 肇 片之線路面11面對該基板20上表面21，且將該等凸塊14 對準該等基板銲墊23。之後，壓合該晶片1〇及該基板2〇， 使得該等凸塊14接觸該等基板銲墊23。接著，再加熱該晶 ’ 片10及該基板20，使得該等凸塊14電氣連接至該等基板銲 、 墊23，此即迴銲製程。 接著，參考圖1 c，由於迴銲製程後，該晶片1 〇之線路面 Π與該基板20上表面21間會有一間隙之產生，在高温時晶 片10及基板20不同之熱膨脹係數會導致破壞，因此必須再 填充一底膠（underfill)30於該晶片10之線路面11與該基板 99046.doc 1264054 20上表面21間之間隙。如此，即完成習用之覆晶接合結構卜 上述之覆晶接合方式之缺點如下，第一，其必須填充該 底膠30,此-填充底膠之步驟，在實際操作上十分困難且 費時。第二，該晶片i 〇與該基板2 〇接合後之總高度不易縮 小，因為其中間具有該等凸塊14。第三，此種接合方式後 之接合強度不大’該晶片10與該基板2〇間容易產生橫向之 相對位移。 因此，有必要提供-種創新且具進步性的覆晶接合方法 及覆晶接合結構，以解決上述問題。 【發明内容】 本發明之目的在於提供—錄# 4 扠仏種覆晶接合方法及覆晶接合結 構’其係直接將晶片上之凸塊嵌入基板上之孔洞，因此不 需使用底膠’可省卻習用填充底膠之步驟，使製程更為簡 早。此外’可增加接合強度㈣小接合後之總高度。 為達上述目的，本發明提供—種覆晶接合方法，包括： ⑷提供-晶片，該晶片具有_線路面及一非線路面，其 中該線路面具有複數個凸塊； ⑻提供-基板，該基板具有_導電線路層及—接合層， 該接合層係位於該導電線路層上方，其具有複數個接:孔 洞’該等接合孔洞之位置及形狀係對應該等凸塊； ⑷對準該晶片及該基板，使得該等凸塊位於該等接合孔 洞内；及 ⑷加熱該晶片及該基板，使得料凸塊電氣連接至該 電線路層。 99046.doc 1264054 【實施方式】 參考圖2a及2b，顯示本發明薄曰 个土啊覆晶接合方法之步驟示意 圖。首先，參考圖2a，提供一曰Η 促1、日日片40，該晶片4〇具有一線 路面41及非線路面42，其中該線路面41具有複數個晶片 銲塾43，每-晶片鲜墊43上具有—凸塊44。該凸塊料之材 質可以是銅（Cu)或鉛（Pb)。 接著，提供一基板50(例如一電路板或1264054 IX. Description of the Invention: [Technical Field] The present invention relates to a flip chip bonding method and a flip chip bonding structure, and more particularly to a flip chip bonding of a hole directly embedded in a bump on a wafer Method and flip chip bonding structure. [Prior Art] Referring to Figures la to lc, a schematic diagram of the steps of a conventional flip chip bonding method is shown. Referring first to FIG. 1a, a wafer 1 is provided having a line surface 11 and a non-line surface 12, wherein the line surface has a plurality of wafer pads each having a bump on the pad 13 14. Next, a substrate 20 is provided having an upper surface 21 and a lower surface 22. The upper surface 21 has a plurality of substrate pads 23 and a conductive circuit layer (not shown). The substrate pads 23 are positioned relative to the bumps 14 and then referenced to FIG. 10 and the substrate 20, that is, the circuit surface 11 of the wafer is faced to the upper surface 21 of the substrate 20, and the bumps 14 are aligned with the substrate pads 23. Thereafter, the wafer 1 and the substrate 2 are pressed together such that the bumps 14 contact the substrate pads 23. Then, the crystal film 10 and the substrate 20 are further heated, so that the bumps 14 are electrically connected to the substrate pads and pads 23, which is a reflow process. Next, referring to FIG. 1c, after the reflow process, there is a gap between the line surface of the wafer 1 and the upper surface 21 of the substrate 20. The thermal expansion coefficient of the wafer 10 and the substrate 20 may cause damage at high temperatures. Therefore, an underfill 30 must be further filled in the gap between the wiring surface 11 of the wafer 10 and the upper surface 21 of the substrate 99046.doc 1264054 20. Thus, the conventional flip chip bonding structure has the following disadvantages. First, it must be filled with the primer 30. This step of filling the primer is very difficult and time consuming in practice. Second, the total height of the wafer i 〇 after bonding to the substrate 2 is not easily reduced because the bumps 14 are present in between. Third, the bonding strength after such bonding is not large. The lateral displacement of the wafer 10 and the substrate 2 is likely to occur. Therefore, it is necessary to provide an innovative and progressive flip chip bonding method and a flip chip bonding structure to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for flip chip bonding and a flip chip bonding structure, which directly inserts bumps on a wafer into holes in a substrate, so that no primer can be used. It eliminates the need to use the step of filling the primer to make the process easier. In addition, the joint strength (4) can be increased after the small joint. To achieve the above object, the present invention provides a flip chip bonding method, comprising: (4) providing a wafer having a _ line surface and a non-line surface, wherein the line surface has a plurality of bumps; (8) providing a substrate, The substrate has a conductive layer and a bonding layer, and the bonding layer is located above the conductive circuit layer, and has a plurality of connections: holes, positions and shapes of the bonding holes corresponding to the bumps; (4) aligning the wafer And the substrate such that the bumps are located in the bonding holes; and (4) heating the wafer and the substrate such that the bumps are electrically connected to the electrical wiring layer. 99046.doc 1264054 [Embodiment] Referring to Figures 2a and 2b, there are shown schematic diagrams of the steps of the method for bonding a thin layer of earth in the present invention. First, referring to Fig. 2a, a stencil 1 is provided. The wafer 4 has a line surface 41 and a non-line surface 42. The line surface 41 has a plurality of wafer pads 43 and a mat for each wafer. 43 has a bump 44. The material of the bump material may be copper (Cu) or lead (Pb). Next, a substrate 50 is provided (such as a circuit board or
晶圓），該基板 50具有-導電線路層51。該導電線路層$ i之材質較佳 銅。接著，形成一接合層52於該導電線路層^上方，該接 合層52具有複數個接合孔㈣，該接合層52係為絕緣體且 為熱傳導體’該等接合孔洞53之位置及形狀係對應該等凸 塊44 〇 在一較佳實施例中，更包括—形成_第_導電材料6〇於 該等接合孔洞53内之步驟，其中該第—導電材料6()之高度 係小於該等接合孔洞53之高度，亦即，該第一導電材料6〇 不填滿該接合孔洞53。同時該第一導電材料6〇之材質較佳 係為銅且係電氣連接至該導電線路層51。接著，再形成一 預銲材料（Pre-S〇lder)70於該第一導電材料6〇上方。至此， 要注意的是，該等凸塊44之體積較佳地係為該接合孔洞” 内扣除該第一導電材料60及該預銲材料7〇之體積。 接著，參考圖2b，對準該晶片40及該基板5〇,即以該晶 片40之線路面41面對該基板5〇之接合層52，且將該等凸塊 44對準該等接合孔洞53。之後，壓合該晶片牝及該基板⑽， 使得該等凸塊44位於該等接合孔洞53内。接著，再加熱該 99046.doc 1264054 晶片40及該基板50，該預銲材料7〇融化使得該等凸塊44電 氣連接至該第一導電材料60，進而電氣連接至該導電線路 層5 1。如此，即完成本發明之覆晶接合結構4。 在其他應用中’該基板50之接合層52更具有複數個導電 孔洞80,因此本發明更包括一形成一第二導電材料81於該 等導電孔洞80内之步驟，其中該第二導電材料81係填滿該 等導電孔洞80，用以透過其上之接墊82而電氣連接該導電 線路層5 1及一外部元件（圖中未示）。 再參考圖2b，本發明之覆晶接合結構i，包括一晶片4〇 及一基板50。該晶片40具有一線路面41及一非線路面42， 其中該線路面41具有複數個凸塊44。該基板5〇(例如一電路 板或一晶圓）具有一導電線路層51及一接合層52，該接合層 52係位於該導電線路層51上方，其具有複數個接合孔洞 53，該等接合孔洞53之位置及形狀係對應該等凸塊料，以 容置該等凸塊44，且使得該等凸塊44電氣連接至該導電線 路層51。 較佳地，該等接合孔洞53内更包括—第—導電材料的及 -預銲材料70,該第—導電材料6()之高度係小於該等接合 孔洞53之高度，且該第—導電材⑽係電氣連接至該導電 線路層51，該預銲材料7〇係於該第一導電材料6〇上方該 等凸塊44係連接該預銲材料7〇。 較佳地’該基板5G更具有複數個導電孔洞，該等導電 孔洞80内更包括一第二導雷鉍 乐导電材枓81，其中該第二導電材料 8 1係填滿該等導電孔洞川，兮 — 且°亥弟一導電材料81係用以電 99046.doc 1264054 氣連该導電線路層51及-外部元件(圖中未示)。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不違背本發 月之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖4至1(：顯示習用覆晶接合方法之步驟示意圖；及 圖2a及2b顯示本發明覆晶接合方法之步驟示音圖。 【主要元件符號說明】 1 習用之覆晶接合結構 4 本發明之覆晶接合結構 10 晶片 11 線路面 12 非線路面 13 晶片鮮塾 14 凸塊 20 基板 21 上表面 22 下表面 23 基板銲墊 30 底膠 40 晶片 41 線路面 42 非線路面 99046.doc 1264054 43 44 50 51 52 53 60 70 80 81 82 晶片銲墊 凸塊 基板 導電線路層 接合層 接合孔洞 第一導電材料 預銲材料 導電孔洞 第二導電材料 接墊 99046.doc -10Wafer), the substrate 50 has a conductive layer 51. The material of the conductive circuit layer $i is preferably copper. Next, a bonding layer 52 is formed over the conductive wiring layer. The bonding layer 52 has a plurality of bonding holes (4). The bonding layer 52 is an insulator and is a thermal conductor. The positions and shapes of the bonding holes 53 correspond to each other. The bumps 44, in a preferred embodiment, further include the step of forming a -first conductive material 6 in the bonding holes 53, wherein the height of the first conductive material 6() is less than the bonding The height of the hole 53, that is, the first conductive material 6〇 does not fill the joint hole 53. At the same time, the material of the first conductive material 6 is preferably copper and electrically connected to the conductive circuit layer 51. Next, a pre-soldering material 70 is formed over the first conductive material 6?. At this point, it should be noted that the volume of the bumps 44 is preferably the volume of the first conductive material 60 and the pre-solder material 7〇 in the bonding hole. Next, referring to FIG. 2b, the alignment is performed. The wafer 40 and the substrate 5 are faced with the bonding layer 52 of the substrate 5 with the wiring surface 41 of the wafer 40, and the bumps 44 are aligned with the bonding holes 53. Thereafter, the wafer is pressed. And the substrate (10) such that the bumps 44 are located in the bonding holes 53. Then, the 99046.doc 1264054 wafer 40 and the substrate 50 are reheated, and the pre-solder material 7 is melted so that the bumps 44 are electrically connected. The first conductive material 60 is electrically connected to the conductive circuit layer 51. Thus, the flip chip bonding structure 4 of the present invention is completed. In other applications, the bonding layer 52 of the substrate 50 has a plurality of conductive holes. 80. Therefore, the present invention further includes a step of forming a second conductive material 81 in the conductive vias 80, wherein the second conductive material 81 fills the conductive vias 80 for the pads 82 therethrough. Electrically connecting the conductive circuit layer 51 and an external component ( Referring again to FIG. 2b, the flip chip bonding structure i of the present invention includes a wafer 4 and a substrate 50. The wafer 40 has a wiring surface 41 and a non-line surface 42, wherein the wiring surface 41 has a plurality of bumps 44. The substrate 5 (for example, a circuit board or a wafer) has a conductive circuit layer 51 and a bonding layer 52, and the bonding layer 52 is located above the conductive circuit layer 51, and has a plurality of bonding The holes 53 are positioned and shaped to correspond to the bumps to accommodate the bumps 44, and the bumps 44 are electrically connected to the conductive circuit layer 51. Preferably, the holes The first bonding hole 53 further includes a first conductive material and a pre-soldering material 70. The height of the first conductive material 6() is smaller than the height of the bonding holes 53, and the first conductive material (10) is electrically connected. To the conductive circuit layer 51, the pre-soldering material 7 is attached to the first conductive material 6〇. The bumps 44 are connected to the pre-solder material 7〇. Preferably, the substrate 5G has a plurality of conductive holes. The conductive holes 80 further include a second conductive material 81, wherein the second conductive material 81 is filled with the conductive holes, and the conductive material 81 is used to electrically connect the conductive circuit layer 51 and the external components (Fig. However, the above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Therefore, those skilled in the art can carry out the above embodiments without departing from the spirit of the present invention. Modifications and variations. The scope of the invention should be as set forth in the appended claims. [FIG. 4 to 1 (: shows a schematic diagram of the steps of a conventional flip chip bonding method; and FIGS. 2a and 2b show the invention. A step diagram of the steps of the crystal bonding method. [Main component symbol description] 1 conventional flip chip bonding structure 4 flip chip bonding structure 10 of the present invention wafer 11 wiring surface 12 non-line surface 13 wafer fresh 塾 14 bump 20 substrate 21 upper surface 22 lower surface 23 substrate pad 30 Primer 40 Wafer 41 Line surface 42 Non-line surface 99046.doc 1264054 43 44 50 51 52 53 60 70 80 81 82 Wafer pad bump substrate conductive circuit layer bonding layer bonding hole first conductive material pre-solder material conductive hole second Conductive material pad 90946.doc -10