TWI261296B - Method of fabricating an array substrate for an OLED - Google Patents

Abstract

The invention discloses a method of fabricating an array substrate for an OLED. The method comprises providing a substrate including a light emitting region and a circuit region. An active device is formed on the circuit region. A passivation layer is formed over the active device and the substrate by plasma-enhanced chemical vapor deposition (PECVD). A pixel electrode is formed on the passivation layer, electrically connecting to the active device. A pixel define layer is formed over the pixel electrode by plasma chemical vapor deposition. An annealing treatment is performed prior to formation of an OLED on the light emitting region.

Description

1261296 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a method of fabricating an organic light emitting diode display, and more particularly to a method of fabricating an organic light emitting diode array substrate. [Prior Art]

The array substrate of the white light and the LED display can be distinguished as the light-emitting area. The method for manufacturing an array substrate of the above organic light-emitting diode display mainly comprises: forming an <in film transistor; TFT) dimorphic element electrode, and forming an organic light emitting diode. Among them, the process of the fine crystal usually comprises the following steps: forming a buffer layer 'polycrystalline complement, interpole, bar, water layer gate, interlayer dielectric layer on the entire surface of the substrate. After the completion of the thin film transistor, a halogen electrode (transparent anode) is subsequently formed, and the halogen electrode is electrically connected to the thin film transistor. Thereafter, an organic light-emitting layer (EL) and a reflective cathode are formed on the light-emitting region to complete the fabrication of the organic light-emitting diode. In the above-mentioned Fangcai, the secret society _ t learning her touch (piasma_entaeed cvd; PECVD) to form the aforementioned relevant film layer, so the array of organic light-emitting diode display on the surface of the stomach plate double-slit crystal structure The towel, which in turn affects the properties of the component. [Inventive content] In accordance with the purpose of the present invention, the method of suppressing the il in the above-mentioned -providing-light-emitting diodes is improved in the manner of side annealing treatment to improve charge accumulation on the array substrate. Happening. The present invention provides a substrate for the organic light-emitting diode array substrate. A substrate is provided, which is divided into a light-emitting region and a circuit region. Forming in the circuit area - active ♦ simplified vapor deposition (PE) or other chemical gases

0773-A31742TWF 5 !261296 phase deposition method to form a javier layer on the active device and the bismuth plate to form a ruthenium electrode on the protective layer, wherein the ruthenium electrode And the formation of a chemical vapor deposition (PECVD) or other chemical gas accumulation method and a pixel define layer on the pixel electrode. An organic electroluminescent element is formed on the light-emitting region of the substrate. At the office. In this, the hair _ use annealing _ way, can improve the cause of the above-mentioned green wind deposition method silk wire layer and pixel definition (four) charm excess f poly electricity ^ film field 1 shellfish, eve day noise The problem of defects (such as rabbits... she) caused by the layer structure.

The above and other objects, aspects and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The figure is a cross-sectional view of a process of an organic light emitting diode array substrate (10) according to a comparative example. The method comprises the following main steps: First, as shown in Fig. 1A, a substrate 1〇1 is provided which is divided into a light-emitting region 1 and a circuit region c. Next, a buffer (four) 3 is formed on the substrate 101. Next, an active element is formed in the above circuit region c, including a polycrystalline second layer 1〇5, an interpolar insulating layer 1〇7, a gate (1), a layer: a layer 109, and a data line 113. 5 Electricity Next, as shown in Figs. 1B and 1c, a protective layer (4) is formed by plasma chemical vapor deposition (m_mwnhanCed CVD; PECW) to form a protective layer (4)-on ^(4)(10) above the active 7L member and the substrate ωΐ. In other embodiments, the above protective layer 1 forming method includes other chemical vapor deposition methods. Wherein, the protective layer U9 includes an oxide. After reading the above-mentioned Lai fresh gas, I read the Wei Mo charge from the contact surface.

Larger metal electrodes (such as data line 113) are collected and conducted and deposited in areas such as polycrystalline milk and idler insulating layer 107, affecting the operational performance of the component. 0773-A31742TWF 6 1261296 Next, as shown in the ID diagram, a pixel electrode (as an anode) (2) is formed over the above protective layer W. The pixel element 121 is electrically connected to the active body by the data line ιΐ3. Next, as shown in FIGS. 1E and 1F, the plasma chemical vapor deposition method i23 (pEcvD) is used to form a pixd defme layer (PDL) 125 on the pixel electrode (2). In the embodiment, the method for forming the pixel defining layer m described above includes other chemical vapor deposition methods. (4) After the above-mentioned electric chemical vapor deposition step, the excess electric charge is also collected and transported through the data line 113 to the polycrystalline stone layer 105 and the gate electrode and the s-s edge layer by the above-mentioned halogen electrode 121 having a large contact area. In areas such as 107, it affects the operational performance of components. Next, as shown in FIG. 1G, the organic light-emitting layer 129 is sequentially formed on the light-emitting region L, and the electron beam diode current on the organic light-emitting diode array substrate of the first FIG. The relationship diagram of the change of the gate electric dust (Vg), wherein the γ axis is the buckle current (the X axis is the compliant (Vg). Among them, the above organic light emitting diode array can be a plurality of panels, and the first 2 _ Randomly select any of the different sinking transistors on different panels, = the relationship between the recording current (Id) and the change of the gate dragon (Vg). From Fig. 2, the difference between the different curves is very large. That is to say, the method of the comparative example is manufactured on: The characteristics of the (10) transistor on the photodiode _ substrate are not uniform __. Thus - the second affects the operational performance of the overall component. FIG. 1G is a diagram showing the relationship between the pM〇s secret current (Id) and the gate voltage (Vg) on the organic light-emitting diode array substrate, wherein the axis current is ¥

The X axis is _pressure (Vg). Among them, the above-mentioned bribe-light diode array can cut a plurality of sulfur, and the third figure is any pM〇s transistor on different tons, _ its non-polar current (Id) with gate voltage (Vg) The relationship diagram of the change. From Fig. 3, the difference between the different curves can be very large, that is, the pMQS electro-crystal characteristics on the photodiode array substrate manufactured by the method of the comparative example are not uniform. Thus, / 0773-A31742TWF 7 1261296 affects the operational performance of the overall device. Embodiments 4A to 4H illustrate a process sectional view of an organic light emitting diode array substrate 200 according to the present invention. First, as shown in Fig. 4A, the substrate-substrate 2 is divided into a light-emitting region L and a circuit region C. Next, a buffer layer 2〇3 is formed on the substrate 201. Next, an active element is formed in the above-described circuit region c, including a polycrystalline layer 205, a gate insulating layer 2?7, an interpole m, an interlayer dielectric layer 209, and a data line 213. Next, as shown in Figs. 4B and 4C, a protective layer (p-layer) 219 is formed on the active device and the substrate 2 by using a plasma chemical vapor deposition method 2i5 (pEcvD). In other embodiments, the protective layer 219 ❺ formation method includes other chemical vapor deposition methods. Wherein the above protective layer 219 includes an oxide or a nitride. After the above-mentioned plasma chemical vapor deposition step, the excess plasma charge is captured by the metal electrode of the contact surface (eg, the data line is collected and conducted and deposited to the polycrystalline pin 2〇5 and the gate is absolutely closed; The performance of the flying hopper is as shown in the 4D figure of 'the formation of a halogen electrode (as an anode) 221 above the protective layer 9. The above-mentioned halogen electrode 221 ^ 曰 is electrically connected. W2U and the above-mentioned active components open 4F riding 'pure plasma chemical vapor deposition method such as (PECVD). Ϊ ^ ^ ♦ a P_5 in the above-mentioned halogen electrode work six, /, 匕 only _, the above The method for forming the pixel defining layer 225 includes other chemical vapor deposition methods. After the above-mentioned Thunderjin powder is applied to the milk phase, the above contact area is large: After the step of the special product, the excess plasma charge is also passed through 2〇. 5 and the interpolar insulation layer 2〇7 denier (3) is collected and transmitted through the data line 213 to the polycrystalline stone layer P 九 domain 'influencing the element's performance. No. 4G diagram, no-annealing 226. Annealing Processing can be done in a vacuum

0773-A31742TWF 8 1261296. It is carried out in a gas having 3 Wei, 1111, or argon gas. The annealing treatment may be carried out at 'fumaee' or in the middle of annealing, and may be carried out under Bin to Fu, and may be carried out for 15 minutes to (four) minutes. For example, the retort is carried out in a furnace containing a gas (0°) at a temperature of up to 24 minutes. After the above annealing treatment 226, the excessive accumulated charge in the region of the gate oxide layer and the polycrystalline stone can be eliminated, and the defect state caused by the repair can be eliminated (4) (10)

She), the above-mentioned causes of the box caused the Lai (10) to slap the definition layer «The plasma "defect state" caused by the accumulation of polycrystalline shop and oxide layer. Heart Next As shown in Fig. 4H, an organic light-emitting layer 22 and a cathode 231 are formed on the light-emitting region L. Figure 5 is a diagram showing the relationship between the gate current (Id) and the gate voltage (Vg) of the galvanic crystal on the organic light-emitting diode array substrate of the 4Hth diagram, wherein the γ-axis is immersed. Current (6) and X-axis are _« (Vg). Wherein, the organic light-emitting diode array board can be cut into a plurality of panels, and the fifth picture randomly selects any touch (10) transistor on different panels, and measures its no-pole current (Id) with the idle voltage (W). The relationship diagram obtained by the change. It can be seen from Fig. 5 that the difference between the two different curves is very small, and the characteristics of the S-transistor on the organic photodiode array substrate manufactured by the method of the embodiment are as follows. Quite uniform, significantly improved overall performance. Figure 6 is a diagram showing the relationship between the gate electric version (Id) and the gate electrode (%) of the pMOS transistor on the organic light-emitting diode array substrate of the 4Hth image, wherein the Y-axis is not The pole current (6) and the = axis are the gates (Vg). Wherein, the organic light emitting diode array substrate can be cut into a plurality of panels, and the sixth image randomly selects any pM〇s transistors on different panels to test the inhomogeneous current (Id) of the interpolar current ( ^) The change is obtained. It can be seen from Fig. 6 that the difference between the different curves is very small, that is to say, the organic hair produced by the method of the embodiment

0773-A31742TWF 9 1261296 The characteristics of the ipM〇S transistor on the bulk array substrate are quite uniform, and the operation of the component is significantly improved. The present invention has been disclosed in several preferred embodiments as above, but it is not intended to limit the present invention. The invention may be made by any person skilled in the art without departing from the spirit and scope of the invention. The scope of protection of the invention is defined by the scope of the appended claims. 1A to 1G are diagrams showing a process of an organic light-emitting diode array substrate according to a comparative example. μ 仏, 曰 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第Diagram of the relationship between the gate current (Vg) of the drain current (Id). Figure 3 shows the electrodeless current (Id) of the PM〇S transistor on the organic light-emitting diode array substrate of Figure 1G. FIG. 4A to FIG. 4H are schematic cross-sectional views showing a process of an organic light emitting diode array substrate according to a preferred embodiment of the present invention. The ancestors on the organic light-emitting diode array substrate of FIG. 4H Diagram of the relationship between the electrodeless current (Id) of the transistor and the gate voltage (Vg). Fig. 6 is a diagram of the OLED of the OLED array on the organic light-emitting diode array substrate of Figure 4H. Diagram of the relationship between the polar current (Id) and the voltage (Vg). [Main component symbol description] 1〇1~substrate; 1〇5~ polysilicon layer; 109~ interlayer dielectric layer; U3~ data line; 100~organic Light-emitting diode array substrate; 103~ buffer layer; 107~ gate insulating layer; 111~ gate;

0773-A31742TWF 10 1261296 115~plasma chemical vapor deposition method; 119~protective layer; 123~plasma chemical vapor deposition method; 129~organic light-emitting layer; 200~organic light-emitting diode array substrate; 203~buffer layer ; 207 ~ gate insulating layer; 211 ~ gate; 215 ~ plasma chemical vapor deposition; 219 ~ protective layer; 223 ~ plasma chemical vapor deposition; 226 ~ annealing treatment; 231 ~ cathode; Area. 117 ~ plasma charge; 121 ~ halogen electrode, 125 ~ halogen definition layer; 131 ~ cathode; 201 ~ substrate; 205 ~ polysilicon layer; 209 ~ interlayer dielectric layer; 213 ~ data line; 217 ~ plasma charge; 221 ~ pixel electrode; 225 ~ halogen definition layer; 229 ~ organic light-emitting layer; C ~ circuit area,

0773-A31742TWF

Claims (1)

^61296 X. Patent Application Range: ^ A method for manufacturing an organic light emitting diode array substrate, comprising the steps of: providing a substrate, which is divided into a light emitting region and a circuit region; forming an active component in the circuit region; Plasma chemical vapor deposition (PECVD) to form a protective layer 1 (10) haiku on the active device and the substrate; forming a halogen electrode on the protective layer, wherein the pixel electrode The active device is electrically connected; 乂^ _ is formed into a pixel define layer on the halogen electrode; performing an annealing treatment; and forming an organic light-emitting layer and a cathode on the edge light-emitting region . 2. The method of manufacturing an organic light-emitting diode array substrate according to claim 1, wherein the method for forming the halogen-defined layer further comprises a plasma chemical vapor deposition method. 3. The method of fabricating an organic light-emitting diode array substrate according to claim 1, wherein the annealing treatment is performed in a vacuum, oxygen, nitrogen, or argon. 4. The method of manufacturing an organic light-emitting diode array substrate according to the invention of claim 2, wherein the annealing treatment comprises rapid annealing treatment (RTA), carried out in a high temperature furnace tube (four), or in a furnace ( In the oven). 5. The method for manufacturing an organic light-emitting diode_substrate according to the scope of the patent application, wherein the annealing treatment is carried out at 2 〇 (rC to 650). 6. For example, the patent model 1|| The method for fabricating an organic light-emitting diode substrate according to the above aspect, wherein the annealing treatment is performed for 15 minutes to 24 minutes. The method of the organic light-emitting diode array substrate according to the item of claim 2, The protective layer of the nano layer includes an oxide or a nitride. 8. The organic light-emitting diode array method according to the scope of claim 2, wherein the plain layer comprises oxygen recording. &quot; 0773-A31742TWF 12 1261296 9. The manufacturing method of the organic light emitting diode array substrate comprises the following steps: providing a substrate, dividing into a light emitting region and a circuit region; forming an active component in the delta circuit region; forming a protective layer on the active component and the Above the substrate; forming a halogen electrode on the protective layer, wherein the halogen is connected; the electrode is formed with the active element The layer is formed on the halogen electrode by plasma chemical vapor deposition (PECVD); an annealing treatment is performed; and an organic light-emitting layer and a cathode are formed on the light-emitting region. 4 〇 〇 如 申请 如 如 如 如 如 如 如 如 如 如 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ 11. The method for manufacturing an organic light-emitting diode array substrate according to claim 9, wherein the ship fire treatment comprises a quick turn (TA), in a high temperature furnace tube (four), or in an oven (oven) In progress. The method for producing an organic light-emitting diode array substrate according to claim 9, wherein the annealing treatment is performed at 2 Å. (: to 65 〇. (: proceeding below. I3 · For example, the application method of the organic light-emitting diode array substrate described in the second paragraph of the application, the towel annealing process is 15 minutes light, minute The method for fabricating an organic light-emitting diode array substrate according to the above item 9, wherein the layer comprises an oxide or a nitride. 15' The organic light according to claim 9 A method of manufacturing a diode array substrate, wherein the halogen defining layer comprises an oxide. 0773-A31742TWF 13